1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
16 #include <linux/msi.h>
18 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/logic_pio.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
33 #include <linux/aer.h>
34 #include <linux/bitfield.h>
37 DEFINE_MUTEX(pci_slot_mutex);
39 const char *pci_power_names[] = {
40 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
42 EXPORT_SYMBOL_GPL(pci_power_names);
45 int isa_dma_bridge_buggy;
46 EXPORT_SYMBOL(isa_dma_bridge_buggy);
50 EXPORT_SYMBOL(pci_pci_problems);
52 unsigned int pci_pm_d3hot_delay;
54 static void pci_pme_list_scan(struct work_struct *work);
56 static LIST_HEAD(pci_pme_list);
57 static DEFINE_MUTEX(pci_pme_list_mutex);
58 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
60 struct pci_pme_device {
61 struct list_head list;
65 #define PME_TIMEOUT 1000 /* How long between PME checks */
67 static void pci_dev_d3_sleep(struct pci_dev *dev)
69 unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay);
73 /* Use a 20% upper bound, 1ms minimum */
74 upper = max(DIV_ROUND_CLOSEST(delay_ms, 5), 1U);
75 usleep_range(delay_ms * USEC_PER_MSEC,
76 (delay_ms + upper) * USEC_PER_MSEC);
80 bool pci_reset_supported(struct pci_dev *dev)
82 return dev->reset_methods[0] != 0;
85 #ifdef CONFIG_PCI_DOMAINS
86 int pci_domains_supported = 1;
89 #define DEFAULT_CARDBUS_IO_SIZE (256)
90 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
91 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
92 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
93 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
95 #define DEFAULT_HOTPLUG_IO_SIZE (256)
96 #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024)
97 #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024)
98 /* hpiosize=nn can override this */
99 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
101 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
102 * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size;
103 * pci=hpmemsize=nnM overrides both
105 unsigned long pci_hotplug_mmio_size = DEFAULT_HOTPLUG_MMIO_SIZE;
106 unsigned long pci_hotplug_mmio_pref_size = DEFAULT_HOTPLUG_MMIO_PREF_SIZE;
108 #define DEFAULT_HOTPLUG_BUS_SIZE 1
109 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
112 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
113 #ifdef CONFIG_PCIE_BUS_TUNE_OFF
114 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
115 #elif defined CONFIG_PCIE_BUS_SAFE
116 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE;
117 #elif defined CONFIG_PCIE_BUS_PERFORMANCE
118 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE;
119 #elif defined CONFIG_PCIE_BUS_PEER2PEER
120 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PEER2PEER;
122 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
126 * The default CLS is used if arch didn't set CLS explicitly and not
127 * all pci devices agree on the same value. Arch can override either
128 * the dfl or actual value as it sees fit. Don't forget this is
129 * measured in 32-bit words, not bytes.
131 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
132 u8 pci_cache_line_size;
135 * If we set up a device for bus mastering, we need to check the latency
136 * timer as certain BIOSes forget to set it properly.
138 unsigned int pcibios_max_latency = 255;
140 /* If set, the PCIe ARI capability will not be used. */
141 static bool pcie_ari_disabled;
143 /* If set, the PCIe ATS capability will not be used. */
144 static bool pcie_ats_disabled;
146 /* If set, the PCI config space of each device is printed during boot. */
149 bool pci_ats_disabled(void)
151 return pcie_ats_disabled;
153 EXPORT_SYMBOL_GPL(pci_ats_disabled);
155 /* Disable bridge_d3 for all PCIe ports */
156 static bool pci_bridge_d3_disable;
157 /* Force bridge_d3 for all PCIe ports */
158 static bool pci_bridge_d3_force;
160 static int __init pcie_port_pm_setup(char *str)
162 if (!strcmp(str, "off"))
163 pci_bridge_d3_disable = true;
164 else if (!strcmp(str, "force"))
165 pci_bridge_d3_force = true;
168 __setup("pcie_port_pm=", pcie_port_pm_setup);
170 /* Time to wait after a reset for device to become responsive */
171 #define PCIE_RESET_READY_POLL_MS 60000
174 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
175 * @bus: pointer to PCI bus structure to search
177 * Given a PCI bus, returns the highest PCI bus number present in the set
178 * including the given PCI bus and its list of child PCI buses.
180 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
183 unsigned char max, n;
185 max = bus->busn_res.end;
186 list_for_each_entry(tmp, &bus->children, node) {
187 n = pci_bus_max_busnr(tmp);
193 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
196 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
197 * @pdev: the PCI device
199 * Returns error bits set in PCI_STATUS and clears them.
201 int pci_status_get_and_clear_errors(struct pci_dev *pdev)
206 ret = pci_read_config_word(pdev, PCI_STATUS, &status);
207 if (ret != PCIBIOS_SUCCESSFUL)
210 status &= PCI_STATUS_ERROR_BITS;
212 pci_write_config_word(pdev, PCI_STATUS, status);
216 EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors);
218 #ifdef CONFIG_HAS_IOMEM
219 static void __iomem *__pci_ioremap_resource(struct pci_dev *pdev, int bar,
222 struct resource *res = &pdev->resource[bar];
223 resource_size_t start = res->start;
224 resource_size_t size = resource_size(res);
227 * Make sure the BAR is actually a memory resource, not an IO resource
229 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
230 pci_err(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
235 return ioremap_wc(start, size);
237 return ioremap(start, size);
240 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
242 return __pci_ioremap_resource(pdev, bar, false);
244 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
246 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
248 return __pci_ioremap_resource(pdev, bar, true);
250 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
254 * pci_dev_str_match_path - test if a path string matches a device
255 * @dev: the PCI device to test
256 * @path: string to match the device against
257 * @endptr: pointer to the string after the match
259 * Test if a string (typically from a kernel parameter) formatted as a
260 * path of device/function addresses matches a PCI device. The string must
263 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
265 * A path for a device can be obtained using 'lspci -t'. Using a path
266 * is more robust against bus renumbering than using only a single bus,
267 * device and function address.
269 * Returns 1 if the string matches the device, 0 if it does not and
270 * a negative error code if it fails to parse the string.
272 static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,
276 unsigned int seg, bus, slot, func;
280 *endptr = strchrnul(path, ';');
282 wpath = kmemdup_nul(path, *endptr - path, GFP_ATOMIC);
287 p = strrchr(wpath, '/');
290 ret = sscanf(p, "/%x.%x%c", &slot, &func, &end);
296 if (dev->devfn != PCI_DEVFN(slot, func)) {
302 * Note: we don't need to get a reference to the upstream
303 * bridge because we hold a reference to the top level
304 * device which should hold a reference to the bridge,
307 dev = pci_upstream_bridge(dev);
316 ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot,
320 ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end);
327 ret = (seg == pci_domain_nr(dev->bus) &&
328 bus == dev->bus->number &&
329 dev->devfn == PCI_DEVFN(slot, func));
337 * pci_dev_str_match - test if a string matches a device
338 * @dev: the PCI device to test
339 * @p: string to match the device against
340 * @endptr: pointer to the string after the match
342 * Test if a string (typically from a kernel parameter) matches a specified
343 * PCI device. The string may be of one of the following formats:
345 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
346 * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
348 * The first format specifies a PCI bus/device/function address which
349 * may change if new hardware is inserted, if motherboard firmware changes,
350 * or due to changes caused in kernel parameters. If the domain is
351 * left unspecified, it is taken to be 0. In order to be robust against
352 * bus renumbering issues, a path of PCI device/function numbers may be used
353 * to address the specific device. The path for a device can be determined
354 * through the use of 'lspci -t'.
356 * The second format matches devices using IDs in the configuration
357 * space which may match multiple devices in the system. A value of 0
358 * for any field will match all devices. (Note: this differs from
359 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
360 * legacy reasons and convenience so users don't have to specify
361 * FFFFFFFFs on the command line.)
363 * Returns 1 if the string matches the device, 0 if it does not and
364 * a negative error code if the string cannot be parsed.
366 static int pci_dev_str_match(struct pci_dev *dev, const char *p,
371 unsigned short vendor, device, subsystem_vendor, subsystem_device;
373 if (strncmp(p, "pci:", 4) == 0) {
374 /* PCI vendor/device (subvendor/subdevice) IDs are specified */
376 ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device,
377 &subsystem_vendor, &subsystem_device, &count);
379 ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count);
383 subsystem_vendor = 0;
384 subsystem_device = 0;
389 if ((!vendor || vendor == dev->vendor) &&
390 (!device || device == dev->device) &&
391 (!subsystem_vendor ||
392 subsystem_vendor == dev->subsystem_vendor) &&
393 (!subsystem_device ||
394 subsystem_device == dev->subsystem_device))
398 * PCI Bus, Device, Function IDs are specified
399 * (optionally, may include a path of devfns following it)
401 ret = pci_dev_str_match_path(dev, p, &p);
416 static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
417 u8 pos, int cap, int *ttl)
422 pci_bus_read_config_byte(bus, devfn, pos, &pos);
428 pci_bus_read_config_word(bus, devfn, pos, &ent);
440 static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
443 int ttl = PCI_FIND_CAP_TTL;
445 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
448 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
450 return __pci_find_next_cap(dev->bus, dev->devfn,
451 pos + PCI_CAP_LIST_NEXT, cap);
453 EXPORT_SYMBOL_GPL(pci_find_next_capability);
455 static u8 __pci_bus_find_cap_start(struct pci_bus *bus,
456 unsigned int devfn, u8 hdr_type)
460 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
461 if (!(status & PCI_STATUS_CAP_LIST))
465 case PCI_HEADER_TYPE_NORMAL:
466 case PCI_HEADER_TYPE_BRIDGE:
467 return PCI_CAPABILITY_LIST;
468 case PCI_HEADER_TYPE_CARDBUS:
469 return PCI_CB_CAPABILITY_LIST;
476 * pci_find_capability - query for devices' capabilities
477 * @dev: PCI device to query
478 * @cap: capability code
480 * Tell if a device supports a given PCI capability.
481 * Returns the address of the requested capability structure within the
482 * device's PCI configuration space or 0 in case the device does not
483 * support it. Possible values for @cap include:
485 * %PCI_CAP_ID_PM Power Management
486 * %PCI_CAP_ID_AGP Accelerated Graphics Port
487 * %PCI_CAP_ID_VPD Vital Product Data
488 * %PCI_CAP_ID_SLOTID Slot Identification
489 * %PCI_CAP_ID_MSI Message Signalled Interrupts
490 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
491 * %PCI_CAP_ID_PCIX PCI-X
492 * %PCI_CAP_ID_EXP PCI Express
494 u8 pci_find_capability(struct pci_dev *dev, int cap)
498 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
500 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
504 EXPORT_SYMBOL(pci_find_capability);
507 * pci_bus_find_capability - query for devices' capabilities
508 * @bus: the PCI bus to query
509 * @devfn: PCI device to query
510 * @cap: capability code
512 * Like pci_find_capability() but works for PCI devices that do not have a
513 * pci_dev structure set up yet.
515 * Returns the address of the requested capability structure within the
516 * device's PCI configuration space or 0 in case the device does not
519 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
523 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
525 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
527 pos = __pci_find_next_cap(bus, devfn, pos, cap);
531 EXPORT_SYMBOL(pci_bus_find_capability);
534 * pci_find_next_ext_capability - Find an extended capability
535 * @dev: PCI device to query
536 * @start: address at which to start looking (0 to start at beginning of list)
537 * @cap: capability code
539 * Returns the address of the next matching extended capability structure
540 * within the device's PCI configuration space or 0 if the device does
541 * not support it. Some capabilities can occur several times, e.g., the
542 * vendor-specific capability, and this provides a way to find them all.
544 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap)
548 u16 pos = PCI_CFG_SPACE_SIZE;
550 /* minimum 8 bytes per capability */
551 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
553 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
559 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
563 * If we have no capabilities, this is indicated by cap ID,
564 * cap version and next pointer all being 0.
570 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
573 pos = PCI_EXT_CAP_NEXT(header);
574 if (pos < PCI_CFG_SPACE_SIZE)
577 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
583 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
586 * pci_find_ext_capability - Find an extended capability
587 * @dev: PCI device to query
588 * @cap: capability code
590 * Returns the address of the requested extended capability structure
591 * within the device's PCI configuration space or 0 if the device does
592 * not support it. Possible values for @cap include:
594 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
595 * %PCI_EXT_CAP_ID_VC Virtual Channel
596 * %PCI_EXT_CAP_ID_DSN Device Serial Number
597 * %PCI_EXT_CAP_ID_PWR Power Budgeting
599 u16 pci_find_ext_capability(struct pci_dev *dev, int cap)
601 return pci_find_next_ext_capability(dev, 0, cap);
603 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
606 * pci_get_dsn - Read and return the 8-byte Device Serial Number
607 * @dev: PCI device to query
609 * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
612 * Returns the DSN, or zero if the capability does not exist.
614 u64 pci_get_dsn(struct pci_dev *dev)
620 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DSN);
625 * The Device Serial Number is two dwords offset 4 bytes from the
626 * capability position. The specification says that the first dword is
627 * the lower half, and the second dword is the upper half.
630 pci_read_config_dword(dev, pos, &dword);
632 pci_read_config_dword(dev, pos + 4, &dword);
633 dsn |= ((u64)dword) << 32;
637 EXPORT_SYMBOL_GPL(pci_get_dsn);
639 static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
641 int rc, ttl = PCI_FIND_CAP_TTL;
644 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
645 mask = HT_3BIT_CAP_MASK;
647 mask = HT_5BIT_CAP_MASK;
649 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
650 PCI_CAP_ID_HT, &ttl);
652 rc = pci_read_config_byte(dev, pos + 3, &cap);
653 if (rc != PCIBIOS_SUCCESSFUL)
656 if ((cap & mask) == ht_cap)
659 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
660 pos + PCI_CAP_LIST_NEXT,
661 PCI_CAP_ID_HT, &ttl);
668 * pci_find_next_ht_capability - query a device's HyperTransport capabilities
669 * @dev: PCI device to query
670 * @pos: Position from which to continue searching
671 * @ht_cap: HyperTransport capability code
673 * To be used in conjunction with pci_find_ht_capability() to search for
674 * all capabilities matching @ht_cap. @pos should always be a value returned
675 * from pci_find_ht_capability().
677 * NB. To be 100% safe against broken PCI devices, the caller should take
678 * steps to avoid an infinite loop.
680 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap)
682 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
684 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
687 * pci_find_ht_capability - query a device's HyperTransport capabilities
688 * @dev: PCI device to query
689 * @ht_cap: HyperTransport capability code
691 * Tell if a device supports a given HyperTransport capability.
692 * Returns an address within the device's PCI configuration space
693 * or 0 in case the device does not support the request capability.
694 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
695 * which has a HyperTransport capability matching @ht_cap.
697 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
701 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
703 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
707 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
710 * pci_find_vsec_capability - Find a vendor-specific extended capability
711 * @dev: PCI device to query
712 * @vendor: Vendor ID for which capability is defined
713 * @cap: Vendor-specific capability ID
715 * If @dev has Vendor ID @vendor, search for a VSEC capability with
716 * VSEC ID @cap. If found, return the capability offset in
717 * config space; otherwise return 0.
719 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap)
724 if (vendor != dev->vendor)
727 while ((vsec = pci_find_next_ext_capability(dev, vsec,
728 PCI_EXT_CAP_ID_VNDR))) {
729 if (pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER,
730 &header) == PCIBIOS_SUCCESSFUL &&
731 PCI_VNDR_HEADER_ID(header) == cap)
737 EXPORT_SYMBOL_GPL(pci_find_vsec_capability);
740 * pci_find_dvsec_capability - Find DVSEC for vendor
741 * @dev: PCI device to query
742 * @vendor: Vendor ID to match for the DVSEC
743 * @dvsec: Designated Vendor-specific capability ID
745 * If DVSEC has Vendor ID @vendor and DVSEC ID @dvsec return the capability
746 * offset in config space; otherwise return 0.
748 u16 pci_find_dvsec_capability(struct pci_dev *dev, u16 vendor, u16 dvsec)
752 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DVSEC);
759 pci_read_config_word(dev, pos + PCI_DVSEC_HEADER1, &v);
760 pci_read_config_word(dev, pos + PCI_DVSEC_HEADER2, &id);
761 if (vendor == v && dvsec == id)
764 pos = pci_find_next_ext_capability(dev, pos, PCI_EXT_CAP_ID_DVSEC);
769 EXPORT_SYMBOL_GPL(pci_find_dvsec_capability);
772 * pci_find_parent_resource - return resource region of parent bus of given
774 * @dev: PCI device structure contains resources to be searched
775 * @res: child resource record for which parent is sought
777 * For given resource region of given device, return the resource region of
778 * parent bus the given region is contained in.
780 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
781 struct resource *res)
783 const struct pci_bus *bus = dev->bus;
787 pci_bus_for_each_resource(bus, r, i) {
790 if (resource_contains(r, res)) {
793 * If the window is prefetchable but the BAR is
794 * not, the allocator made a mistake.
796 if (r->flags & IORESOURCE_PREFETCH &&
797 !(res->flags & IORESOURCE_PREFETCH))
801 * If we're below a transparent bridge, there may
802 * be both a positively-decoded aperture and a
803 * subtractively-decoded region that contain the BAR.
804 * We want the positively-decoded one, so this depends
805 * on pci_bus_for_each_resource() giving us those
813 EXPORT_SYMBOL(pci_find_parent_resource);
816 * pci_find_resource - Return matching PCI device resource
817 * @dev: PCI device to query
818 * @res: Resource to look for
820 * Goes over standard PCI resources (BARs) and checks if the given resource
821 * is partially or fully contained in any of them. In that case the
822 * matching resource is returned, %NULL otherwise.
824 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
828 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
829 struct resource *r = &dev->resource[i];
831 if (r->start && resource_contains(r, res))
837 EXPORT_SYMBOL(pci_find_resource);
840 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
841 * @dev: the PCI device to operate on
842 * @pos: config space offset of status word
843 * @mask: mask of bit(s) to care about in status word
845 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
847 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
851 /* Wait for Transaction Pending bit clean */
852 for (i = 0; i < 4; i++) {
855 msleep((1 << (i - 1)) * 100);
857 pci_read_config_word(dev, pos, &status);
858 if (!(status & mask))
865 static int pci_acs_enable;
868 * pci_request_acs - ask for ACS to be enabled if supported
870 void pci_request_acs(void)
875 static const char *disable_acs_redir_param;
878 * pci_disable_acs_redir - disable ACS redirect capabilities
879 * @dev: the PCI device
881 * For only devices specified in the disable_acs_redir parameter.
883 static void pci_disable_acs_redir(struct pci_dev *dev)
890 if (!disable_acs_redir_param)
893 p = disable_acs_redir_param;
895 ret = pci_dev_str_match(dev, p, &p);
897 pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
898 disable_acs_redir_param);
901 } else if (ret == 1) {
906 if (*p != ';' && *p != ',') {
907 /* End of param or invalid format */
916 if (!pci_dev_specific_disable_acs_redir(dev))
921 pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
925 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
927 /* P2P Request & Completion Redirect */
928 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
930 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
932 pci_info(dev, "disabled ACS redirect\n");
936 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
937 * @dev: the PCI device
939 static void pci_std_enable_acs(struct pci_dev *dev)
949 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
950 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
952 /* Source Validation */
953 ctrl |= (cap & PCI_ACS_SV);
955 /* P2P Request Redirect */
956 ctrl |= (cap & PCI_ACS_RR);
958 /* P2P Completion Redirect */
959 ctrl |= (cap & PCI_ACS_CR);
961 /* Upstream Forwarding */
962 ctrl |= (cap & PCI_ACS_UF);
964 /* Enable Translation Blocking for external devices and noats */
965 if (pci_ats_disabled() || dev->external_facing || dev->untrusted)
966 ctrl |= (cap & PCI_ACS_TB);
968 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
972 * pci_enable_acs - enable ACS if hardware support it
973 * @dev: the PCI device
975 static void pci_enable_acs(struct pci_dev *dev)
978 goto disable_acs_redir;
980 if (!pci_dev_specific_enable_acs(dev))
981 goto disable_acs_redir;
983 pci_std_enable_acs(dev);
987 * Note: pci_disable_acs_redir() must be called even if ACS was not
988 * enabled by the kernel because it may have been enabled by
989 * platform firmware. So if we are told to disable it, we should
990 * always disable it after setting the kernel's default
993 pci_disable_acs_redir(dev);
997 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
998 * @dev: PCI device to have its BARs restored
1000 * Restore the BAR values for a given device, so as to make it
1001 * accessible by its driver.
1003 static void pci_restore_bars(struct pci_dev *dev)
1007 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
1008 pci_update_resource(dev, i);
1011 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
1013 if (pci_use_mid_pm())
1016 return acpi_pci_power_manageable(dev);
1019 static inline int platform_pci_set_power_state(struct pci_dev *dev,
1022 if (pci_use_mid_pm())
1023 return mid_pci_set_power_state(dev, t);
1025 return acpi_pci_set_power_state(dev, t);
1028 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
1030 if (pci_use_mid_pm())
1031 return mid_pci_get_power_state(dev);
1033 return acpi_pci_get_power_state(dev);
1036 static inline void platform_pci_refresh_power_state(struct pci_dev *dev)
1038 if (!pci_use_mid_pm())
1039 acpi_pci_refresh_power_state(dev);
1042 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
1044 if (pci_use_mid_pm())
1045 return PCI_POWER_ERROR;
1047 return acpi_pci_choose_state(dev);
1050 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
1052 if (pci_use_mid_pm())
1053 return PCI_POWER_ERROR;
1055 return acpi_pci_wakeup(dev, enable);
1058 static inline bool platform_pci_need_resume(struct pci_dev *dev)
1060 if (pci_use_mid_pm())
1063 return acpi_pci_need_resume(dev);
1066 static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
1068 if (pci_use_mid_pm())
1071 return acpi_pci_bridge_d3(dev);
1075 * pci_update_current_state - Read power state of given device and cache it
1076 * @dev: PCI device to handle.
1077 * @state: State to cache in case the device doesn't have the PM capability
1079 * The power state is read from the PMCSR register, which however is
1080 * inaccessible in D3cold. The platform firmware is therefore queried first
1081 * to detect accessibility of the register. In case the platform firmware
1082 * reports an incorrect state or the device isn't power manageable by the
1083 * platform at all, we try to detect D3cold by testing accessibility of the
1084 * vendor ID in config space.
1086 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
1088 if (platform_pci_get_power_state(dev) == PCI_D3cold) {
1089 dev->current_state = PCI_D3cold;
1090 } else if (dev->pm_cap) {
1093 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1094 if (PCI_POSSIBLE_ERROR(pmcsr)) {
1095 dev->current_state = PCI_D3cold;
1098 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1100 dev->current_state = state;
1105 * pci_refresh_power_state - Refresh the given device's power state data
1106 * @dev: Target PCI device.
1108 * Ask the platform to refresh the devices power state information and invoke
1109 * pci_update_current_state() to update its current PCI power state.
1111 void pci_refresh_power_state(struct pci_dev *dev)
1113 platform_pci_refresh_power_state(dev);
1114 pci_update_current_state(dev, dev->current_state);
1118 * pci_platform_power_transition - Use platform to change device power state
1119 * @dev: PCI device to handle.
1120 * @state: State to put the device into.
1122 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
1126 error = platform_pci_set_power_state(dev, state);
1128 pci_update_current_state(dev, state);
1129 else if (!dev->pm_cap) /* Fall back to PCI_D0 */
1130 dev->current_state = PCI_D0;
1134 EXPORT_SYMBOL_GPL(pci_platform_power_transition);
1136 static int pci_resume_one(struct pci_dev *pci_dev, void *ign)
1138 pm_request_resume(&pci_dev->dev);
1143 * pci_resume_bus - Walk given bus and runtime resume devices on it
1144 * @bus: Top bus of the subtree to walk.
1146 void pci_resume_bus(struct pci_bus *bus)
1149 pci_walk_bus(bus, pci_resume_one, NULL);
1152 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
1158 * After reset, the device should not silently discard config
1159 * requests, but it may still indicate that it needs more time by
1160 * responding to them with CRS completions. The Root Port will
1161 * generally synthesize ~0 (PCI_ERROR_RESPONSE) data to complete
1162 * the read (except when CRS SV is enabled and the read was for the
1163 * Vendor ID; in that case it synthesizes 0x0001 data).
1165 * Wait for the device to return a non-CRS completion. Read the
1166 * Command register instead of Vendor ID so we don't have to
1167 * contend with the CRS SV value.
1169 pci_read_config_dword(dev, PCI_COMMAND, &id);
1170 while (PCI_POSSIBLE_ERROR(id)) {
1171 if (delay > timeout) {
1172 pci_warn(dev, "not ready %dms after %s; giving up\n",
1173 delay - 1, reset_type);
1178 pci_info(dev, "not ready %dms after %s; waiting\n",
1179 delay - 1, reset_type);
1183 pci_read_config_dword(dev, PCI_COMMAND, &id);
1187 pci_info(dev, "ready %dms after %s\n", delay - 1,
1194 * pci_power_up - Put the given device into D0
1195 * @dev: PCI device to power up
1197 * On success, return 0 or 1, depending on whether or not it is necessary to
1198 * restore the device's BARs subsequently (1 is returned in that case).
1200 int pci_power_up(struct pci_dev *dev)
1206 platform_pci_set_power_state(dev, PCI_D0);
1209 state = platform_pci_get_power_state(dev);
1210 if (state == PCI_UNKNOWN)
1211 dev->current_state = PCI_D0;
1213 dev->current_state = state;
1215 if (state == PCI_D0)
1221 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1222 if (PCI_POSSIBLE_ERROR(pmcsr)) {
1223 pci_err(dev, "Unable to change power state from %s to D0, device inaccessible\n",
1224 pci_power_name(dev->current_state));
1225 dev->current_state = PCI_D3cold;
1229 state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1231 need_restore = (state == PCI_D3hot || dev->current_state >= PCI_D3hot) &&
1232 !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET);
1234 if (state == PCI_D0)
1238 * Force the entire word to 0. This doesn't affect PME_Status, disables
1239 * PME_En, and sets PowerState to 0.
1241 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, 0);
1243 /* Mandatory transition delays; see PCI PM 1.2. */
1244 if (state == PCI_D3hot)
1245 pci_dev_d3_sleep(dev);
1246 else if (state == PCI_D2)
1247 udelay(PCI_PM_D2_DELAY);
1250 dev->current_state = PCI_D0;
1258 * pci_set_full_power_state - Put a PCI device into D0 and update its state
1259 * @dev: PCI device to power up
1261 * Call pci_power_up() to put @dev into D0, read from its PCI_PM_CTRL register
1262 * to confirm the state change, restore its BARs if they might be lost and
1263 * reconfigure ASPM in acordance with the new power state.
1265 * If pci_restore_state() is going to be called right after a power state change
1266 * to D0, it is more efficient to use pci_power_up() directly instead of this
1269 static int pci_set_full_power_state(struct pci_dev *dev)
1274 ret = pci_power_up(dev);
1278 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1279 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1280 if (dev->current_state != PCI_D0) {
1281 pci_info_ratelimited(dev, "Refused to change power state from %s to D0\n",
1282 pci_power_name(dev->current_state));
1283 } else if (ret > 0) {
1285 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
1286 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
1287 * from D3hot to D0 _may_ perform an internal reset, thereby
1288 * going to "D0 Uninitialized" rather than "D0 Initialized".
1289 * For example, at least some versions of the 3c905B and the
1290 * 3c556B exhibit this behaviour.
1292 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
1293 * devices in a D3hot state at boot. Consequently, we need to
1294 * restore at least the BARs so that the device will be
1295 * accessible to its driver.
1297 pci_restore_bars(dev);
1304 * __pci_dev_set_current_state - Set current state of a PCI device
1305 * @dev: Device to handle
1306 * @data: pointer to state to be set
1308 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
1310 pci_power_t state = *(pci_power_t *)data;
1312 dev->current_state = state;
1317 * pci_bus_set_current_state - Walk given bus and set current state of devices
1318 * @bus: Top bus of the subtree to walk.
1319 * @state: state to be set
1321 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
1324 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
1328 * pci_set_low_power_state - Put a PCI device into a low-power state.
1329 * @dev: PCI device to handle.
1330 * @state: PCI power state (D1, D2, D3hot) to put the device into.
1332 * Use the device's PCI_PM_CTRL register to put it into a low-power state.
1335 * -EINVAL if the requested state is invalid.
1336 * -EIO if device does not support PCI PM or its PM capabilities register has a
1337 * wrong version, or device doesn't support the requested state.
1338 * 0 if device already is in the requested state.
1339 * 0 if device's power state has been successfully changed.
1341 static int pci_set_low_power_state(struct pci_dev *dev, pci_power_t state)
1349 * Validate transition: We can enter D0 from any state, but if
1350 * we're already in a low-power state, we can only go deeper. E.g.,
1351 * we can go from D1 to D3, but we can't go directly from D3 to D1;
1352 * we'd have to go from D3 to D0, then to D1.
1354 if (dev->current_state <= PCI_D3cold && dev->current_state > state) {
1355 pci_dbg(dev, "Invalid power transition (from %s to %s)\n",
1356 pci_power_name(dev->current_state),
1357 pci_power_name(state));
1361 /* Check if this device supports the desired state */
1362 if ((state == PCI_D1 && !dev->d1_support)
1363 || (state == PCI_D2 && !dev->d2_support))
1366 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1367 if (PCI_POSSIBLE_ERROR(pmcsr)) {
1368 pci_err(dev, "Unable to change power state from %s to %s, device inaccessible\n",
1369 pci_power_name(dev->current_state),
1370 pci_power_name(state));
1371 dev->current_state = PCI_D3cold;
1375 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
1378 /* Enter specified state */
1379 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1381 /* Mandatory power management transition delays; see PCI PM 1.2. */
1382 if (state == PCI_D3hot)
1383 pci_dev_d3_sleep(dev);
1384 else if (state == PCI_D2)
1385 udelay(PCI_PM_D2_DELAY);
1387 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1388 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK;
1389 if (dev->current_state != state)
1390 pci_info_ratelimited(dev, "Refused to change power state from %s to %s\n",
1391 pci_power_name(dev->current_state),
1392 pci_power_name(state));
1398 * pci_set_power_state - Set the power state of a PCI device
1399 * @dev: PCI device to handle.
1400 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1402 * Transition a device to a new power state, using the platform firmware and/or
1403 * the device's PCI PM registers.
1406 * -EINVAL if the requested state is invalid.
1407 * -EIO if device does not support PCI PM or its PM capabilities register has a
1408 * wrong version, or device doesn't support the requested state.
1409 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1410 * 0 if device already is in the requested state.
1411 * 0 if the transition is to D3 but D3 is not supported.
1412 * 0 if device's power state has been successfully changed.
1414 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1418 /* Bound the state we're entering */
1419 if (state > PCI_D3cold)
1421 else if (state < PCI_D0)
1423 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
1426 * If the device or the parent bridge do not support PCI
1427 * PM, ignore the request if we're doing anything other
1428 * than putting it into D0 (which would only happen on
1433 /* Check if we're already there */
1434 if (dev->current_state == state)
1437 if (state == PCI_D0)
1438 return pci_set_full_power_state(dev);
1441 * This device is quirked not to be put into D3, so don't put it in
1444 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1447 if (state == PCI_D3cold) {
1449 * To put the device in D3cold, put it into D3hot in the native
1450 * way, then put it into D3cold using platform ops.
1452 error = pci_set_low_power_state(dev, PCI_D3hot);
1454 if (pci_platform_power_transition(dev, PCI_D3cold))
1457 /* Powering off a bridge may power off the whole hierarchy */
1458 if (dev->current_state == PCI_D3cold)
1459 pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
1461 error = pci_set_low_power_state(dev, state);
1463 if (pci_platform_power_transition(dev, state))
1469 EXPORT_SYMBOL(pci_set_power_state);
1471 #define PCI_EXP_SAVE_REGS 7
1473 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
1474 u16 cap, bool extended)
1476 struct pci_cap_saved_state *tmp;
1478 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
1479 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
1485 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1487 return _pci_find_saved_cap(dev, cap, false);
1490 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1492 return _pci_find_saved_cap(dev, cap, true);
1495 static int pci_save_pcie_state(struct pci_dev *dev)
1498 struct pci_cap_saved_state *save_state;
1501 if (!pci_is_pcie(dev))
1504 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1506 pci_err(dev, "buffer not found in %s\n", __func__);
1510 cap = (u16 *)&save_state->cap.data[0];
1511 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1512 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1513 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1514 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1515 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1516 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1517 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1522 void pci_bridge_reconfigure_ltr(struct pci_dev *dev)
1524 #ifdef CONFIG_PCIEASPM
1525 struct pci_dev *bridge;
1528 bridge = pci_upstream_bridge(dev);
1529 if (bridge && bridge->ltr_path) {
1530 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, &ctl);
1531 if (!(ctl & PCI_EXP_DEVCTL2_LTR_EN)) {
1532 pci_dbg(bridge, "re-enabling LTR\n");
1533 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
1534 PCI_EXP_DEVCTL2_LTR_EN);
1540 static void pci_restore_pcie_state(struct pci_dev *dev)
1543 struct pci_cap_saved_state *save_state;
1546 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1551 * Downstream ports reset the LTR enable bit when link goes down.
1552 * Check and re-configure the bit here before restoring device.
1553 * PCIe r5.0, sec 7.5.3.16.
1555 pci_bridge_reconfigure_ltr(dev);
1557 cap = (u16 *)&save_state->cap.data[0];
1558 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1559 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1560 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1561 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1562 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1563 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1564 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1567 static int pci_save_pcix_state(struct pci_dev *dev)
1570 struct pci_cap_saved_state *save_state;
1572 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1576 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1578 pci_err(dev, "buffer not found in %s\n", __func__);
1582 pci_read_config_word(dev, pos + PCI_X_CMD,
1583 (u16 *)save_state->cap.data);
1588 static void pci_restore_pcix_state(struct pci_dev *dev)
1591 struct pci_cap_saved_state *save_state;
1594 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1595 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1596 if (!save_state || !pos)
1598 cap = (u16 *)&save_state->cap.data[0];
1600 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1603 static void pci_save_ltr_state(struct pci_dev *dev)
1606 struct pci_cap_saved_state *save_state;
1609 if (!pci_is_pcie(dev))
1612 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1616 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1618 pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
1622 /* Some broken devices only support dword access to LTR */
1623 cap = &save_state->cap.data[0];
1624 pci_read_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap);
1627 static void pci_restore_ltr_state(struct pci_dev *dev)
1629 struct pci_cap_saved_state *save_state;
1633 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1634 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1635 if (!save_state || !ltr)
1638 /* Some broken devices only support dword access to LTR */
1639 cap = &save_state->cap.data[0];
1640 pci_write_config_dword(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap);
1644 * pci_save_state - save the PCI configuration space of a device before
1646 * @dev: PCI device that we're dealing with
1648 int pci_save_state(struct pci_dev *dev)
1651 /* XXX: 100% dword access ok here? */
1652 for (i = 0; i < 16; i++) {
1653 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1654 pci_dbg(dev, "saving config space at offset %#x (reading %#x)\n",
1655 i * 4, dev->saved_config_space[i]);
1657 dev->state_saved = true;
1659 i = pci_save_pcie_state(dev);
1663 i = pci_save_pcix_state(dev);
1667 pci_save_ltr_state(dev);
1668 pci_save_dpc_state(dev);
1669 pci_save_aer_state(dev);
1670 pci_save_ptm_state(dev);
1671 return pci_save_vc_state(dev);
1673 EXPORT_SYMBOL(pci_save_state);
1675 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1676 u32 saved_val, int retry, bool force)
1680 pci_read_config_dword(pdev, offset, &val);
1681 if (!force && val == saved_val)
1685 pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1686 offset, val, saved_val);
1687 pci_write_config_dword(pdev, offset, saved_val);
1691 pci_read_config_dword(pdev, offset, &val);
1692 if (val == saved_val)
1699 static void pci_restore_config_space_range(struct pci_dev *pdev,
1700 int start, int end, int retry,
1705 for (index = end; index >= start; index--)
1706 pci_restore_config_dword(pdev, 4 * index,
1707 pdev->saved_config_space[index],
1711 static void pci_restore_config_space(struct pci_dev *pdev)
1713 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1714 pci_restore_config_space_range(pdev, 10, 15, 0, false);
1715 /* Restore BARs before the command register. */
1716 pci_restore_config_space_range(pdev, 4, 9, 10, false);
1717 pci_restore_config_space_range(pdev, 0, 3, 0, false);
1718 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1719 pci_restore_config_space_range(pdev, 12, 15, 0, false);
1722 * Force rewriting of prefetch registers to avoid S3 resume
1723 * issues on Intel PCI bridges that occur when these
1724 * registers are not explicitly written.
1726 pci_restore_config_space_range(pdev, 9, 11, 0, true);
1727 pci_restore_config_space_range(pdev, 0, 8, 0, false);
1729 pci_restore_config_space_range(pdev, 0, 15, 0, false);
1733 static void pci_restore_rebar_state(struct pci_dev *pdev)
1735 unsigned int pos, nbars, i;
1738 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
1742 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1743 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
1744 PCI_REBAR_CTRL_NBAR_SHIFT;
1746 for (i = 0; i < nbars; i++, pos += 8) {
1747 struct resource *res;
1750 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1751 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
1752 res = pdev->resource + bar_idx;
1753 size = pci_rebar_bytes_to_size(resource_size(res));
1754 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
1755 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
1756 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
1761 * pci_restore_state - Restore the saved state of a PCI device
1762 * @dev: PCI device that we're dealing with
1764 void pci_restore_state(struct pci_dev *dev)
1766 if (!dev->state_saved)
1770 * Restore max latencies (in the LTR capability) before enabling
1771 * LTR itself (in the PCIe capability).
1773 pci_restore_ltr_state(dev);
1775 pci_restore_pcie_state(dev);
1776 pci_restore_pasid_state(dev);
1777 pci_restore_pri_state(dev);
1778 pci_restore_ats_state(dev);
1779 pci_restore_vc_state(dev);
1780 pci_restore_rebar_state(dev);
1781 pci_restore_dpc_state(dev);
1782 pci_restore_ptm_state(dev);
1784 pci_aer_clear_status(dev);
1785 pci_restore_aer_state(dev);
1787 pci_restore_config_space(dev);
1789 pci_restore_pcix_state(dev);
1790 pci_restore_msi_state(dev);
1792 /* Restore ACS and IOV configuration state */
1793 pci_enable_acs(dev);
1794 pci_restore_iov_state(dev);
1796 dev->state_saved = false;
1798 EXPORT_SYMBOL(pci_restore_state);
1800 struct pci_saved_state {
1801 u32 config_space[16];
1802 struct pci_cap_saved_data cap[];
1806 * pci_store_saved_state - Allocate and return an opaque struct containing
1807 * the device saved state.
1808 * @dev: PCI device that we're dealing with
1810 * Return NULL if no state or error.
1812 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1814 struct pci_saved_state *state;
1815 struct pci_cap_saved_state *tmp;
1816 struct pci_cap_saved_data *cap;
1819 if (!dev->state_saved)
1822 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1824 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1825 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1827 state = kzalloc(size, GFP_KERNEL);
1831 memcpy(state->config_space, dev->saved_config_space,
1832 sizeof(state->config_space));
1835 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1836 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1837 memcpy(cap, &tmp->cap, len);
1838 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1840 /* Empty cap_save terminates list */
1844 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1847 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1848 * @dev: PCI device that we're dealing with
1849 * @state: Saved state returned from pci_store_saved_state()
1851 int pci_load_saved_state(struct pci_dev *dev,
1852 struct pci_saved_state *state)
1854 struct pci_cap_saved_data *cap;
1856 dev->state_saved = false;
1861 memcpy(dev->saved_config_space, state->config_space,
1862 sizeof(state->config_space));
1866 struct pci_cap_saved_state *tmp;
1868 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1869 if (!tmp || tmp->cap.size != cap->size)
1872 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1873 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1874 sizeof(struct pci_cap_saved_data) + cap->size);
1877 dev->state_saved = true;
1880 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1883 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1884 * and free the memory allocated for it.
1885 * @dev: PCI device that we're dealing with
1886 * @state: Pointer to saved state returned from pci_store_saved_state()
1888 int pci_load_and_free_saved_state(struct pci_dev *dev,
1889 struct pci_saved_state **state)
1891 int ret = pci_load_saved_state(dev, *state);
1896 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1898 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1900 return pci_enable_resources(dev, bars);
1903 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1906 struct pci_dev *bridge;
1910 err = pci_set_power_state(dev, PCI_D0);
1911 if (err < 0 && err != -EIO)
1914 bridge = pci_upstream_bridge(dev);
1916 pcie_aspm_powersave_config_link(bridge);
1918 err = pcibios_enable_device(dev, bars);
1921 pci_fixup_device(pci_fixup_enable, dev);
1923 if (dev->msi_enabled || dev->msix_enabled)
1926 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1928 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1929 if (cmd & PCI_COMMAND_INTX_DISABLE)
1930 pci_write_config_word(dev, PCI_COMMAND,
1931 cmd & ~PCI_COMMAND_INTX_DISABLE);
1938 * pci_reenable_device - Resume abandoned device
1939 * @dev: PCI device to be resumed
1941 * NOTE: This function is a backend of pci_default_resume() and is not supposed
1942 * to be called by normal code, write proper resume handler and use it instead.
1944 int pci_reenable_device(struct pci_dev *dev)
1946 if (pci_is_enabled(dev))
1947 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1950 EXPORT_SYMBOL(pci_reenable_device);
1952 static void pci_enable_bridge(struct pci_dev *dev)
1954 struct pci_dev *bridge;
1957 bridge = pci_upstream_bridge(dev);
1959 pci_enable_bridge(bridge);
1961 if (pci_is_enabled(dev)) {
1962 if (!dev->is_busmaster)
1963 pci_set_master(dev);
1967 retval = pci_enable_device(dev);
1969 pci_err(dev, "Error enabling bridge (%d), continuing\n",
1971 pci_set_master(dev);
1974 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1976 struct pci_dev *bridge;
1981 * Power state could be unknown at this point, either due to a fresh
1982 * boot or a device removal call. So get the current power state
1983 * so that things like MSI message writing will behave as expected
1984 * (e.g. if the device really is in D0 at enable time).
1986 pci_update_current_state(dev, dev->current_state);
1988 if (atomic_inc_return(&dev->enable_cnt) > 1)
1989 return 0; /* already enabled */
1991 bridge = pci_upstream_bridge(dev);
1993 pci_enable_bridge(bridge);
1995 /* only skip sriov related */
1996 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1997 if (dev->resource[i].flags & flags)
1999 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
2000 if (dev->resource[i].flags & flags)
2003 err = do_pci_enable_device(dev, bars);
2005 atomic_dec(&dev->enable_cnt);
2010 * pci_enable_device_io - Initialize a device for use with IO space
2011 * @dev: PCI device to be initialized
2013 * Initialize device before it's used by a driver. Ask low-level code
2014 * to enable I/O resources. Wake up the device if it was suspended.
2015 * Beware, this function can fail.
2017 int pci_enable_device_io(struct pci_dev *dev)
2019 return pci_enable_device_flags(dev, IORESOURCE_IO);
2021 EXPORT_SYMBOL(pci_enable_device_io);
2024 * pci_enable_device_mem - Initialize a device for use with Memory space
2025 * @dev: PCI device to be initialized
2027 * Initialize device before it's used by a driver. Ask low-level code
2028 * to enable Memory resources. Wake up the device if it was suspended.
2029 * Beware, this function can fail.
2031 int pci_enable_device_mem(struct pci_dev *dev)
2033 return pci_enable_device_flags(dev, IORESOURCE_MEM);
2035 EXPORT_SYMBOL(pci_enable_device_mem);
2038 * pci_enable_device - Initialize device before it's used by a driver.
2039 * @dev: PCI device to be initialized
2041 * Initialize device before it's used by a driver. Ask low-level code
2042 * to enable I/O and memory. Wake up the device if it was suspended.
2043 * Beware, this function can fail.
2045 * Note we don't actually enable the device many times if we call
2046 * this function repeatedly (we just increment the count).
2048 int pci_enable_device(struct pci_dev *dev)
2050 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
2052 EXPORT_SYMBOL(pci_enable_device);
2055 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
2056 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
2057 * there's no need to track it separately. pci_devres is initialized
2058 * when a device is enabled using managed PCI device enable interface.
2061 unsigned int enabled:1;
2062 unsigned int pinned:1;
2063 unsigned int orig_intx:1;
2064 unsigned int restore_intx:1;
2069 static void pcim_release(struct device *gendev, void *res)
2071 struct pci_dev *dev = to_pci_dev(gendev);
2072 struct pci_devres *this = res;
2075 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
2076 if (this->region_mask & (1 << i))
2077 pci_release_region(dev, i);
2082 if (this->restore_intx)
2083 pci_intx(dev, this->orig_intx);
2085 if (this->enabled && !this->pinned)
2086 pci_disable_device(dev);
2089 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
2091 struct pci_devres *dr, *new_dr;
2093 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
2097 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
2100 return devres_get(&pdev->dev, new_dr, NULL, NULL);
2103 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
2105 if (pci_is_managed(pdev))
2106 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
2111 * pcim_enable_device - Managed pci_enable_device()
2112 * @pdev: PCI device to be initialized
2114 * Managed pci_enable_device().
2116 int pcim_enable_device(struct pci_dev *pdev)
2118 struct pci_devres *dr;
2121 dr = get_pci_dr(pdev);
2127 rc = pci_enable_device(pdev);
2129 pdev->is_managed = 1;
2134 EXPORT_SYMBOL(pcim_enable_device);
2137 * pcim_pin_device - Pin managed PCI device
2138 * @pdev: PCI device to pin
2140 * Pin managed PCI device @pdev. Pinned device won't be disabled on
2141 * driver detach. @pdev must have been enabled with
2142 * pcim_enable_device().
2144 void pcim_pin_device(struct pci_dev *pdev)
2146 struct pci_devres *dr;
2148 dr = find_pci_dr(pdev);
2149 WARN_ON(!dr || !dr->enabled);
2153 EXPORT_SYMBOL(pcim_pin_device);
2156 * pcibios_device_add - provide arch specific hooks when adding device dev
2157 * @dev: the PCI device being added
2159 * Permits the platform to provide architecture specific functionality when
2160 * devices are added. This is the default implementation. Architecture
2161 * implementations can override this.
2163 int __weak pcibios_device_add(struct pci_dev *dev)
2169 * pcibios_release_device - provide arch specific hooks when releasing
2171 * @dev: the PCI device being released
2173 * Permits the platform to provide architecture specific functionality when
2174 * devices are released. This is the default implementation. Architecture
2175 * implementations can override this.
2177 void __weak pcibios_release_device(struct pci_dev *dev) {}
2180 * pcibios_disable_device - disable arch specific PCI resources for device dev
2181 * @dev: the PCI device to disable
2183 * Disables architecture specific PCI resources for the device. This
2184 * is the default implementation. Architecture implementations can
2187 void __weak pcibios_disable_device(struct pci_dev *dev) {}
2190 * pcibios_penalize_isa_irq - penalize an ISA IRQ
2191 * @irq: ISA IRQ to penalize
2192 * @active: IRQ active or not
2194 * Permits the platform to provide architecture-specific functionality when
2195 * penalizing ISA IRQs. This is the default implementation. Architecture
2196 * implementations can override this.
2198 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
2200 static void do_pci_disable_device(struct pci_dev *dev)
2204 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
2205 if (pci_command & PCI_COMMAND_MASTER) {
2206 pci_command &= ~PCI_COMMAND_MASTER;
2207 pci_write_config_word(dev, PCI_COMMAND, pci_command);
2210 pcibios_disable_device(dev);
2214 * pci_disable_enabled_device - Disable device without updating enable_cnt
2215 * @dev: PCI device to disable
2217 * NOTE: This function is a backend of PCI power management routines and is
2218 * not supposed to be called drivers.
2220 void pci_disable_enabled_device(struct pci_dev *dev)
2222 if (pci_is_enabled(dev))
2223 do_pci_disable_device(dev);
2227 * pci_disable_device - Disable PCI device after use
2228 * @dev: PCI device to be disabled
2230 * Signal to the system that the PCI device is not in use by the system
2231 * anymore. This only involves disabling PCI bus-mastering, if active.
2233 * Note we don't actually disable the device until all callers of
2234 * pci_enable_device() have called pci_disable_device().
2236 void pci_disable_device(struct pci_dev *dev)
2238 struct pci_devres *dr;
2240 dr = find_pci_dr(dev);
2244 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
2245 "disabling already-disabled device");
2247 if (atomic_dec_return(&dev->enable_cnt) != 0)
2250 do_pci_disable_device(dev);
2252 dev->is_busmaster = 0;
2254 EXPORT_SYMBOL(pci_disable_device);
2257 * pcibios_set_pcie_reset_state - set reset state for device dev
2258 * @dev: the PCIe device reset
2259 * @state: Reset state to enter into
2261 * Set the PCIe reset state for the device. This is the default
2262 * implementation. Architecture implementations can override this.
2264 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
2265 enum pcie_reset_state state)
2271 * pci_set_pcie_reset_state - set reset state for device dev
2272 * @dev: the PCIe device reset
2273 * @state: Reset state to enter into
2275 * Sets the PCI reset state for the device.
2277 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
2279 return pcibios_set_pcie_reset_state(dev, state);
2281 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
2283 #ifdef CONFIG_PCIEAER
2284 void pcie_clear_device_status(struct pci_dev *dev)
2288 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);
2289 pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);
2294 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2295 * @dev: PCIe root port or event collector.
2297 void pcie_clear_root_pme_status(struct pci_dev *dev)
2299 pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
2303 * pci_check_pme_status - Check if given device has generated PME.
2304 * @dev: Device to check.
2306 * Check the PME status of the device and if set, clear it and clear PME enable
2307 * (if set). Return 'true' if PME status and PME enable were both set or
2308 * 'false' otherwise.
2310 bool pci_check_pme_status(struct pci_dev *dev)
2319 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
2320 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
2321 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
2324 /* Clear PME status. */
2325 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2326 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
2327 /* Disable PME to avoid interrupt flood. */
2328 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2332 pci_write_config_word(dev, pmcsr_pos, pmcsr);
2338 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2339 * @dev: Device to handle.
2340 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
2342 * Check if @dev has generated PME and queue a resume request for it in that
2345 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
2347 if (pme_poll_reset && dev->pme_poll)
2348 dev->pme_poll = false;
2350 if (pci_check_pme_status(dev)) {
2351 pci_wakeup_event(dev);
2352 pm_request_resume(&dev->dev);
2358 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2359 * @bus: Top bus of the subtree to walk.
2361 void pci_pme_wakeup_bus(struct pci_bus *bus)
2364 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
2369 * pci_pme_capable - check the capability of PCI device to generate PME#
2370 * @dev: PCI device to handle.
2371 * @state: PCI state from which device will issue PME#.
2373 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
2378 return !!(dev->pme_support & (1 << state));
2380 EXPORT_SYMBOL(pci_pme_capable);
2382 static void pci_pme_list_scan(struct work_struct *work)
2384 struct pci_pme_device *pme_dev, *n;
2386 mutex_lock(&pci_pme_list_mutex);
2387 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
2388 if (pme_dev->dev->pme_poll) {
2389 struct pci_dev *bridge;
2391 bridge = pme_dev->dev->bus->self;
2393 * If bridge is in low power state, the
2394 * configuration space of subordinate devices
2395 * may be not accessible
2397 if (bridge && bridge->current_state != PCI_D0)
2400 * If the device is in D3cold it should not be
2403 if (pme_dev->dev->current_state == PCI_D3cold)
2406 pci_pme_wakeup(pme_dev->dev, NULL);
2408 list_del(&pme_dev->list);
2412 if (!list_empty(&pci_pme_list))
2413 queue_delayed_work(system_freezable_wq, &pci_pme_work,
2414 msecs_to_jiffies(PME_TIMEOUT));
2415 mutex_unlock(&pci_pme_list_mutex);
2418 static void __pci_pme_active(struct pci_dev *dev, bool enable)
2422 if (!dev->pme_support)
2425 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2426 /* Clear PME_Status by writing 1 to it and enable PME# */
2427 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
2429 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2431 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2435 * pci_pme_restore - Restore PME configuration after config space restore.
2436 * @dev: PCI device to update.
2438 void pci_pme_restore(struct pci_dev *dev)
2442 if (!dev->pme_support)
2445 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2446 if (dev->wakeup_prepared) {
2447 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2448 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
2450 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2451 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2453 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2457 * pci_pme_active - enable or disable PCI device's PME# function
2458 * @dev: PCI device to handle.
2459 * @enable: 'true' to enable PME# generation; 'false' to disable it.
2461 * The caller must verify that the device is capable of generating PME# before
2462 * calling this function with @enable equal to 'true'.
2464 void pci_pme_active(struct pci_dev *dev, bool enable)
2466 __pci_pme_active(dev, enable);
2469 * PCI (as opposed to PCIe) PME requires that the device have
2470 * its PME# line hooked up correctly. Not all hardware vendors
2471 * do this, so the PME never gets delivered and the device
2472 * remains asleep. The easiest way around this is to
2473 * periodically walk the list of suspended devices and check
2474 * whether any have their PME flag set. The assumption is that
2475 * we'll wake up often enough anyway that this won't be a huge
2476 * hit, and the power savings from the devices will still be a
2479 * Although PCIe uses in-band PME message instead of PME# line
2480 * to report PME, PME does not work for some PCIe devices in
2481 * reality. For example, there are devices that set their PME
2482 * status bits, but don't really bother to send a PME message;
2483 * there are PCI Express Root Ports that don't bother to
2484 * trigger interrupts when they receive PME messages from the
2485 * devices below. So PME poll is used for PCIe devices too.
2488 if (dev->pme_poll) {
2489 struct pci_pme_device *pme_dev;
2491 pme_dev = kmalloc(sizeof(struct pci_pme_device),
2494 pci_warn(dev, "can't enable PME#\n");
2498 mutex_lock(&pci_pme_list_mutex);
2499 list_add(&pme_dev->list, &pci_pme_list);
2500 if (list_is_singular(&pci_pme_list))
2501 queue_delayed_work(system_freezable_wq,
2503 msecs_to_jiffies(PME_TIMEOUT));
2504 mutex_unlock(&pci_pme_list_mutex);
2506 mutex_lock(&pci_pme_list_mutex);
2507 list_for_each_entry(pme_dev, &pci_pme_list, list) {
2508 if (pme_dev->dev == dev) {
2509 list_del(&pme_dev->list);
2514 mutex_unlock(&pci_pme_list_mutex);
2518 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
2520 EXPORT_SYMBOL(pci_pme_active);
2523 * __pci_enable_wake - enable PCI device as wakeup event source
2524 * @dev: PCI device affected
2525 * @state: PCI state from which device will issue wakeup events
2526 * @enable: True to enable event generation; false to disable
2528 * This enables the device as a wakeup event source, or disables it.
2529 * When such events involves platform-specific hooks, those hooks are
2530 * called automatically by this routine.
2532 * Devices with legacy power management (no standard PCI PM capabilities)
2533 * always require such platform hooks.
2536 * 0 is returned on success
2537 * -EINVAL is returned if device is not supposed to wake up the system
2538 * Error code depending on the platform is returned if both the platform and
2539 * the native mechanism fail to enable the generation of wake-up events
2541 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
2546 * Bridges that are not power-manageable directly only signal
2547 * wakeup on behalf of subordinate devices which is set up
2548 * elsewhere, so skip them. However, bridges that are
2549 * power-manageable may signal wakeup for themselves (for example,
2550 * on a hotplug event) and they need to be covered here.
2552 if (!pci_power_manageable(dev))
2555 /* Don't do the same thing twice in a row for one device. */
2556 if (!!enable == !!dev->wakeup_prepared)
2560 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2561 * Anderson we should be doing PME# wake enable followed by ACPI wake
2562 * enable. To disable wake-up we call the platform first, for symmetry.
2569 * Enable PME signaling if the device can signal PME from
2570 * D3cold regardless of whether or not it can signal PME from
2571 * the current target state, because that will allow it to
2572 * signal PME when the hierarchy above it goes into D3cold and
2573 * the device itself ends up in D3cold as a result of that.
2575 if (pci_pme_capable(dev, state) || pci_pme_capable(dev, PCI_D3cold))
2576 pci_pme_active(dev, true);
2579 error = platform_pci_set_wakeup(dev, true);
2583 dev->wakeup_prepared = true;
2585 platform_pci_set_wakeup(dev, false);
2586 pci_pme_active(dev, false);
2587 dev->wakeup_prepared = false;
2594 * pci_enable_wake - change wakeup settings for a PCI device
2595 * @pci_dev: Target device
2596 * @state: PCI state from which device will issue wakeup events
2597 * @enable: Whether or not to enable event generation
2599 * If @enable is set, check device_may_wakeup() for the device before calling
2600 * __pci_enable_wake() for it.
2602 int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable)
2604 if (enable && !device_may_wakeup(&pci_dev->dev))
2607 return __pci_enable_wake(pci_dev, state, enable);
2609 EXPORT_SYMBOL(pci_enable_wake);
2612 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2613 * @dev: PCI device to prepare
2614 * @enable: True to enable wake-up event generation; false to disable
2616 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2617 * and this function allows them to set that up cleanly - pci_enable_wake()
2618 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2619 * ordering constraints.
2621 * This function only returns error code if the device is not allowed to wake
2622 * up the system from sleep or it is not capable of generating PME# from both
2623 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2625 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2627 return pci_pme_capable(dev, PCI_D3cold) ?
2628 pci_enable_wake(dev, PCI_D3cold, enable) :
2629 pci_enable_wake(dev, PCI_D3hot, enable);
2631 EXPORT_SYMBOL(pci_wake_from_d3);
2634 * pci_target_state - find an appropriate low power state for a given PCI dev
2636 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2638 * Use underlying platform code to find a supported low power state for @dev.
2639 * If the platform can't manage @dev, return the deepest state from which it
2640 * can generate wake events, based on any available PME info.
2642 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2644 if (platform_pci_power_manageable(dev)) {
2646 * Call the platform to find the target state for the device.
2648 pci_power_t state = platform_pci_choose_state(dev);
2651 case PCI_POWER_ERROR:
2657 if (pci_no_d1d2(dev))
2665 * If the device is in D3cold even though it's not power-manageable by
2666 * the platform, it may have been powered down by non-standard means.
2667 * Best to let it slumber.
2669 if (dev->current_state == PCI_D3cold)
2671 else if (!dev->pm_cap)
2674 if (wakeup && dev->pme_support) {
2675 pci_power_t state = PCI_D3hot;
2678 * Find the deepest state from which the device can generate
2681 while (state && !(dev->pme_support & (1 << state)))
2686 else if (dev->pme_support & 1)
2694 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2695 * into a sleep state
2696 * @dev: Device to handle.
2698 * Choose the power state appropriate for the device depending on whether
2699 * it can wake up the system and/or is power manageable by the platform
2700 * (PCI_D3hot is the default) and put the device into that state.
2702 int pci_prepare_to_sleep(struct pci_dev *dev)
2704 bool wakeup = device_may_wakeup(&dev->dev);
2705 pci_power_t target_state = pci_target_state(dev, wakeup);
2708 if (target_state == PCI_POWER_ERROR)
2711 pci_enable_wake(dev, target_state, wakeup);
2713 error = pci_set_power_state(dev, target_state);
2716 pci_enable_wake(dev, target_state, false);
2720 EXPORT_SYMBOL(pci_prepare_to_sleep);
2723 * pci_back_from_sleep - turn PCI device on during system-wide transition
2724 * into working state
2725 * @dev: Device to handle.
2727 * Disable device's system wake-up capability and put it into D0.
2729 int pci_back_from_sleep(struct pci_dev *dev)
2731 int ret = pci_set_power_state(dev, PCI_D0);
2736 pci_enable_wake(dev, PCI_D0, false);
2739 EXPORT_SYMBOL(pci_back_from_sleep);
2742 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2743 * @dev: PCI device being suspended.
2745 * Prepare @dev to generate wake-up events at run time and put it into a low
2748 int pci_finish_runtime_suspend(struct pci_dev *dev)
2750 pci_power_t target_state;
2753 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2754 if (target_state == PCI_POWER_ERROR)
2757 __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2759 error = pci_set_power_state(dev, target_state);
2762 pci_enable_wake(dev, target_state, false);
2768 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2769 * @dev: Device to check.
2771 * Return true if the device itself is capable of generating wake-up events
2772 * (through the platform or using the native PCIe PME) or if the device supports
2773 * PME and one of its upstream bridges can generate wake-up events.
2775 bool pci_dev_run_wake(struct pci_dev *dev)
2777 struct pci_bus *bus = dev->bus;
2779 if (!dev->pme_support)
2782 /* PME-capable in principle, but not from the target power state */
2783 if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2786 if (device_can_wakeup(&dev->dev))
2789 while (bus->parent) {
2790 struct pci_dev *bridge = bus->self;
2792 if (device_can_wakeup(&bridge->dev))
2798 /* We have reached the root bus. */
2800 return device_can_wakeup(bus->bridge);
2804 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2807 * pci_dev_need_resume - Check if it is necessary to resume the device.
2808 * @pci_dev: Device to check.
2810 * Return 'true' if the device is not runtime-suspended or it has to be
2811 * reconfigured due to wakeup settings difference between system and runtime
2812 * suspend, or the current power state of it is not suitable for the upcoming
2813 * (system-wide) transition.
2815 bool pci_dev_need_resume(struct pci_dev *pci_dev)
2817 struct device *dev = &pci_dev->dev;
2818 pci_power_t target_state;
2820 if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev))
2823 target_state = pci_target_state(pci_dev, device_may_wakeup(dev));
2826 * If the earlier platform check has not triggered, D3cold is just power
2827 * removal on top of D3hot, so no need to resume the device in that
2830 return target_state != pci_dev->current_state &&
2831 target_state != PCI_D3cold &&
2832 pci_dev->current_state != PCI_D3hot;
2836 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2837 * @pci_dev: Device to check.
2839 * If the device is suspended and it is not configured for system wakeup,
2840 * disable PME for it to prevent it from waking up the system unnecessarily.
2842 * Note that if the device's power state is D3cold and the platform check in
2843 * pci_dev_need_resume() has not triggered, the device's configuration need not
2846 void pci_dev_adjust_pme(struct pci_dev *pci_dev)
2848 struct device *dev = &pci_dev->dev;
2850 spin_lock_irq(&dev->power.lock);
2852 if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) &&
2853 pci_dev->current_state < PCI_D3cold)
2854 __pci_pme_active(pci_dev, false);
2856 spin_unlock_irq(&dev->power.lock);
2860 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2861 * @pci_dev: Device to handle.
2863 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2864 * it might have been disabled during the prepare phase of system suspend if
2865 * the device was not configured for system wakeup.
2867 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2869 struct device *dev = &pci_dev->dev;
2871 if (!pci_dev_run_wake(pci_dev))
2874 spin_lock_irq(&dev->power.lock);
2876 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2877 __pci_pme_active(pci_dev, true);
2879 spin_unlock_irq(&dev->power.lock);
2883 * pci_choose_state - Choose the power state of a PCI device.
2884 * @dev: Target PCI device.
2885 * @state: Target state for the whole system.
2887 * Returns PCI power state suitable for @dev and @state.
2889 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
2891 if (state.event == PM_EVENT_ON)
2894 return pci_target_state(dev, false);
2896 EXPORT_SYMBOL(pci_choose_state);
2898 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2900 struct device *dev = &pdev->dev;
2901 struct device *parent = dev->parent;
2904 pm_runtime_get_sync(parent);
2905 pm_runtime_get_noresume(dev);
2907 * pdev->current_state is set to PCI_D3cold during suspending,
2908 * so wait until suspending completes
2910 pm_runtime_barrier(dev);
2912 * Only need to resume devices in D3cold, because config
2913 * registers are still accessible for devices suspended but
2916 if (pdev->current_state == PCI_D3cold)
2917 pm_runtime_resume(dev);
2920 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2922 struct device *dev = &pdev->dev;
2923 struct device *parent = dev->parent;
2925 pm_runtime_put(dev);
2927 pm_runtime_put_sync(parent);
2930 static const struct dmi_system_id bridge_d3_blacklist[] = {
2934 * Gigabyte X299 root port is not marked as hotplug capable
2935 * which allows Linux to power manage it. However, this
2936 * confuses the BIOS SMI handler so don't power manage root
2937 * ports on that system.
2939 .ident = "X299 DESIGNARE EX-CF",
2941 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
2942 DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
2947 * Downstream device is not accessible after putting a root port
2948 * into D3cold and back into D0 on Elo i2.
2952 DMI_MATCH(DMI_SYS_VENDOR, "Elo Touch Solutions"),
2953 DMI_MATCH(DMI_PRODUCT_NAME, "Elo i2"),
2954 DMI_MATCH(DMI_PRODUCT_VERSION, "RevB"),
2962 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2963 * @bridge: Bridge to check
2965 * This function checks if it is possible to move the bridge to D3.
2966 * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
2968 bool pci_bridge_d3_possible(struct pci_dev *bridge)
2970 if (!pci_is_pcie(bridge))
2973 switch (pci_pcie_type(bridge)) {
2974 case PCI_EXP_TYPE_ROOT_PORT:
2975 case PCI_EXP_TYPE_UPSTREAM:
2976 case PCI_EXP_TYPE_DOWNSTREAM:
2977 if (pci_bridge_d3_disable)
2981 * Hotplug ports handled by firmware in System Management Mode
2982 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2984 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge))
2987 if (pci_bridge_d3_force)
2990 /* Even the oldest 2010 Thunderbolt controller supports D3. */
2991 if (bridge->is_thunderbolt)
2994 /* Platform might know better if the bridge supports D3 */
2995 if (platform_pci_bridge_d3(bridge))
2999 * Hotplug ports handled natively by the OS were not validated
3000 * by vendors for runtime D3 at least until 2018 because there
3001 * was no OS support.
3003 if (bridge->is_hotplug_bridge)
3006 if (dmi_check_system(bridge_d3_blacklist))
3010 * It should be safe to put PCIe ports from 2015 or newer
3013 if (dmi_get_bios_year() >= 2015)
3021 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
3023 bool *d3cold_ok = data;
3025 if (/* The device needs to be allowed to go D3cold ... */
3026 dev->no_d3cold || !dev->d3cold_allowed ||
3028 /* ... and if it is wakeup capable to do so from D3cold. */
3029 (device_may_wakeup(&dev->dev) &&
3030 !pci_pme_capable(dev, PCI_D3cold)) ||
3032 /* If it is a bridge it must be allowed to go to D3. */
3033 !pci_power_manageable(dev))
3041 * pci_bridge_d3_update - Update bridge D3 capabilities
3042 * @dev: PCI device which is changed
3044 * Update upstream bridge PM capabilities accordingly depending on if the
3045 * device PM configuration was changed or the device is being removed. The
3046 * change is also propagated upstream.
3048 void pci_bridge_d3_update(struct pci_dev *dev)
3050 bool remove = !device_is_registered(&dev->dev);
3051 struct pci_dev *bridge;
3052 bool d3cold_ok = true;
3054 bridge = pci_upstream_bridge(dev);
3055 if (!bridge || !pci_bridge_d3_possible(bridge))
3059 * If D3 is currently allowed for the bridge, removing one of its
3060 * children won't change that.
3062 if (remove && bridge->bridge_d3)
3066 * If D3 is currently allowed for the bridge and a child is added or
3067 * changed, disallowance of D3 can only be caused by that child, so
3068 * we only need to check that single device, not any of its siblings.
3070 * If D3 is currently not allowed for the bridge, checking the device
3071 * first may allow us to skip checking its siblings.
3074 pci_dev_check_d3cold(dev, &d3cold_ok);
3077 * If D3 is currently not allowed for the bridge, this may be caused
3078 * either by the device being changed/removed or any of its siblings,
3079 * so we need to go through all children to find out if one of them
3080 * continues to block D3.
3082 if (d3cold_ok && !bridge->bridge_d3)
3083 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
3086 if (bridge->bridge_d3 != d3cold_ok) {
3087 bridge->bridge_d3 = d3cold_ok;
3088 /* Propagate change to upstream bridges */
3089 pci_bridge_d3_update(bridge);
3094 * pci_d3cold_enable - Enable D3cold for device
3095 * @dev: PCI device to handle
3097 * This function can be used in drivers to enable D3cold from the device
3098 * they handle. It also updates upstream PCI bridge PM capabilities
3101 void pci_d3cold_enable(struct pci_dev *dev)
3103 if (dev->no_d3cold) {
3104 dev->no_d3cold = false;
3105 pci_bridge_d3_update(dev);
3108 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
3111 * pci_d3cold_disable - Disable D3cold for device
3112 * @dev: PCI device to handle
3114 * This function can be used in drivers to disable D3cold from the device
3115 * they handle. It also updates upstream PCI bridge PM capabilities
3118 void pci_d3cold_disable(struct pci_dev *dev)
3120 if (!dev->no_d3cold) {
3121 dev->no_d3cold = true;
3122 pci_bridge_d3_update(dev);
3125 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
3128 * pci_pm_init - Initialize PM functions of given PCI device
3129 * @dev: PCI device to handle.
3131 void pci_pm_init(struct pci_dev *dev)
3137 pm_runtime_forbid(&dev->dev);
3138 pm_runtime_set_active(&dev->dev);
3139 pm_runtime_enable(&dev->dev);
3140 device_enable_async_suspend(&dev->dev);
3141 dev->wakeup_prepared = false;
3144 dev->pme_support = 0;
3146 /* find PCI PM capability in list */
3147 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3150 /* Check device's ability to generate PME# */
3151 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
3153 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
3154 pci_err(dev, "unsupported PM cap regs version (%u)\n",
3155 pmc & PCI_PM_CAP_VER_MASK);
3160 dev->d3hot_delay = PCI_PM_D3HOT_WAIT;
3161 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
3162 dev->bridge_d3 = pci_bridge_d3_possible(dev);
3163 dev->d3cold_allowed = true;
3165 dev->d1_support = false;
3166 dev->d2_support = false;
3167 if (!pci_no_d1d2(dev)) {
3168 if (pmc & PCI_PM_CAP_D1)
3169 dev->d1_support = true;
3170 if (pmc & PCI_PM_CAP_D2)
3171 dev->d2_support = true;
3173 if (dev->d1_support || dev->d2_support)
3174 pci_info(dev, "supports%s%s\n",
3175 dev->d1_support ? " D1" : "",
3176 dev->d2_support ? " D2" : "");
3179 pmc &= PCI_PM_CAP_PME_MASK;
3181 pci_info(dev, "PME# supported from%s%s%s%s%s\n",
3182 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
3183 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
3184 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
3185 (pmc & PCI_PM_CAP_PME_D3hot) ? " D3hot" : "",
3186 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
3187 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
3188 dev->pme_poll = true;
3190 * Make device's PM flags reflect the wake-up capability, but
3191 * let the user space enable it to wake up the system as needed.
3193 device_set_wakeup_capable(&dev->dev, true);
3194 /* Disable the PME# generation functionality */
3195 pci_pme_active(dev, false);
3198 pci_read_config_word(dev, PCI_STATUS, &status);
3199 if (status & PCI_STATUS_IMM_READY)
3203 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
3205 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
3209 case PCI_EA_P_VF_MEM:
3210 flags |= IORESOURCE_MEM;
3212 case PCI_EA_P_MEM_PREFETCH:
3213 case PCI_EA_P_VF_MEM_PREFETCH:
3214 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
3217 flags |= IORESOURCE_IO;
3226 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
3229 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
3230 return &dev->resource[bei];
3231 #ifdef CONFIG_PCI_IOV
3232 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
3233 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
3234 return &dev->resource[PCI_IOV_RESOURCES +
3235 bei - PCI_EA_BEI_VF_BAR0];
3237 else if (bei == PCI_EA_BEI_ROM)
3238 return &dev->resource[PCI_ROM_RESOURCE];
3243 /* Read an Enhanced Allocation (EA) entry */
3244 static int pci_ea_read(struct pci_dev *dev, int offset)
3246 struct resource *res;
3247 int ent_size, ent_offset = offset;
3248 resource_size_t start, end;
3249 unsigned long flags;
3250 u32 dw0, bei, base, max_offset;
3252 bool support_64 = (sizeof(resource_size_t) >= 8);
3254 pci_read_config_dword(dev, ent_offset, &dw0);
3257 /* Entry size field indicates DWORDs after 1st */
3258 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
3260 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
3263 bei = (dw0 & PCI_EA_BEI) >> 4;
3264 prop = (dw0 & PCI_EA_PP) >> 8;
3267 * If the Property is in the reserved range, try the Secondary
3270 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
3271 prop = (dw0 & PCI_EA_SP) >> 16;
3272 if (prop > PCI_EA_P_BRIDGE_IO)
3275 res = pci_ea_get_resource(dev, bei, prop);
3277 pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
3281 flags = pci_ea_flags(dev, prop);
3283 pci_err(dev, "Unsupported EA properties: %#x\n", prop);
3288 pci_read_config_dword(dev, ent_offset, &base);
3289 start = (base & PCI_EA_FIELD_MASK);
3292 /* Read MaxOffset */
3293 pci_read_config_dword(dev, ent_offset, &max_offset);
3296 /* Read Base MSBs (if 64-bit entry) */
3297 if (base & PCI_EA_IS_64) {
3300 pci_read_config_dword(dev, ent_offset, &base_upper);
3303 flags |= IORESOURCE_MEM_64;
3305 /* entry starts above 32-bit boundary, can't use */
3306 if (!support_64 && base_upper)
3310 start |= ((u64)base_upper << 32);
3313 end = start + (max_offset | 0x03);
3315 /* Read MaxOffset MSBs (if 64-bit entry) */
3316 if (max_offset & PCI_EA_IS_64) {
3317 u32 max_offset_upper;
3319 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
3322 flags |= IORESOURCE_MEM_64;
3324 /* entry too big, can't use */
3325 if (!support_64 && max_offset_upper)
3329 end += ((u64)max_offset_upper << 32);
3333 pci_err(dev, "EA Entry crosses address boundary\n");
3337 if (ent_size != ent_offset - offset) {
3338 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
3339 ent_size, ent_offset - offset);
3343 res->name = pci_name(dev);
3348 if (bei <= PCI_EA_BEI_BAR5)
3349 pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3351 else if (bei == PCI_EA_BEI_ROM)
3352 pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
3354 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
3355 pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3356 bei - PCI_EA_BEI_VF_BAR0, res, prop);
3358 pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
3362 return offset + ent_size;
3365 /* Enhanced Allocation Initialization */
3366 void pci_ea_init(struct pci_dev *dev)
3373 /* find PCI EA capability in list */
3374 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
3378 /* determine the number of entries */
3379 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
3381 num_ent &= PCI_EA_NUM_ENT_MASK;
3383 offset = ea + PCI_EA_FIRST_ENT;
3385 /* Skip DWORD 2 for type 1 functions */
3386 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
3389 /* parse each EA entry */
3390 for (i = 0; i < num_ent; ++i)
3391 offset = pci_ea_read(dev, offset);
3394 static void pci_add_saved_cap(struct pci_dev *pci_dev,
3395 struct pci_cap_saved_state *new_cap)
3397 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
3401 * _pci_add_cap_save_buffer - allocate buffer for saving given
3402 * capability registers
3403 * @dev: the PCI device
3404 * @cap: the capability to allocate the buffer for
3405 * @extended: Standard or Extended capability ID
3406 * @size: requested size of the buffer
3408 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
3409 bool extended, unsigned int size)
3412 struct pci_cap_saved_state *save_state;
3415 pos = pci_find_ext_capability(dev, cap);
3417 pos = pci_find_capability(dev, cap);
3422 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
3426 save_state->cap.cap_nr = cap;
3427 save_state->cap.cap_extended = extended;
3428 save_state->cap.size = size;
3429 pci_add_saved_cap(dev, save_state);
3434 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
3436 return _pci_add_cap_save_buffer(dev, cap, false, size);
3439 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
3441 return _pci_add_cap_save_buffer(dev, cap, true, size);
3445 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3446 * @dev: the PCI device
3448 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
3452 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
3453 PCI_EXP_SAVE_REGS * sizeof(u16));
3455 pci_err(dev, "unable to preallocate PCI Express save buffer\n");
3457 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
3459 pci_err(dev, "unable to preallocate PCI-X save buffer\n");
3461 error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
3464 pci_err(dev, "unable to allocate suspend buffer for LTR\n");
3466 pci_allocate_vc_save_buffers(dev);
3469 void pci_free_cap_save_buffers(struct pci_dev *dev)
3471 struct pci_cap_saved_state *tmp;
3472 struct hlist_node *n;
3474 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
3479 * pci_configure_ari - enable or disable ARI forwarding
3480 * @dev: the PCI device
3482 * If @dev and its upstream bridge both support ARI, enable ARI in the
3483 * bridge. Otherwise, disable ARI in the bridge.
3485 void pci_configure_ari(struct pci_dev *dev)
3488 struct pci_dev *bridge;
3490 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
3493 bridge = dev->bus->self;
3497 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3498 if (!(cap & PCI_EXP_DEVCAP2_ARI))
3501 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
3502 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
3503 PCI_EXP_DEVCTL2_ARI);
3504 bridge->ari_enabled = 1;
3506 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
3507 PCI_EXP_DEVCTL2_ARI);
3508 bridge->ari_enabled = 0;
3512 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
3517 pos = pdev->acs_cap;
3522 * Except for egress control, capabilities are either required
3523 * or only required if controllable. Features missing from the
3524 * capability field can therefore be assumed as hard-wired enabled.
3526 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
3527 acs_flags &= (cap | PCI_ACS_EC);
3529 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
3530 return (ctrl & acs_flags) == acs_flags;
3534 * pci_acs_enabled - test ACS against required flags for a given device
3535 * @pdev: device to test
3536 * @acs_flags: required PCI ACS flags
3538 * Return true if the device supports the provided flags. Automatically
3539 * filters out flags that are not implemented on multifunction devices.
3541 * Note that this interface checks the effective ACS capabilities of the
3542 * device rather than the actual capabilities. For instance, most single
3543 * function endpoints are not required to support ACS because they have no
3544 * opportunity for peer-to-peer access. We therefore return 'true'
3545 * regardless of whether the device exposes an ACS capability. This makes
3546 * it much easier for callers of this function to ignore the actual type
3547 * or topology of the device when testing ACS support.
3549 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
3553 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
3558 * Conventional PCI and PCI-X devices never support ACS, either
3559 * effectively or actually. The shared bus topology implies that
3560 * any device on the bus can receive or snoop DMA.
3562 if (!pci_is_pcie(pdev))
3565 switch (pci_pcie_type(pdev)) {
3567 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3568 * but since their primary interface is PCI/X, we conservatively
3569 * handle them as we would a non-PCIe device.
3571 case PCI_EXP_TYPE_PCIE_BRIDGE:
3573 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
3574 * applicable... must never implement an ACS Extended Capability...".
3575 * This seems arbitrary, but we take a conservative interpretation
3576 * of this statement.
3578 case PCI_EXP_TYPE_PCI_BRIDGE:
3579 case PCI_EXP_TYPE_RC_EC:
3582 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3583 * implement ACS in order to indicate their peer-to-peer capabilities,
3584 * regardless of whether they are single- or multi-function devices.
3586 case PCI_EXP_TYPE_DOWNSTREAM:
3587 case PCI_EXP_TYPE_ROOT_PORT:
3588 return pci_acs_flags_enabled(pdev, acs_flags);
3590 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3591 * implemented by the remaining PCIe types to indicate peer-to-peer
3592 * capabilities, but only when they are part of a multifunction
3593 * device. The footnote for section 6.12 indicates the specific
3594 * PCIe types included here.
3596 case PCI_EXP_TYPE_ENDPOINT:
3597 case PCI_EXP_TYPE_UPSTREAM:
3598 case PCI_EXP_TYPE_LEG_END:
3599 case PCI_EXP_TYPE_RC_END:
3600 if (!pdev->multifunction)
3603 return pci_acs_flags_enabled(pdev, acs_flags);
3607 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3608 * to single function devices with the exception of downstream ports.
3614 * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3615 * @start: starting downstream device
3616 * @end: ending upstream device or NULL to search to the root bus
3617 * @acs_flags: required flags
3619 * Walk up a device tree from start to end testing PCI ACS support. If
3620 * any step along the way does not support the required flags, return false.
3622 bool pci_acs_path_enabled(struct pci_dev *start,
3623 struct pci_dev *end, u16 acs_flags)
3625 struct pci_dev *pdev, *parent = start;
3630 if (!pci_acs_enabled(pdev, acs_flags))
3633 if (pci_is_root_bus(pdev->bus))
3634 return (end == NULL);
3636 parent = pdev->bus->self;
3637 } while (pdev != end);
3643 * pci_acs_init - Initialize ACS if hardware supports it
3644 * @dev: the PCI device
3646 void pci_acs_init(struct pci_dev *dev)
3648 dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3651 * Attempt to enable ACS regardless of capability because some Root
3652 * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have
3653 * the standard ACS capability but still support ACS via those
3656 pci_enable_acs(dev);
3660 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3664 * Helper to find the position of the ctrl register for a BAR.
3665 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3666 * Returns -ENOENT if no ctrl register for the BAR could be found.
3668 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
3670 unsigned int pos, nbars, i;
3673 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3677 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3678 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
3679 PCI_REBAR_CTRL_NBAR_SHIFT;
3681 for (i = 0; i < nbars; i++, pos += 8) {
3684 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3685 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
3694 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3696 * @bar: BAR to query
3698 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3699 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3701 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3706 pos = pci_rebar_find_pos(pdev, bar);
3710 pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3711 cap &= PCI_REBAR_CAP_SIZES;
3713 /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */
3714 if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f &&
3715 bar == 0 && cap == 0x7000)
3720 EXPORT_SYMBOL(pci_rebar_get_possible_sizes);
3723 * pci_rebar_get_current_size - get the current size of a BAR
3725 * @bar: BAR to set size to
3727 * Read the size of a BAR from the resizable BAR config.
3728 * Returns size if found or negative error code.
3730 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3735 pos = pci_rebar_find_pos(pdev, bar);
3739 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3740 return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT;
3744 * pci_rebar_set_size - set a new size for a BAR
3746 * @bar: BAR to set size to
3747 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3749 * Set the new size of a BAR as defined in the spec.
3750 * Returns zero if resizing was successful, error code otherwise.
3752 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3757 pos = pci_rebar_find_pos(pdev, bar);
3761 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3762 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3763 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
3764 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3769 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3770 * @dev: the PCI device
3771 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3772 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3773 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3774 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3776 * Return 0 if all upstream bridges support AtomicOp routing, egress
3777 * blocking is disabled on all upstream ports, and the root port supports
3778 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3779 * AtomicOp completion), or negative otherwise.
3781 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3783 struct pci_bus *bus = dev->bus;
3784 struct pci_dev *bridge;
3788 * Per PCIe r5.0, sec 9.3.5.10, the AtomicOp Requester Enable bit
3789 * in Device Control 2 is reserved in VFs and the PF value applies
3790 * to all associated VFs.
3795 if (!pci_is_pcie(dev))
3799 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3800 * AtomicOp requesters. For now, we only support endpoints as
3801 * requesters and root ports as completers. No endpoints as
3802 * completers, and no peer-to-peer.
3805 switch (pci_pcie_type(dev)) {
3806 case PCI_EXP_TYPE_ENDPOINT:
3807 case PCI_EXP_TYPE_LEG_END:
3808 case PCI_EXP_TYPE_RC_END:
3814 while (bus->parent) {
3817 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3819 switch (pci_pcie_type(bridge)) {
3820 /* Ensure switch ports support AtomicOp routing */
3821 case PCI_EXP_TYPE_UPSTREAM:
3822 case PCI_EXP_TYPE_DOWNSTREAM:
3823 if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3827 /* Ensure root port supports all the sizes we care about */
3828 case PCI_EXP_TYPE_ROOT_PORT:
3829 if ((cap & cap_mask) != cap_mask)
3834 /* Ensure upstream ports don't block AtomicOps on egress */
3835 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) {
3836 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3838 if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3845 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3846 PCI_EXP_DEVCTL2_ATOMIC_REQ);
3849 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
3852 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3853 * @dev: the PCI device
3854 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3856 * Perform INTx swizzling for a device behind one level of bridge. This is
3857 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3858 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3859 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3860 * the PCI Express Base Specification, Revision 2.1)
3862 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3866 if (pci_ari_enabled(dev->bus))
3869 slot = PCI_SLOT(dev->devfn);
3871 return (((pin - 1) + slot) % 4) + 1;
3874 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3882 while (!pci_is_root_bus(dev->bus)) {
3883 pin = pci_swizzle_interrupt_pin(dev, pin);
3884 dev = dev->bus->self;
3891 * pci_common_swizzle - swizzle INTx all the way to root bridge
3892 * @dev: the PCI device
3893 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3895 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3896 * bridges all the way up to a PCI root bus.
3898 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3902 while (!pci_is_root_bus(dev->bus)) {
3903 pin = pci_swizzle_interrupt_pin(dev, pin);
3904 dev = dev->bus->self;
3907 return PCI_SLOT(dev->devfn);
3909 EXPORT_SYMBOL_GPL(pci_common_swizzle);
3912 * pci_release_region - Release a PCI bar
3913 * @pdev: PCI device whose resources were previously reserved by
3914 * pci_request_region()
3915 * @bar: BAR to release
3917 * Releases the PCI I/O and memory resources previously reserved by a
3918 * successful call to pci_request_region(). Call this function only
3919 * after all use of the PCI regions has ceased.
3921 void pci_release_region(struct pci_dev *pdev, int bar)
3923 struct pci_devres *dr;
3925 if (pci_resource_len(pdev, bar) == 0)
3927 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3928 release_region(pci_resource_start(pdev, bar),
3929 pci_resource_len(pdev, bar));
3930 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3931 release_mem_region(pci_resource_start(pdev, bar),
3932 pci_resource_len(pdev, bar));
3934 dr = find_pci_dr(pdev);
3936 dr->region_mask &= ~(1 << bar);
3938 EXPORT_SYMBOL(pci_release_region);
3941 * __pci_request_region - Reserved PCI I/O and memory resource
3942 * @pdev: PCI device whose resources are to be reserved
3943 * @bar: BAR to be reserved
3944 * @res_name: Name to be associated with resource.
3945 * @exclusive: whether the region access is exclusive or not
3947 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3948 * being reserved by owner @res_name. Do not access any
3949 * address inside the PCI regions unless this call returns
3952 * If @exclusive is set, then the region is marked so that userspace
3953 * is explicitly not allowed to map the resource via /dev/mem or
3954 * sysfs MMIO access.
3956 * Returns 0 on success, or %EBUSY on error. A warning
3957 * message is also printed on failure.
3959 static int __pci_request_region(struct pci_dev *pdev, int bar,
3960 const char *res_name, int exclusive)
3962 struct pci_devres *dr;
3964 if (pci_resource_len(pdev, bar) == 0)
3967 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3968 if (!request_region(pci_resource_start(pdev, bar),
3969 pci_resource_len(pdev, bar), res_name))
3971 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3972 if (!__request_mem_region(pci_resource_start(pdev, bar),
3973 pci_resource_len(pdev, bar), res_name,
3978 dr = find_pci_dr(pdev);
3980 dr->region_mask |= 1 << bar;
3985 pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
3986 &pdev->resource[bar]);
3991 * pci_request_region - Reserve PCI I/O and memory resource
3992 * @pdev: PCI device whose resources are to be reserved
3993 * @bar: BAR to be reserved
3994 * @res_name: Name to be associated with resource
3996 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3997 * being reserved by owner @res_name. Do not access any
3998 * address inside the PCI regions unless this call returns
4001 * Returns 0 on success, or %EBUSY on error. A warning
4002 * message is also printed on failure.
4004 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
4006 return __pci_request_region(pdev, bar, res_name, 0);
4008 EXPORT_SYMBOL(pci_request_region);
4011 * pci_release_selected_regions - Release selected PCI I/O and memory resources
4012 * @pdev: PCI device whose resources were previously reserved
4013 * @bars: Bitmask of BARs to be released
4015 * Release selected PCI I/O and memory resources previously reserved.
4016 * Call this function only after all use of the PCI regions has ceased.
4018 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
4022 for (i = 0; i < PCI_STD_NUM_BARS; i++)
4023 if (bars & (1 << i))
4024 pci_release_region(pdev, i);
4026 EXPORT_SYMBOL(pci_release_selected_regions);
4028 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
4029 const char *res_name, int excl)
4033 for (i = 0; i < PCI_STD_NUM_BARS; i++)
4034 if (bars & (1 << i))
4035 if (__pci_request_region(pdev, i, res_name, excl))
4041 if (bars & (1 << i))
4042 pci_release_region(pdev, i);
4049 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
4050 * @pdev: PCI device whose resources are to be reserved
4051 * @bars: Bitmask of BARs to be requested
4052 * @res_name: Name to be associated with resource
4054 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
4055 const char *res_name)
4057 return __pci_request_selected_regions(pdev, bars, res_name, 0);
4059 EXPORT_SYMBOL(pci_request_selected_regions);
4061 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
4062 const char *res_name)
4064 return __pci_request_selected_regions(pdev, bars, res_name,
4065 IORESOURCE_EXCLUSIVE);
4067 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
4070 * pci_release_regions - Release reserved PCI I/O and memory resources
4071 * @pdev: PCI device whose resources were previously reserved by
4072 * pci_request_regions()
4074 * Releases all PCI I/O and memory resources previously reserved by a
4075 * successful call to pci_request_regions(). Call this function only
4076 * after all use of the PCI regions has ceased.
4079 void pci_release_regions(struct pci_dev *pdev)
4081 pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1);
4083 EXPORT_SYMBOL(pci_release_regions);
4086 * pci_request_regions - Reserve PCI I/O and memory resources
4087 * @pdev: PCI device whose resources are to be reserved
4088 * @res_name: Name to be associated with resource.
4090 * Mark all PCI regions associated with PCI device @pdev as
4091 * being reserved by owner @res_name. Do not access any
4092 * address inside the PCI regions unless this call returns
4095 * Returns 0 on success, or %EBUSY on error. A warning
4096 * message is also printed on failure.
4098 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
4100 return pci_request_selected_regions(pdev,
4101 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4103 EXPORT_SYMBOL(pci_request_regions);
4106 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4107 * @pdev: PCI device whose resources are to be reserved
4108 * @res_name: Name to be associated with resource.
4110 * Mark all PCI regions associated with PCI device @pdev as being reserved
4111 * by owner @res_name. Do not access any address inside the PCI regions
4112 * unless this call returns successfully.
4114 * pci_request_regions_exclusive() will mark the region so that /dev/mem
4115 * and the sysfs MMIO access will not be allowed.
4117 * Returns 0 on success, or %EBUSY on error. A warning message is also
4118 * printed on failure.
4120 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
4122 return pci_request_selected_regions_exclusive(pdev,
4123 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4125 EXPORT_SYMBOL(pci_request_regions_exclusive);
4128 * Record the PCI IO range (expressed as CPU physical address + size).
4129 * Return a negative value if an error has occurred, zero otherwise
4131 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
4132 resource_size_t size)
4136 struct logic_pio_hwaddr *range;
4138 if (!size || addr + size < addr)
4141 range = kzalloc(sizeof(*range), GFP_ATOMIC);
4145 range->fwnode = fwnode;
4147 range->hw_start = addr;
4148 range->flags = LOGIC_PIO_CPU_MMIO;
4150 ret = logic_pio_register_range(range);
4154 /* Ignore duplicates due to deferred probing */
4162 phys_addr_t pci_pio_to_address(unsigned long pio)
4164 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
4167 if (pio >= MMIO_UPPER_LIMIT)
4170 address = logic_pio_to_hwaddr(pio);
4175 EXPORT_SYMBOL_GPL(pci_pio_to_address);
4177 unsigned long __weak pci_address_to_pio(phys_addr_t address)
4180 return logic_pio_trans_cpuaddr(address);
4182 if (address > IO_SPACE_LIMIT)
4183 return (unsigned long)-1;
4185 return (unsigned long) address;
4190 * pci_remap_iospace - Remap the memory mapped I/O space
4191 * @res: Resource describing the I/O space
4192 * @phys_addr: physical address of range to be mapped
4194 * Remap the memory mapped I/O space described by the @res and the CPU
4195 * physical address @phys_addr into virtual address space. Only
4196 * architectures that have memory mapped IO functions defined (and the
4197 * PCI_IOBASE value defined) should call this function.
4199 #ifndef pci_remap_iospace
4200 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
4202 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4203 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4205 if (!(res->flags & IORESOURCE_IO))
4208 if (res->end > IO_SPACE_LIMIT)
4211 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
4212 pgprot_device(PAGE_KERNEL));
4215 * This architecture does not have memory mapped I/O space,
4216 * so this function should never be called
4218 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
4222 EXPORT_SYMBOL(pci_remap_iospace);
4226 * pci_unmap_iospace - Unmap the memory mapped I/O space
4227 * @res: resource to be unmapped
4229 * Unmap the CPU virtual address @res from virtual address space. Only
4230 * architectures that have memory mapped IO functions defined (and the
4231 * PCI_IOBASE value defined) should call this function.
4233 void pci_unmap_iospace(struct resource *res)
4235 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4236 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4238 vunmap_range(vaddr, vaddr + resource_size(res));
4241 EXPORT_SYMBOL(pci_unmap_iospace);
4243 static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
4245 struct resource **res = ptr;
4247 pci_unmap_iospace(*res);
4251 * devm_pci_remap_iospace - Managed pci_remap_iospace()
4252 * @dev: Generic device to remap IO address for
4253 * @res: Resource describing the I/O space
4254 * @phys_addr: physical address of range to be mapped
4256 * Managed pci_remap_iospace(). Map is automatically unmapped on driver
4259 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
4260 phys_addr_t phys_addr)
4262 const struct resource **ptr;
4265 ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
4269 error = pci_remap_iospace(res, phys_addr);
4274 devres_add(dev, ptr);
4279 EXPORT_SYMBOL(devm_pci_remap_iospace);
4282 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4283 * @dev: Generic device to remap IO address for
4284 * @offset: Resource address to map
4285 * @size: Size of map
4287 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
4290 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
4291 resource_size_t offset,
4292 resource_size_t size)
4294 void __iomem **ptr, *addr;
4296 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
4300 addr = pci_remap_cfgspace(offset, size);
4303 devres_add(dev, ptr);
4309 EXPORT_SYMBOL(devm_pci_remap_cfgspace);
4312 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4313 * @dev: generic device to handle the resource for
4314 * @res: configuration space resource to be handled
4316 * Checks that a resource is a valid memory region, requests the memory
4317 * region and ioremaps with pci_remap_cfgspace() API that ensures the
4318 * proper PCI configuration space memory attributes are guaranteed.
4320 * All operations are managed and will be undone on driver detach.
4322 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
4323 * on failure. Usage example::
4325 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4326 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4328 * return PTR_ERR(base);
4330 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
4331 struct resource *res)
4333 resource_size_t size;
4335 void __iomem *dest_ptr;
4339 if (!res || resource_type(res) != IORESOURCE_MEM) {
4340 dev_err(dev, "invalid resource\n");
4341 return IOMEM_ERR_PTR(-EINVAL);
4344 size = resource_size(res);
4347 name = devm_kasprintf(dev, GFP_KERNEL, "%s %s", dev_name(dev),
4350 name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
4352 return IOMEM_ERR_PTR(-ENOMEM);
4354 if (!devm_request_mem_region(dev, res->start, size, name)) {
4355 dev_err(dev, "can't request region for resource %pR\n", res);
4356 return IOMEM_ERR_PTR(-EBUSY);
4359 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
4361 dev_err(dev, "ioremap failed for resource %pR\n", res);
4362 devm_release_mem_region(dev, res->start, size);
4363 dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
4368 EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
4370 static void __pci_set_master(struct pci_dev *dev, bool enable)
4374 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
4376 cmd = old_cmd | PCI_COMMAND_MASTER;
4378 cmd = old_cmd & ~PCI_COMMAND_MASTER;
4379 if (cmd != old_cmd) {
4380 pci_dbg(dev, "%s bus mastering\n",
4381 enable ? "enabling" : "disabling");
4382 pci_write_config_word(dev, PCI_COMMAND, cmd);
4384 dev->is_busmaster = enable;
4388 * pcibios_setup - process "pci=" kernel boot arguments
4389 * @str: string used to pass in "pci=" kernel boot arguments
4391 * Process kernel boot arguments. This is the default implementation.
4392 * Architecture specific implementations can override this as necessary.
4394 char * __weak __init pcibios_setup(char *str)
4400 * pcibios_set_master - enable PCI bus-mastering for device dev
4401 * @dev: the PCI device to enable
4403 * Enables PCI bus-mastering for the device. This is the default
4404 * implementation. Architecture specific implementations can override
4405 * this if necessary.
4407 void __weak pcibios_set_master(struct pci_dev *dev)
4411 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
4412 if (pci_is_pcie(dev))
4415 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
4417 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
4418 else if (lat > pcibios_max_latency)
4419 lat = pcibios_max_latency;
4423 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
4427 * pci_set_master - enables bus-mastering for device dev
4428 * @dev: the PCI device to enable
4430 * Enables bus-mastering on the device and calls pcibios_set_master()
4431 * to do the needed arch specific settings.
4433 void pci_set_master(struct pci_dev *dev)
4435 __pci_set_master(dev, true);
4436 pcibios_set_master(dev);
4438 EXPORT_SYMBOL(pci_set_master);
4441 * pci_clear_master - disables bus-mastering for device dev
4442 * @dev: the PCI device to disable
4444 void pci_clear_master(struct pci_dev *dev)
4446 __pci_set_master(dev, false);
4448 EXPORT_SYMBOL(pci_clear_master);
4451 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4452 * @dev: the PCI device for which MWI is to be enabled
4454 * Helper function for pci_set_mwi.
4455 * Originally copied from drivers/net/acenic.c.
4456 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4458 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4460 int pci_set_cacheline_size(struct pci_dev *dev)
4464 if (!pci_cache_line_size)
4467 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
4468 equal to or multiple of the right value. */
4469 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4470 if (cacheline_size >= pci_cache_line_size &&
4471 (cacheline_size % pci_cache_line_size) == 0)
4474 /* Write the correct value. */
4475 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
4477 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4478 if (cacheline_size == pci_cache_line_size)
4481 pci_dbg(dev, "cache line size of %d is not supported\n",
4482 pci_cache_line_size << 2);
4486 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
4489 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4490 * @dev: the PCI device for which MWI is enabled
4492 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4494 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4496 int pci_set_mwi(struct pci_dev *dev)
4498 #ifdef PCI_DISABLE_MWI
4504 rc = pci_set_cacheline_size(dev);
4508 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4509 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
4510 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
4511 cmd |= PCI_COMMAND_INVALIDATE;
4512 pci_write_config_word(dev, PCI_COMMAND, cmd);
4517 EXPORT_SYMBOL(pci_set_mwi);
4520 * pcim_set_mwi - a device-managed pci_set_mwi()
4521 * @dev: the PCI device for which MWI is enabled
4523 * Managed pci_set_mwi().
4525 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4527 int pcim_set_mwi(struct pci_dev *dev)
4529 struct pci_devres *dr;
4531 dr = find_pci_dr(dev);
4536 return pci_set_mwi(dev);
4538 EXPORT_SYMBOL(pcim_set_mwi);
4541 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4542 * @dev: the PCI device for which MWI is enabled
4544 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4545 * Callers are not required to check the return value.
4547 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4549 int pci_try_set_mwi(struct pci_dev *dev)
4551 #ifdef PCI_DISABLE_MWI
4554 return pci_set_mwi(dev);
4557 EXPORT_SYMBOL(pci_try_set_mwi);
4560 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4561 * @dev: the PCI device to disable
4563 * Disables PCI Memory-Write-Invalidate transaction on the device
4565 void pci_clear_mwi(struct pci_dev *dev)
4567 #ifndef PCI_DISABLE_MWI
4570 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4571 if (cmd & PCI_COMMAND_INVALIDATE) {
4572 cmd &= ~PCI_COMMAND_INVALIDATE;
4573 pci_write_config_word(dev, PCI_COMMAND, cmd);
4577 EXPORT_SYMBOL(pci_clear_mwi);
4580 * pci_disable_parity - disable parity checking for device
4581 * @dev: the PCI device to operate on
4583 * Disable parity checking for device @dev
4585 void pci_disable_parity(struct pci_dev *dev)
4589 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4590 if (cmd & PCI_COMMAND_PARITY) {
4591 cmd &= ~PCI_COMMAND_PARITY;
4592 pci_write_config_word(dev, PCI_COMMAND, cmd);
4597 * pci_intx - enables/disables PCI INTx for device dev
4598 * @pdev: the PCI device to operate on
4599 * @enable: boolean: whether to enable or disable PCI INTx
4601 * Enables/disables PCI INTx for device @pdev
4603 void pci_intx(struct pci_dev *pdev, int enable)
4605 u16 pci_command, new;
4607 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
4610 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
4612 new = pci_command | PCI_COMMAND_INTX_DISABLE;
4614 if (new != pci_command) {
4615 struct pci_devres *dr;
4617 pci_write_config_word(pdev, PCI_COMMAND, new);
4619 dr = find_pci_dr(pdev);
4620 if (dr && !dr->restore_intx) {
4621 dr->restore_intx = 1;
4622 dr->orig_intx = !enable;
4626 EXPORT_SYMBOL_GPL(pci_intx);
4628 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
4630 struct pci_bus *bus = dev->bus;
4631 bool mask_updated = true;
4632 u32 cmd_status_dword;
4633 u16 origcmd, newcmd;
4634 unsigned long flags;
4638 * We do a single dword read to retrieve both command and status.
4639 * Document assumptions that make this possible.
4641 BUILD_BUG_ON(PCI_COMMAND % 4);
4642 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
4644 raw_spin_lock_irqsave(&pci_lock, flags);
4646 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4648 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
4651 * Check interrupt status register to see whether our device
4652 * triggered the interrupt (when masking) or the next IRQ is
4653 * already pending (when unmasking).
4655 if (mask != irq_pending) {
4656 mask_updated = false;
4660 origcmd = cmd_status_dword;
4661 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
4663 newcmd |= PCI_COMMAND_INTX_DISABLE;
4664 if (newcmd != origcmd)
4665 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4668 raw_spin_unlock_irqrestore(&pci_lock, flags);
4670 return mask_updated;
4674 * pci_check_and_mask_intx - mask INTx on pending interrupt
4675 * @dev: the PCI device to operate on
4677 * Check if the device dev has its INTx line asserted, mask it and return
4678 * true in that case. False is returned if no interrupt was pending.
4680 bool pci_check_and_mask_intx(struct pci_dev *dev)
4682 return pci_check_and_set_intx_mask(dev, true);
4684 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
4687 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4688 * @dev: the PCI device to operate on
4690 * Check if the device dev has its INTx line asserted, unmask it if not and
4691 * return true. False is returned and the mask remains active if there was
4692 * still an interrupt pending.
4694 bool pci_check_and_unmask_intx(struct pci_dev *dev)
4696 return pci_check_and_set_intx_mask(dev, false);
4698 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4701 * pci_wait_for_pending_transaction - wait for pending transaction
4702 * @dev: the PCI device to operate on
4704 * Return 0 if transaction is pending 1 otherwise.
4706 int pci_wait_for_pending_transaction(struct pci_dev *dev)
4708 if (!pci_is_pcie(dev))
4711 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4712 PCI_EXP_DEVSTA_TRPND);
4714 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4717 * pcie_flr - initiate a PCIe function level reset
4718 * @dev: device to reset
4720 * Initiate a function level reset unconditionally on @dev without
4721 * checking any flags and DEVCAP
4723 int pcie_flr(struct pci_dev *dev)
4725 if (!pci_wait_for_pending_transaction(dev))
4726 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4728 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4734 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4735 * 100ms, but may silently discard requests while the FLR is in
4736 * progress. Wait 100ms before trying to access the device.
4740 return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4742 EXPORT_SYMBOL_GPL(pcie_flr);
4745 * pcie_reset_flr - initiate a PCIe function level reset
4746 * @dev: device to reset
4747 * @probe: if true, return 0 if device can be reset this way
4749 * Initiate a function level reset on @dev.
4751 int pcie_reset_flr(struct pci_dev *dev, bool probe)
4753 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4756 if (!(dev->devcap & PCI_EXP_DEVCAP_FLR))
4762 return pcie_flr(dev);
4764 EXPORT_SYMBOL_GPL(pcie_reset_flr);
4766 static int pci_af_flr(struct pci_dev *dev, bool probe)
4771 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4775 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4778 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4779 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4786 * Wait for Transaction Pending bit to clear. A word-aligned test
4787 * is used, so we use the control offset rather than status and shift
4788 * the test bit to match.
4790 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4791 PCI_AF_STATUS_TP << 8))
4792 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4794 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4800 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4801 * updated 27 July 2006; a device must complete an FLR within
4802 * 100ms, but may silently discard requests while the FLR is in
4803 * progress. Wait 100ms before trying to access the device.
4807 return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4811 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4812 * @dev: Device to reset.
4813 * @probe: if true, return 0 if the device can be reset this way.
4815 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4816 * unset, it will be reinitialized internally when going from PCI_D3hot to
4817 * PCI_D0. If that's the case and the device is not in a low-power state
4818 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4820 * NOTE: This causes the caller to sleep for twice the device power transition
4821 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4822 * by default (i.e. unless the @dev's d3hot_delay field has a different value).
4823 * Moreover, only devices in D0 can be reset by this function.
4825 static int pci_pm_reset(struct pci_dev *dev, bool probe)
4829 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4832 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4833 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4839 if (dev->current_state != PCI_D0)
4842 csr &= ~PCI_PM_CTRL_STATE_MASK;
4844 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4845 pci_dev_d3_sleep(dev);
4847 csr &= ~PCI_PM_CTRL_STATE_MASK;
4849 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4850 pci_dev_d3_sleep(dev);
4852 return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS);
4856 * pcie_wait_for_link_delay - Wait until link is active or inactive
4857 * @pdev: Bridge device
4858 * @active: waiting for active or inactive?
4859 * @delay: Delay to wait after link has become active (in ms)
4861 * Use this to wait till link becomes active or inactive.
4863 static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active,
4871 * Some controllers might not implement link active reporting. In this
4872 * case, we wait for 1000 ms + any delay requested by the caller.
4874 if (!pdev->link_active_reporting) {
4875 msleep(timeout + delay);
4880 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
4881 * after which we should expect an link active if the reset was
4882 * successful. If so, software must wait a minimum 100ms before sending
4883 * configuration requests to devices downstream this port.
4885 * If the link fails to activate, either the device was physically
4886 * removed or the link is permanently failed.
4891 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
4892 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
4903 return ret == active;
4907 * pcie_wait_for_link - Wait until link is active or inactive
4908 * @pdev: Bridge device
4909 * @active: waiting for active or inactive?
4911 * Use this to wait till link becomes active or inactive.
4913 bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
4915 return pcie_wait_for_link_delay(pdev, active, 100);
4919 * Find maximum D3cold delay required by all the devices on the bus. The
4920 * spec says 100 ms, but firmware can lower it and we allow drivers to
4921 * increase it as well.
4923 * Called with @pci_bus_sem locked for reading.
4925 static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
4927 const struct pci_dev *pdev;
4928 int min_delay = 100;
4931 list_for_each_entry(pdev, &bus->devices, bus_list) {
4932 if (pdev->d3cold_delay < min_delay)
4933 min_delay = pdev->d3cold_delay;
4934 if (pdev->d3cold_delay > max_delay)
4935 max_delay = pdev->d3cold_delay;
4938 return max(min_delay, max_delay);
4942 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
4945 * Handle necessary delays before access to the devices on the secondary
4946 * side of the bridge are permitted after D3cold to D0 transition.
4948 * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For
4949 * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
4952 void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev)
4954 struct pci_dev *child;
4957 if (pci_dev_is_disconnected(dev))
4960 if (!pci_is_bridge(dev) || !dev->bridge_d3)
4963 down_read(&pci_bus_sem);
4966 * We only deal with devices that are present currently on the bus.
4967 * For any hot-added devices the access delay is handled in pciehp
4968 * board_added(). In case of ACPI hotplug the firmware is expected
4969 * to configure the devices before OS is notified.
4971 if (!dev->subordinate || list_empty(&dev->subordinate->devices)) {
4972 up_read(&pci_bus_sem);
4976 /* Take d3cold_delay requirements into account */
4977 delay = pci_bus_max_d3cold_delay(dev->subordinate);
4979 up_read(&pci_bus_sem);
4983 child = list_first_entry(&dev->subordinate->devices, struct pci_dev,
4985 up_read(&pci_bus_sem);
4988 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before
4989 * accessing the device after reset (that is 1000 ms + 100 ms). In
4990 * practice this should not be needed because we don't do power
4991 * management for them (see pci_bridge_d3_possible()).
4993 if (!pci_is_pcie(dev)) {
4994 pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
4995 msleep(1000 + delay);
5000 * For PCIe downstream and root ports that do not support speeds
5001 * greater than 5 GT/s need to wait minimum 100 ms. For higher
5002 * speeds (gen3) we need to wait first for the data link layer to
5005 * However, 100 ms is the minimum and the PCIe spec says the
5006 * software must allow at least 1s before it can determine that the
5007 * device that did not respond is a broken device. There is
5008 * evidence that 100 ms is not always enough, for example certain
5009 * Titan Ridge xHCI controller does not always respond to
5010 * configuration requests if we only wait for 100 ms (see
5011 * https://bugzilla.kernel.org/show_bug.cgi?id=203885).
5013 * Therefore we wait for 100 ms and check for the device presence.
5014 * If it is still not present give it an additional 100 ms.
5016 if (!pcie_downstream_port(dev))
5019 if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {
5020 pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
5023 pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",
5025 if (!pcie_wait_for_link_delay(dev, true, delay)) {
5026 /* Did not train, no need to wait any further */
5027 pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n");
5032 if (!pci_device_is_present(child)) {
5033 pci_dbg(child, "waiting additional %d ms to become accessible\n", delay);
5038 void pci_reset_secondary_bus(struct pci_dev *dev)
5042 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
5043 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
5044 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
5047 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
5048 * this to 2ms to ensure that we meet the minimum requirement.
5052 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
5053 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
5056 * Trhfa for conventional PCI is 2^25 clock cycles.
5057 * Assuming a minimum 33MHz clock this results in a 1s
5058 * delay before we can consider subordinate devices to
5059 * be re-initialized. PCIe has some ways to shorten this,
5060 * but we don't make use of them yet.
5065 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
5067 pci_reset_secondary_bus(dev);
5071 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
5072 * @dev: Bridge device
5074 * Use the bridge control register to assert reset on the secondary bus.
5075 * Devices on the secondary bus are left in power-on state.
5077 int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
5079 pcibios_reset_secondary_bus(dev);
5081 return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
5083 EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
5085 static int pci_parent_bus_reset(struct pci_dev *dev, bool probe)
5087 struct pci_dev *pdev;
5089 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
5090 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5093 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
5100 return pci_bridge_secondary_bus_reset(dev->bus->self);
5103 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, bool probe)
5107 if (!hotplug || !try_module_get(hotplug->owner))
5110 if (hotplug->ops->reset_slot)
5111 rc = hotplug->ops->reset_slot(hotplug, probe);
5113 module_put(hotplug->owner);
5118 static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe)
5120 if (dev->multifunction || dev->subordinate || !dev->slot ||
5121 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5124 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
5127 static int pci_reset_bus_function(struct pci_dev *dev, bool probe)
5131 rc = pci_dev_reset_slot_function(dev, probe);
5134 return pci_parent_bus_reset(dev, probe);
5137 void pci_dev_lock(struct pci_dev *dev)
5139 /* block PM suspend, driver probe, etc. */
5140 device_lock(&dev->dev);
5141 pci_cfg_access_lock(dev);
5143 EXPORT_SYMBOL_GPL(pci_dev_lock);
5145 /* Return 1 on successful lock, 0 on contention */
5146 int pci_dev_trylock(struct pci_dev *dev)
5148 if (device_trylock(&dev->dev)) {
5149 if (pci_cfg_access_trylock(dev))
5151 device_unlock(&dev->dev);
5156 EXPORT_SYMBOL_GPL(pci_dev_trylock);
5158 void pci_dev_unlock(struct pci_dev *dev)
5160 pci_cfg_access_unlock(dev);
5161 device_unlock(&dev->dev);
5163 EXPORT_SYMBOL_GPL(pci_dev_unlock);
5165 static void pci_dev_save_and_disable(struct pci_dev *dev)
5167 const struct pci_error_handlers *err_handler =
5168 dev->driver ? dev->driver->err_handler : NULL;
5171 * dev->driver->err_handler->reset_prepare() is protected against
5172 * races with ->remove() by the device lock, which must be held by
5175 if (err_handler && err_handler->reset_prepare)
5176 err_handler->reset_prepare(dev);
5179 * Wake-up device prior to save. PM registers default to D0 after
5180 * reset and a simple register restore doesn't reliably return
5181 * to a non-D0 state anyway.
5183 pci_set_power_state(dev, PCI_D0);
5185 pci_save_state(dev);
5187 * Disable the device by clearing the Command register, except for
5188 * INTx-disable which is set. This not only disables MMIO and I/O port
5189 * BARs, but also prevents the device from being Bus Master, preventing
5190 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
5191 * compliant devices, INTx-disable prevents legacy interrupts.
5193 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
5196 static void pci_dev_restore(struct pci_dev *dev)
5198 const struct pci_error_handlers *err_handler =
5199 dev->driver ? dev->driver->err_handler : NULL;
5201 pci_restore_state(dev);
5204 * dev->driver->err_handler->reset_done() is protected against
5205 * races with ->remove() by the device lock, which must be held by
5208 if (err_handler && err_handler->reset_done)
5209 err_handler->reset_done(dev);
5212 /* dev->reset_methods[] is a 0-terminated list of indices into this array */
5213 static const struct pci_reset_fn_method pci_reset_fn_methods[] = {
5215 { pci_dev_specific_reset, .name = "device_specific" },
5216 { pci_dev_acpi_reset, .name = "acpi" },
5217 { pcie_reset_flr, .name = "flr" },
5218 { pci_af_flr, .name = "af_flr" },
5219 { pci_pm_reset, .name = "pm" },
5220 { pci_reset_bus_function, .name = "bus" },
5223 static ssize_t reset_method_show(struct device *dev,
5224 struct device_attribute *attr, char *buf)
5226 struct pci_dev *pdev = to_pci_dev(dev);
5230 for (i = 0; i < PCI_NUM_RESET_METHODS; i++) {
5231 m = pdev->reset_methods[i];
5235 len += sysfs_emit_at(buf, len, "%s%s", len ? " " : "",
5236 pci_reset_fn_methods[m].name);
5240 len += sysfs_emit_at(buf, len, "\n");
5245 static int reset_method_lookup(const char *name)
5249 for (m = 1; m < PCI_NUM_RESET_METHODS; m++) {
5250 if (sysfs_streq(name, pci_reset_fn_methods[m].name))
5254 return 0; /* not found */
5257 static ssize_t reset_method_store(struct device *dev,
5258 struct device_attribute *attr,
5259 const char *buf, size_t count)
5261 struct pci_dev *pdev = to_pci_dev(dev);
5262 char *options, *name;
5264 u8 reset_methods[PCI_NUM_RESET_METHODS] = { 0 };
5266 if (sysfs_streq(buf, "")) {
5267 pdev->reset_methods[0] = 0;
5268 pci_warn(pdev, "All device reset methods disabled by user");
5272 if (sysfs_streq(buf, "default")) {
5273 pci_init_reset_methods(pdev);
5277 options = kstrndup(buf, count, GFP_KERNEL);
5282 while ((name = strsep(&options, " ")) != NULL) {
5283 if (sysfs_streq(name, ""))
5288 m = reset_method_lookup(name);
5290 pci_err(pdev, "Invalid reset method '%s'", name);
5294 if (pci_reset_fn_methods[m].reset_fn(pdev, PCI_RESET_PROBE)) {
5295 pci_err(pdev, "Unsupported reset method '%s'", name);
5299 if (n == PCI_NUM_RESET_METHODS - 1) {
5300 pci_err(pdev, "Too many reset methods\n");
5304 reset_methods[n++] = m;
5307 reset_methods[n] = 0;
5309 /* Warn if dev-specific supported but not highest priority */
5310 if (pci_reset_fn_methods[1].reset_fn(pdev, PCI_RESET_PROBE) == 0 &&
5311 reset_methods[0] != 1)
5312 pci_warn(pdev, "Device-specific reset disabled/de-prioritized by user");
5313 memcpy(pdev->reset_methods, reset_methods, sizeof(pdev->reset_methods));
5318 /* Leave previous methods unchanged */
5322 static DEVICE_ATTR_RW(reset_method);
5324 static struct attribute *pci_dev_reset_method_attrs[] = {
5325 &dev_attr_reset_method.attr,
5329 static umode_t pci_dev_reset_method_attr_is_visible(struct kobject *kobj,
5330 struct attribute *a, int n)
5332 struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
5334 if (!pci_reset_supported(pdev))
5340 const struct attribute_group pci_dev_reset_method_attr_group = {
5341 .attrs = pci_dev_reset_method_attrs,
5342 .is_visible = pci_dev_reset_method_attr_is_visible,
5346 * __pci_reset_function_locked - reset a PCI device function while holding
5347 * the @dev mutex lock.
5348 * @dev: PCI device to reset
5350 * Some devices allow an individual function to be reset without affecting
5351 * other functions in the same device. The PCI device must be responsive
5352 * to PCI config space in order to use this function.
5354 * The device function is presumed to be unused and the caller is holding
5355 * the device mutex lock when this function is called.
5357 * Resetting the device will make the contents of PCI configuration space
5358 * random, so any caller of this must be prepared to reinitialise the
5359 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
5362 * Returns 0 if the device function was successfully reset or negative if the
5363 * device doesn't support resetting a single function.
5365 int __pci_reset_function_locked(struct pci_dev *dev)
5372 * A reset method returns -ENOTTY if it doesn't support this device and
5373 * we should try the next method.
5375 * If it returns 0 (success), we're finished. If it returns any other
5376 * error, we're also finished: this indicates that further reset
5377 * mechanisms might be broken on the device.
5379 for (i = 0; i < PCI_NUM_RESET_METHODS; i++) {
5380 m = dev->reset_methods[i];
5384 rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_DO_RESET);
5393 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
5396 * pci_init_reset_methods - check whether device can be safely reset
5397 * and store supported reset mechanisms.
5398 * @dev: PCI device to check for reset mechanisms
5400 * Some devices allow an individual function to be reset without affecting
5401 * other functions in the same device. The PCI device must be in D0-D3hot
5404 * Stores reset mechanisms supported by device in reset_methods byte array
5405 * which is a member of struct pci_dev.
5407 void pci_init_reset_methods(struct pci_dev *dev)
5411 BUILD_BUG_ON(ARRAY_SIZE(pci_reset_fn_methods) != PCI_NUM_RESET_METHODS);
5416 for (m = 1; m < PCI_NUM_RESET_METHODS; m++) {
5417 rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_PROBE);
5419 dev->reset_methods[i++] = m;
5420 else if (rc != -ENOTTY)
5424 dev->reset_methods[i] = 0;
5428 * pci_reset_function - quiesce and reset a PCI device function
5429 * @dev: PCI device to reset
5431 * Some devices allow an individual function to be reset without affecting
5432 * other functions in the same device. The PCI device must be responsive
5433 * to PCI config space in order to use this function.
5435 * This function does not just reset the PCI portion of a device, but
5436 * clears all the state associated with the device. This function differs
5437 * from __pci_reset_function_locked() in that it saves and restores device state
5438 * over the reset and takes the PCI device lock.
5440 * Returns 0 if the device function was successfully reset or negative if the
5441 * device doesn't support resetting a single function.
5443 int pci_reset_function(struct pci_dev *dev)
5447 if (!pci_reset_supported(dev))
5451 pci_dev_save_and_disable(dev);
5453 rc = __pci_reset_function_locked(dev);
5455 pci_dev_restore(dev);
5456 pci_dev_unlock(dev);
5460 EXPORT_SYMBOL_GPL(pci_reset_function);
5463 * pci_reset_function_locked - quiesce and reset a PCI device function
5464 * @dev: PCI device to reset
5466 * Some devices allow an individual function to be reset without affecting
5467 * other functions in the same device. The PCI device must be responsive
5468 * to PCI config space in order to use this function.
5470 * This function does not just reset the PCI portion of a device, but
5471 * clears all the state associated with the device. This function differs
5472 * from __pci_reset_function_locked() in that it saves and restores device state
5473 * over the reset. It also differs from pci_reset_function() in that it
5474 * requires the PCI device lock to be held.
5476 * Returns 0 if the device function was successfully reset or negative if the
5477 * device doesn't support resetting a single function.
5479 int pci_reset_function_locked(struct pci_dev *dev)
5483 if (!pci_reset_supported(dev))
5486 pci_dev_save_and_disable(dev);
5488 rc = __pci_reset_function_locked(dev);
5490 pci_dev_restore(dev);
5494 EXPORT_SYMBOL_GPL(pci_reset_function_locked);
5497 * pci_try_reset_function - quiesce and reset a PCI device function
5498 * @dev: PCI device to reset
5500 * Same as above, except return -EAGAIN if unable to lock device.
5502 int pci_try_reset_function(struct pci_dev *dev)
5506 if (!pci_reset_supported(dev))
5509 if (!pci_dev_trylock(dev))
5512 pci_dev_save_and_disable(dev);
5513 rc = __pci_reset_function_locked(dev);
5514 pci_dev_restore(dev);
5515 pci_dev_unlock(dev);
5519 EXPORT_SYMBOL_GPL(pci_try_reset_function);
5521 /* Do any devices on or below this bus prevent a bus reset? */
5522 static bool pci_bus_resetable(struct pci_bus *bus)
5524 struct pci_dev *dev;
5527 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5530 list_for_each_entry(dev, &bus->devices, bus_list) {
5531 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5532 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5539 /* Lock devices from the top of the tree down */
5540 static void pci_bus_lock(struct pci_bus *bus)
5542 struct pci_dev *dev;
5544 list_for_each_entry(dev, &bus->devices, bus_list) {
5546 if (dev->subordinate)
5547 pci_bus_lock(dev->subordinate);
5551 /* Unlock devices from the bottom of the tree up */
5552 static void pci_bus_unlock(struct pci_bus *bus)
5554 struct pci_dev *dev;
5556 list_for_each_entry(dev, &bus->devices, bus_list) {
5557 if (dev->subordinate)
5558 pci_bus_unlock(dev->subordinate);
5559 pci_dev_unlock(dev);
5563 /* Return 1 on successful lock, 0 on contention */
5564 static int pci_bus_trylock(struct pci_bus *bus)
5566 struct pci_dev *dev;
5568 list_for_each_entry(dev, &bus->devices, bus_list) {
5569 if (!pci_dev_trylock(dev))
5571 if (dev->subordinate) {
5572 if (!pci_bus_trylock(dev->subordinate)) {
5573 pci_dev_unlock(dev);
5581 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
5582 if (dev->subordinate)
5583 pci_bus_unlock(dev->subordinate);
5584 pci_dev_unlock(dev);
5589 /* Do any devices on or below this slot prevent a bus reset? */
5590 static bool pci_slot_resetable(struct pci_slot *slot)
5592 struct pci_dev *dev;
5594 if (slot->bus->self &&
5595 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5598 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5599 if (!dev->slot || dev->slot != slot)
5601 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5602 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5609 /* Lock devices from the top of the tree down */
5610 static void pci_slot_lock(struct pci_slot *slot)
5612 struct pci_dev *dev;
5614 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5615 if (!dev->slot || dev->slot != slot)
5618 if (dev->subordinate)
5619 pci_bus_lock(dev->subordinate);
5623 /* Unlock devices from the bottom of the tree up */
5624 static void pci_slot_unlock(struct pci_slot *slot)
5626 struct pci_dev *dev;
5628 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5629 if (!dev->slot || dev->slot != slot)
5631 if (dev->subordinate)
5632 pci_bus_unlock(dev->subordinate);
5633 pci_dev_unlock(dev);
5637 /* Return 1 on successful lock, 0 on contention */
5638 static int pci_slot_trylock(struct pci_slot *slot)
5640 struct pci_dev *dev;
5642 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5643 if (!dev->slot || dev->slot != slot)
5645 if (!pci_dev_trylock(dev))
5647 if (dev->subordinate) {
5648 if (!pci_bus_trylock(dev->subordinate)) {
5649 pci_dev_unlock(dev);
5657 list_for_each_entry_continue_reverse(dev,
5658 &slot->bus->devices, bus_list) {
5659 if (!dev->slot || dev->slot != slot)
5661 if (dev->subordinate)
5662 pci_bus_unlock(dev->subordinate);
5663 pci_dev_unlock(dev);
5669 * Save and disable devices from the top of the tree down while holding
5670 * the @dev mutex lock for the entire tree.
5672 static void pci_bus_save_and_disable_locked(struct pci_bus *bus)
5674 struct pci_dev *dev;
5676 list_for_each_entry(dev, &bus->devices, bus_list) {
5677 pci_dev_save_and_disable(dev);
5678 if (dev->subordinate)
5679 pci_bus_save_and_disable_locked(dev->subordinate);
5684 * Restore devices from top of the tree down while holding @dev mutex lock
5685 * for the entire tree. Parent bridges need to be restored before we can
5686 * get to subordinate devices.
5688 static void pci_bus_restore_locked(struct pci_bus *bus)
5690 struct pci_dev *dev;
5692 list_for_each_entry(dev, &bus->devices, bus_list) {
5693 pci_dev_restore(dev);
5694 if (dev->subordinate)
5695 pci_bus_restore_locked(dev->subordinate);
5700 * Save and disable devices from the top of the tree down while holding
5701 * the @dev mutex lock for the entire tree.
5703 static void pci_slot_save_and_disable_locked(struct pci_slot *slot)
5705 struct pci_dev *dev;
5707 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5708 if (!dev->slot || dev->slot != slot)
5710 pci_dev_save_and_disable(dev);
5711 if (dev->subordinate)
5712 pci_bus_save_and_disable_locked(dev->subordinate);
5717 * Restore devices from top of the tree down while holding @dev mutex lock
5718 * for the entire tree. Parent bridges need to be restored before we can
5719 * get to subordinate devices.
5721 static void pci_slot_restore_locked(struct pci_slot *slot)
5723 struct pci_dev *dev;
5725 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5726 if (!dev->slot || dev->slot != slot)
5728 pci_dev_restore(dev);
5729 if (dev->subordinate)
5730 pci_bus_restore_locked(dev->subordinate);
5734 static int pci_slot_reset(struct pci_slot *slot, bool probe)
5738 if (!slot || !pci_slot_resetable(slot))
5742 pci_slot_lock(slot);
5746 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
5749 pci_slot_unlock(slot);
5755 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5756 * @slot: PCI slot to probe
5758 * Return 0 if slot can be reset, negative if a slot reset is not supported.
5760 int pci_probe_reset_slot(struct pci_slot *slot)
5762 return pci_slot_reset(slot, PCI_RESET_PROBE);
5764 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
5767 * __pci_reset_slot - Try to reset a PCI slot
5768 * @slot: PCI slot to reset
5770 * A PCI bus may host multiple slots, each slot may support a reset mechanism
5771 * independent of other slots. For instance, some slots may support slot power
5772 * control. In the case of a 1:1 bus to slot architecture, this function may
5773 * wrap the bus reset to avoid spurious slot related events such as hotplug.
5774 * Generally a slot reset should be attempted before a bus reset. All of the
5775 * function of the slot and any subordinate buses behind the slot are reset
5776 * through this function. PCI config space of all devices in the slot and
5777 * behind the slot is saved before and restored after reset.
5779 * Same as above except return -EAGAIN if the slot cannot be locked
5781 static int __pci_reset_slot(struct pci_slot *slot)
5785 rc = pci_slot_reset(slot, PCI_RESET_PROBE);
5789 if (pci_slot_trylock(slot)) {
5790 pci_slot_save_and_disable_locked(slot);
5792 rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET);
5793 pci_slot_restore_locked(slot);
5794 pci_slot_unlock(slot);
5801 static int pci_bus_reset(struct pci_bus *bus, bool probe)
5805 if (!bus->self || !pci_bus_resetable(bus))
5815 ret = pci_bridge_secondary_bus_reset(bus->self);
5817 pci_bus_unlock(bus);
5823 * pci_bus_error_reset - reset the bridge's subordinate bus
5824 * @bridge: The parent device that connects to the bus to reset
5826 * This function will first try to reset the slots on this bus if the method is
5827 * available. If slot reset fails or is not available, this will fall back to a
5828 * secondary bus reset.
5830 int pci_bus_error_reset(struct pci_dev *bridge)
5832 struct pci_bus *bus = bridge->subordinate;
5833 struct pci_slot *slot;
5838 mutex_lock(&pci_slot_mutex);
5839 if (list_empty(&bus->slots))
5842 list_for_each_entry(slot, &bus->slots, list)
5843 if (pci_probe_reset_slot(slot))
5846 list_for_each_entry(slot, &bus->slots, list)
5847 if (pci_slot_reset(slot, PCI_RESET_DO_RESET))
5850 mutex_unlock(&pci_slot_mutex);
5853 mutex_unlock(&pci_slot_mutex);
5854 return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET);
5858 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5859 * @bus: PCI bus to probe
5861 * Return 0 if bus can be reset, negative if a bus reset is not supported.
5863 int pci_probe_reset_bus(struct pci_bus *bus)
5865 return pci_bus_reset(bus, PCI_RESET_PROBE);
5867 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
5870 * __pci_reset_bus - Try to reset a PCI bus
5871 * @bus: top level PCI bus to reset
5873 * Same as above except return -EAGAIN if the bus cannot be locked
5875 static int __pci_reset_bus(struct pci_bus *bus)
5879 rc = pci_bus_reset(bus, PCI_RESET_PROBE);
5883 if (pci_bus_trylock(bus)) {
5884 pci_bus_save_and_disable_locked(bus);
5886 rc = pci_bridge_secondary_bus_reset(bus->self);
5887 pci_bus_restore_locked(bus);
5888 pci_bus_unlock(bus);
5896 * pci_reset_bus - Try to reset a PCI bus
5897 * @pdev: top level PCI device to reset via slot/bus
5899 * Same as above except return -EAGAIN if the bus cannot be locked
5901 int pci_reset_bus(struct pci_dev *pdev)
5903 return (!pci_probe_reset_slot(pdev->slot)) ?
5904 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);
5906 EXPORT_SYMBOL_GPL(pci_reset_bus);
5909 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5910 * @dev: PCI device to query
5912 * Returns mmrbc: maximum designed memory read count in bytes or
5913 * appropriate error value.
5915 int pcix_get_max_mmrbc(struct pci_dev *dev)
5920 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5924 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5927 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
5929 EXPORT_SYMBOL(pcix_get_max_mmrbc);
5932 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5933 * @dev: PCI device to query
5935 * Returns mmrbc: maximum memory read count in bytes or appropriate error
5938 int pcix_get_mmrbc(struct pci_dev *dev)
5943 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5947 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5950 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
5952 EXPORT_SYMBOL(pcix_get_mmrbc);
5955 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5956 * @dev: PCI device to query
5957 * @mmrbc: maximum memory read count in bytes
5958 * valid values are 512, 1024, 2048, 4096
5960 * If possible sets maximum memory read byte count, some bridges have errata
5961 * that prevent this.
5963 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
5969 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
5972 v = ffs(mmrbc) - 10;
5974 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5978 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5981 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
5984 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5987 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
5989 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
5992 cmd &= ~PCI_X_CMD_MAX_READ;
5994 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
5999 EXPORT_SYMBOL(pcix_set_mmrbc);
6002 * pcie_get_readrq - get PCI Express read request size
6003 * @dev: PCI device to query
6005 * Returns maximum memory read request in bytes or appropriate error value.
6007 int pcie_get_readrq(struct pci_dev *dev)
6011 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
6013 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6015 EXPORT_SYMBOL(pcie_get_readrq);
6018 * pcie_set_readrq - set PCI Express maximum memory read request
6019 * @dev: PCI device to query
6020 * @rq: maximum memory read count in bytes
6021 * valid values are 128, 256, 512, 1024, 2048, 4096
6023 * If possible sets maximum memory read request in bytes
6025 int pcie_set_readrq(struct pci_dev *dev, int rq)
6029 struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus);
6031 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
6035 * If using the "performance" PCIe config, we clamp the read rq
6036 * size to the max packet size to keep the host bridge from
6037 * generating requests larger than we can cope with.
6039 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
6040 int mps = pcie_get_mps(dev);
6046 v = (ffs(rq) - 8) << 12;
6048 if (bridge->no_inc_mrrs) {
6049 int max_mrrs = pcie_get_readrq(dev);
6051 if (rq > max_mrrs) {
6052 pci_info(dev, "can't set Max_Read_Request_Size to %d; max is %d\n", rq, max_mrrs);
6057 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
6058 PCI_EXP_DEVCTL_READRQ, v);
6060 return pcibios_err_to_errno(ret);
6062 EXPORT_SYMBOL(pcie_set_readrq);
6065 * pcie_get_mps - get PCI Express maximum payload size
6066 * @dev: PCI device to query
6068 * Returns maximum payload size in bytes
6070 int pcie_get_mps(struct pci_dev *dev)
6074 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
6076 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6078 EXPORT_SYMBOL(pcie_get_mps);
6081 * pcie_set_mps - set PCI Express maximum payload size
6082 * @dev: PCI device to query
6083 * @mps: maximum payload size in bytes
6084 * valid values are 128, 256, 512, 1024, 2048, 4096
6086 * If possible sets maximum payload size
6088 int pcie_set_mps(struct pci_dev *dev, int mps)
6093 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
6097 if (v > dev->pcie_mpss)
6101 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
6102 PCI_EXP_DEVCTL_PAYLOAD, v);
6104 return pcibios_err_to_errno(ret);
6106 EXPORT_SYMBOL(pcie_set_mps);
6109 * pcie_bandwidth_available - determine minimum link settings of a PCIe
6110 * device and its bandwidth limitation
6111 * @dev: PCI device to query
6112 * @limiting_dev: storage for device causing the bandwidth limitation
6113 * @speed: storage for speed of limiting device
6114 * @width: storage for width of limiting device
6116 * Walk up the PCI device chain and find the point where the minimum
6117 * bandwidth is available. Return the bandwidth available there and (if
6118 * limiting_dev, speed, and width pointers are supplied) information about
6119 * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
6122 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
6123 enum pci_bus_speed *speed,
6124 enum pcie_link_width *width)
6127 enum pci_bus_speed next_speed;
6128 enum pcie_link_width next_width;
6132 *speed = PCI_SPEED_UNKNOWN;
6134 *width = PCIE_LNK_WIDTH_UNKNOWN;
6139 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
6141 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
6142 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
6143 PCI_EXP_LNKSTA_NLW_SHIFT;
6145 next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
6147 /* Check if current device limits the total bandwidth */
6148 if (!bw || next_bw <= bw) {
6152 *limiting_dev = dev;
6154 *speed = next_speed;
6156 *width = next_width;
6159 dev = pci_upstream_bridge(dev);
6164 EXPORT_SYMBOL(pcie_bandwidth_available);
6167 * pcie_get_speed_cap - query for the PCI device's link speed capability
6168 * @dev: PCI device to query
6170 * Query the PCI device speed capability. Return the maximum link speed
6171 * supported by the device.
6173 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
6175 u32 lnkcap2, lnkcap;
6178 * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The
6179 * implementation note there recommends using the Supported Link
6180 * Speeds Vector in Link Capabilities 2 when supported.
6182 * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
6183 * should use the Supported Link Speeds field in Link Capabilities,
6184 * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
6186 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
6188 /* PCIe r3.0-compliant */
6190 return PCIE_LNKCAP2_SLS2SPEED(lnkcap2);
6192 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6193 if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
6194 return PCIE_SPEED_5_0GT;
6195 else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)
6196 return PCIE_SPEED_2_5GT;
6198 return PCI_SPEED_UNKNOWN;
6200 EXPORT_SYMBOL(pcie_get_speed_cap);
6203 * pcie_get_width_cap - query for the PCI device's link width capability
6204 * @dev: PCI device to query
6206 * Query the PCI device width capability. Return the maximum link width
6207 * supported by the device.
6209 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
6213 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6215 return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
6217 return PCIE_LNK_WIDTH_UNKNOWN;
6219 EXPORT_SYMBOL(pcie_get_width_cap);
6222 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
6224 * @speed: storage for link speed
6225 * @width: storage for link width
6227 * Calculate a PCI device's link bandwidth by querying for its link speed
6228 * and width, multiplying them, and applying encoding overhead. The result
6229 * is in Mb/s, i.e., megabits/second of raw bandwidth.
6231 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
6232 enum pcie_link_width *width)
6234 *speed = pcie_get_speed_cap(dev);
6235 *width = pcie_get_width_cap(dev);
6237 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
6240 return *width * PCIE_SPEED2MBS_ENC(*speed);
6244 * __pcie_print_link_status - Report the PCI device's link speed and width
6245 * @dev: PCI device to query
6246 * @verbose: Print info even when enough bandwidth is available
6248 * If the available bandwidth at the device is less than the device is
6249 * capable of, report the device's maximum possible bandwidth and the
6250 * upstream link that limits its performance. If @verbose, always print
6251 * the available bandwidth, even if the device isn't constrained.
6253 void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
6255 enum pcie_link_width width, width_cap;
6256 enum pci_bus_speed speed, speed_cap;
6257 struct pci_dev *limiting_dev = NULL;
6258 u32 bw_avail, bw_cap;
6260 bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
6261 bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
6263 if (bw_avail >= bw_cap && verbose)
6264 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
6265 bw_cap / 1000, bw_cap % 1000,
6266 pci_speed_string(speed_cap), width_cap);
6267 else if (bw_avail < bw_cap)
6268 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
6269 bw_avail / 1000, bw_avail % 1000,
6270 pci_speed_string(speed), width,
6271 limiting_dev ? pci_name(limiting_dev) : "<unknown>",
6272 bw_cap / 1000, bw_cap % 1000,
6273 pci_speed_string(speed_cap), width_cap);
6277 * pcie_print_link_status - Report the PCI device's link speed and width
6278 * @dev: PCI device to query
6280 * Report the available bandwidth at the device.
6282 void pcie_print_link_status(struct pci_dev *dev)
6284 __pcie_print_link_status(dev, true);
6286 EXPORT_SYMBOL(pcie_print_link_status);
6289 * pci_select_bars - Make BAR mask from the type of resource
6290 * @dev: the PCI device for which BAR mask is made
6291 * @flags: resource type mask to be selected
6293 * This helper routine makes bar mask from the type of resource.
6295 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
6298 for (i = 0; i < PCI_NUM_RESOURCES; i++)
6299 if (pci_resource_flags(dev, i) & flags)
6303 EXPORT_SYMBOL(pci_select_bars);
6305 /* Some architectures require additional programming to enable VGA */
6306 static arch_set_vga_state_t arch_set_vga_state;
6308 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
6310 arch_set_vga_state = func; /* NULL disables */
6313 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
6314 unsigned int command_bits, u32 flags)
6316 if (arch_set_vga_state)
6317 return arch_set_vga_state(dev, decode, command_bits,
6323 * pci_set_vga_state - set VGA decode state on device and parents if requested
6324 * @dev: the PCI device
6325 * @decode: true = enable decoding, false = disable decoding
6326 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
6327 * @flags: traverse ancestors and change bridges
6328 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
6330 int pci_set_vga_state(struct pci_dev *dev, bool decode,
6331 unsigned int command_bits, u32 flags)
6333 struct pci_bus *bus;
6334 struct pci_dev *bridge;
6338 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
6340 /* ARCH specific VGA enables */
6341 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
6345 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
6346 pci_read_config_word(dev, PCI_COMMAND, &cmd);
6348 cmd |= command_bits;
6350 cmd &= ~command_bits;
6351 pci_write_config_word(dev, PCI_COMMAND, cmd);
6354 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
6361 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
6364 cmd |= PCI_BRIDGE_CTL_VGA;
6366 cmd &= ~PCI_BRIDGE_CTL_VGA;
6367 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
6376 bool pci_pr3_present(struct pci_dev *pdev)
6378 struct acpi_device *adev;
6383 adev = ACPI_COMPANION(&pdev->dev);
6387 return adev->power.flags.power_resources &&
6388 acpi_has_method(adev->handle, "_PR3");
6390 EXPORT_SYMBOL_GPL(pci_pr3_present);
6394 * pci_add_dma_alias - Add a DMA devfn alias for a device
6395 * @dev: the PCI device for which alias is added
6396 * @devfn_from: alias slot and function
6397 * @nr_devfns: number of subsequent devfns to alias
6399 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6400 * which is used to program permissible bus-devfn source addresses for DMA
6401 * requests in an IOMMU. These aliases factor into IOMMU group creation
6402 * and are useful for devices generating DMA requests beyond or different
6403 * from their logical bus-devfn. Examples include device quirks where the
6404 * device simply uses the wrong devfn, as well as non-transparent bridges
6405 * where the alias may be a proxy for devices in another domain.
6407 * IOMMU group creation is performed during device discovery or addition,
6408 * prior to any potential DMA mapping and therefore prior to driver probing
6409 * (especially for userspace assigned devices where IOMMU group definition
6410 * cannot be left as a userspace activity). DMA aliases should therefore
6411 * be configured via quirks, such as the PCI fixup header quirk.
6413 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from,
6414 unsigned int nr_devfns)
6418 nr_devfns = min(nr_devfns, (unsigned int)MAX_NR_DEVFNS - devfn_from);
6419 devfn_to = devfn_from + nr_devfns - 1;
6421 if (!dev->dma_alias_mask)
6422 dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL);
6423 if (!dev->dma_alias_mask) {
6424 pci_warn(dev, "Unable to allocate DMA alias mask\n");
6428 bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns);
6431 pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
6432 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from));
6433 else if (nr_devfns > 1)
6434 pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",
6435 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from),
6436 PCI_SLOT(devfn_to), PCI_FUNC(devfn_to));
6439 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
6441 return (dev1->dma_alias_mask &&
6442 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
6443 (dev2->dma_alias_mask &&
6444 test_bit(dev1->devfn, dev2->dma_alias_mask)) ||
6445 pci_real_dma_dev(dev1) == dev2 ||
6446 pci_real_dma_dev(dev2) == dev1;
6449 bool pci_device_is_present(struct pci_dev *pdev)
6453 /* Check PF if pdev is a VF, since VF Vendor/Device IDs are 0xffff */
6454 pdev = pci_physfn(pdev);
6455 if (pci_dev_is_disconnected(pdev))
6457 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
6459 EXPORT_SYMBOL_GPL(pci_device_is_present);
6461 void pci_ignore_hotplug(struct pci_dev *dev)
6463 struct pci_dev *bridge = dev->bus->self;
6465 dev->ignore_hotplug = 1;
6466 /* Propagate the "ignore hotplug" setting to the parent bridge. */
6468 bridge->ignore_hotplug = 1;
6470 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
6473 * pci_real_dma_dev - Get PCI DMA device for PCI device
6474 * @dev: the PCI device that may have a PCI DMA alias
6476 * Permits the platform to provide architecture-specific functionality to
6477 * devices needing to alias DMA to another PCI device on another PCI bus. If
6478 * the PCI device is on the same bus, it is recommended to use
6479 * pci_add_dma_alias(). This is the default implementation. Architecture
6480 * implementations can override this.
6482 struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev)
6487 resource_size_t __weak pcibios_default_alignment(void)
6493 * Arches that don't want to expose struct resource to userland as-is in
6494 * sysfs and /proc can implement their own pci_resource_to_user().
6496 void __weak pci_resource_to_user(const struct pci_dev *dev, int bar,
6497 const struct resource *rsrc,
6498 resource_size_t *start, resource_size_t *end)
6500 *start = rsrc->start;
6504 static char *resource_alignment_param;
6505 static DEFINE_SPINLOCK(resource_alignment_lock);
6508 * pci_specified_resource_alignment - get resource alignment specified by user.
6509 * @dev: the PCI device to get
6510 * @resize: whether or not to change resources' size when reassigning alignment
6512 * RETURNS: Resource alignment if it is specified.
6513 * Zero if it is not specified.
6515 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
6518 int align_order, count;
6519 resource_size_t align = pcibios_default_alignment();
6523 spin_lock(&resource_alignment_lock);
6524 p = resource_alignment_param;
6527 if (pci_has_flag(PCI_PROBE_ONLY)) {
6529 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
6535 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
6538 if (align_order > 63) {
6539 pr_err("PCI: Invalid requested alignment (order %d)\n",
6541 align_order = PAGE_SHIFT;
6544 align_order = PAGE_SHIFT;
6547 ret = pci_dev_str_match(dev, p, &p);
6550 align = 1ULL << align_order;
6552 } else if (ret < 0) {
6553 pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
6558 if (*p != ';' && *p != ',') {
6559 /* End of param or invalid format */
6565 spin_unlock(&resource_alignment_lock);
6569 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
6570 resource_size_t align, bool resize)
6572 struct resource *r = &dev->resource[bar];
6573 resource_size_t size;
6575 if (!(r->flags & IORESOURCE_MEM))
6578 if (r->flags & IORESOURCE_PCI_FIXED) {
6579 pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
6580 bar, r, (unsigned long long)align);
6584 size = resource_size(r);
6589 * Increase the alignment of the resource. There are two ways we
6592 * 1) Increase the size of the resource. BARs are aligned on their
6593 * size, so when we reallocate space for this resource, we'll
6594 * allocate it with the larger alignment. This also prevents
6595 * assignment of any other BARs inside the alignment region, so
6596 * if we're requesting page alignment, this means no other BARs
6597 * will share the page.
6599 * The disadvantage is that this makes the resource larger than
6600 * the hardware BAR, which may break drivers that compute things
6601 * based on the resource size, e.g., to find registers at a
6602 * fixed offset before the end of the BAR.
6604 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
6605 * set r->start to the desired alignment. By itself this
6606 * doesn't prevent other BARs being put inside the alignment
6607 * region, but if we realign *every* resource of every device in
6608 * the system, none of them will share an alignment region.
6610 * When the user has requested alignment for only some devices via
6611 * the "pci=resource_alignment" argument, "resize" is true and we
6612 * use the first method. Otherwise we assume we're aligning all
6613 * devices and we use the second.
6616 pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
6617 bar, r, (unsigned long long)align);
6623 r->flags &= ~IORESOURCE_SIZEALIGN;
6624 r->flags |= IORESOURCE_STARTALIGN;
6626 r->end = r->start + size - 1;
6628 r->flags |= IORESOURCE_UNSET;
6632 * This function disables memory decoding and releases memory resources
6633 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
6634 * It also rounds up size to specified alignment.
6635 * Later on, the kernel will assign page-aligned memory resource back
6638 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
6642 resource_size_t align;
6644 bool resize = false;
6647 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
6648 * 3.4.1.11. Their resources are allocated from the space
6649 * described by the VF BARx register in the PF's SR-IOV capability.
6650 * We can't influence their alignment here.
6655 /* check if specified PCI is target device to reassign */
6656 align = pci_specified_resource_alignment(dev, &resize);
6660 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
6661 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
6662 pci_warn(dev, "Can't reassign resources to host bridge\n");
6666 pci_read_config_word(dev, PCI_COMMAND, &command);
6667 command &= ~PCI_COMMAND_MEMORY;
6668 pci_write_config_word(dev, PCI_COMMAND, command);
6670 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
6671 pci_request_resource_alignment(dev, i, align, resize);
6674 * Need to disable bridge's resource window,
6675 * to enable the kernel to reassign new resource
6678 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
6679 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
6680 r = &dev->resource[i];
6681 if (!(r->flags & IORESOURCE_MEM))
6683 r->flags |= IORESOURCE_UNSET;
6684 r->end = resource_size(r) - 1;
6687 pci_disable_bridge_window(dev);
6691 static ssize_t resource_alignment_show(struct bus_type *bus, char *buf)
6695 spin_lock(&resource_alignment_lock);
6696 if (resource_alignment_param)
6697 count = sysfs_emit(buf, "%s\n", resource_alignment_param);
6698 spin_unlock(&resource_alignment_lock);
6703 static ssize_t resource_alignment_store(struct bus_type *bus,
6704 const char *buf, size_t count)
6706 char *param, *old, *end;
6708 if (count >= (PAGE_SIZE - 1))
6711 param = kstrndup(buf, count, GFP_KERNEL);
6715 end = strchr(param, '\n');
6719 spin_lock(&resource_alignment_lock);
6720 old = resource_alignment_param;
6721 if (strlen(param)) {
6722 resource_alignment_param = param;
6725 resource_alignment_param = NULL;
6727 spin_unlock(&resource_alignment_lock);
6734 static BUS_ATTR_RW(resource_alignment);
6736 static int __init pci_resource_alignment_sysfs_init(void)
6738 return bus_create_file(&pci_bus_type,
6739 &bus_attr_resource_alignment);
6741 late_initcall(pci_resource_alignment_sysfs_init);
6743 static void pci_no_domains(void)
6745 #ifdef CONFIG_PCI_DOMAINS
6746 pci_domains_supported = 0;
6750 #ifdef CONFIG_PCI_DOMAINS_GENERIC
6751 static DEFINE_IDA(pci_domain_nr_static_ida);
6752 static DEFINE_IDA(pci_domain_nr_dynamic_ida);
6754 static void of_pci_reserve_static_domain_nr(void)
6756 struct device_node *np;
6759 for_each_node_by_type(np, "pci") {
6760 domain_nr = of_get_pci_domain_nr(np);
6764 * Permanently allocate domain_nr in dynamic_ida
6765 * to prevent it from dynamic allocation.
6767 ida_alloc_range(&pci_domain_nr_dynamic_ida,
6768 domain_nr, domain_nr, GFP_KERNEL);
6772 static int of_pci_bus_find_domain_nr(struct device *parent)
6774 static bool static_domains_reserved = false;
6777 /* On the first call scan device tree for static allocations. */
6778 if (!static_domains_reserved) {
6779 of_pci_reserve_static_domain_nr();
6780 static_domains_reserved = true;
6785 * If domain is in DT, allocate it in static IDA. This
6786 * prevents duplicate static allocations in case of errors
6789 domain_nr = of_get_pci_domain_nr(parent->of_node);
6791 return ida_alloc_range(&pci_domain_nr_static_ida,
6792 domain_nr, domain_nr,
6797 * If domain was not specified in DT, choose a free ID from dynamic
6798 * allocations. All domain numbers from DT are permanently in
6799 * dynamic allocations to prevent assigning them to other DT nodes
6800 * without static domain.
6802 return ida_alloc(&pci_domain_nr_dynamic_ida, GFP_KERNEL);
6805 static void of_pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent)
6807 if (bus->domain_nr < 0)
6810 /* Release domain from IDA where it was allocated. */
6811 if (of_get_pci_domain_nr(parent->of_node) == bus->domain_nr)
6812 ida_free(&pci_domain_nr_static_ida, bus->domain_nr);
6814 ida_free(&pci_domain_nr_dynamic_ida, bus->domain_nr);
6817 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
6819 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
6820 acpi_pci_bus_find_domain_nr(bus);
6823 void pci_bus_release_domain_nr(struct pci_bus *bus, struct device *parent)
6827 of_pci_bus_release_domain_nr(bus, parent);
6832 * pci_ext_cfg_avail - can we access extended PCI config space?
6834 * Returns 1 if we can access PCI extended config space (offsets
6835 * greater than 0xff). This is the default implementation. Architecture
6836 * implementations can override this.
6838 int __weak pci_ext_cfg_avail(void)
6843 void __weak pci_fixup_cardbus(struct pci_bus *bus)
6846 EXPORT_SYMBOL(pci_fixup_cardbus);
6848 static int __init pci_setup(char *str)
6851 char *k = strchr(str, ',');
6854 if (*str && (str = pcibios_setup(str)) && *str) {
6855 if (!strcmp(str, "nomsi")) {
6857 } else if (!strncmp(str, "noats", 5)) {
6858 pr_info("PCIe: ATS is disabled\n");
6859 pcie_ats_disabled = true;
6860 } else if (!strcmp(str, "noaer")) {
6862 } else if (!strcmp(str, "earlydump")) {
6863 pci_early_dump = true;
6864 } else if (!strncmp(str, "realloc=", 8)) {
6865 pci_realloc_get_opt(str + 8);
6866 } else if (!strncmp(str, "realloc", 7)) {
6867 pci_realloc_get_opt("on");
6868 } else if (!strcmp(str, "nodomains")) {
6870 } else if (!strncmp(str, "noari", 5)) {
6871 pcie_ari_disabled = true;
6872 } else if (!strncmp(str, "cbiosize=", 9)) {
6873 pci_cardbus_io_size = memparse(str + 9, &str);
6874 } else if (!strncmp(str, "cbmemsize=", 10)) {
6875 pci_cardbus_mem_size = memparse(str + 10, &str);
6876 } else if (!strncmp(str, "resource_alignment=", 19)) {
6877 resource_alignment_param = str + 19;
6878 } else if (!strncmp(str, "ecrc=", 5)) {
6879 pcie_ecrc_get_policy(str + 5);
6880 } else if (!strncmp(str, "hpiosize=", 9)) {
6881 pci_hotplug_io_size = memparse(str + 9, &str);
6882 } else if (!strncmp(str, "hpmmiosize=", 11)) {
6883 pci_hotplug_mmio_size = memparse(str + 11, &str);
6884 } else if (!strncmp(str, "hpmmioprefsize=", 15)) {
6885 pci_hotplug_mmio_pref_size = memparse(str + 15, &str);
6886 } else if (!strncmp(str, "hpmemsize=", 10)) {
6887 pci_hotplug_mmio_size = memparse(str + 10, &str);
6888 pci_hotplug_mmio_pref_size = pci_hotplug_mmio_size;
6889 } else if (!strncmp(str, "hpbussize=", 10)) {
6890 pci_hotplug_bus_size =
6891 simple_strtoul(str + 10, &str, 0);
6892 if (pci_hotplug_bus_size > 0xff)
6893 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
6894 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
6895 pcie_bus_config = PCIE_BUS_TUNE_OFF;
6896 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
6897 pcie_bus_config = PCIE_BUS_SAFE;
6898 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
6899 pcie_bus_config = PCIE_BUS_PERFORMANCE;
6900 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
6901 pcie_bus_config = PCIE_BUS_PEER2PEER;
6902 } else if (!strncmp(str, "pcie_scan_all", 13)) {
6903 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
6904 } else if (!strncmp(str, "disable_acs_redir=", 18)) {
6905 disable_acs_redir_param = str + 18;
6907 pr_err("PCI: Unknown option `%s'\n", str);
6914 early_param("pci", pci_setup);
6917 * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
6918 * in pci_setup(), above, to point to data in the __initdata section which
6919 * will be freed after the init sequence is complete. We can't allocate memory
6920 * in pci_setup() because some architectures do not have any memory allocation
6921 * service available during an early_param() call. So we allocate memory and
6922 * copy the variable here before the init section is freed.
6925 static int __init pci_realloc_setup_params(void)
6927 resource_alignment_param = kstrdup(resource_alignment_param,
6929 disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL);
6933 pure_initcall(pci_realloc_setup_params);