Merge branch 'master' of git://www.denx.de/git/u-boot-imx
[platform/kernel/u-boot.git] / drivers / pci / pci.c
1 /*
2  * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3  * Andreas Heppel <aheppel@sysgo.de>
4  *
5  * (C) Copyright 2002, 2003
6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7  *
8  * SPDX-License-Identifier:     GPL-2.0+
9  */
10
11 /*
12  * PCI routines
13  */
14
15 #include <common.h>
16
17 #include <command.h>
18 #include <asm/processor.h>
19 #include <asm/io.h>
20 #include <pci.h>
21
22 #define PCI_HOSE_OP(rw, size, type)                                     \
23 int pci_hose_##rw##_config_##size(struct pci_controller *hose,          \
24                                   pci_dev_t dev,                        \
25                                   int offset, type value)               \
26 {                                                                       \
27         return hose->rw##_##size(hose, dev, offset, value);             \
28 }
29
30 PCI_HOSE_OP(read, byte, u8 *)
31 PCI_HOSE_OP(read, word, u16 *)
32 PCI_HOSE_OP(read, dword, u32 *)
33 PCI_HOSE_OP(write, byte, u8)
34 PCI_HOSE_OP(write, word, u16)
35 PCI_HOSE_OP(write, dword, u32)
36
37 #define PCI_OP(rw, size, type, error_code)                              \
38 int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value)     \
39 {                                                                       \
40         struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev));    \
41                                                                         \
42         if (!hose)                                                      \
43         {                                                               \
44                 error_code;                                             \
45                 return -1;                                              \
46         }                                                               \
47                                                                         \
48         return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
49 }
50
51 PCI_OP(read, byte, u8 *, *value = 0xff)
52 PCI_OP(read, word, u16 *, *value = 0xffff)
53 PCI_OP(read, dword, u32 *, *value = 0xffffffff)
54 PCI_OP(write, byte, u8, )
55 PCI_OP(write, word, u16, )
56 PCI_OP(write, dword, u32, )
57
58 #define PCI_READ_VIA_DWORD_OP(size, type, off_mask)                     \
59 int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
60                                         pci_dev_t dev,                  \
61                                         int offset, type val)           \
62 {                                                                       \
63         u32 val32;                                                      \
64                                                                         \
65         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
66                 *val = -1;                                              \
67                 return -1;                                              \
68         }                                                               \
69                                                                         \
70         *val = (val32 >> ((offset & (int)off_mask) * 8));               \
71                                                                         \
72         return 0;                                                       \
73 }
74
75 #define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask)          \
76 int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
77                                              pci_dev_t dev,             \
78                                              int offset, type val)      \
79 {                                                                       \
80         u32 val32, mask, ldata, shift;                                  \
81                                                                         \
82         if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
83                 return -1;                                              \
84                                                                         \
85         shift = ((offset & (int)off_mask) * 8);                         \
86         ldata = (((unsigned long)val) & val_mask) << shift;             \
87         mask = val_mask << shift;                                       \
88         val32 = (val32 & ~mask) | ldata;                                \
89                                                                         \
90         if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
91                 return -1;                                              \
92                                                                         \
93         return 0;                                                       \
94 }
95
96 PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
97 PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
98 PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
99 PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
100
101 /* Get a virtual address associated with a BAR region */
102 void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
103 {
104         pci_addr_t pci_bus_addr;
105         u32 bar_response;
106
107         /* read BAR address */
108         pci_read_config_dword(pdev, bar, &bar_response);
109         pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
110
111         /*
112          * Pass "0" as the length argument to pci_bus_to_virt.  The arg
113          * isn't actualy used on any platform because u-boot assumes a static
114          * linear mapping.  In the future, this could read the BAR size
115          * and pass that as the size if needed.
116          */
117         return pci_bus_to_virt(pdev, pci_bus_addr, flags, 0, MAP_NOCACHE);
118 }
119
120 /*
121  *
122  */
123
124 static struct pci_controller* hose_head;
125
126 void pci_register_hose(struct pci_controller* hose)
127 {
128         struct pci_controller **phose = &hose_head;
129
130         while(*phose)
131                 phose = &(*phose)->next;
132
133         hose->next = NULL;
134
135         *phose = hose;
136 }
137
138 struct pci_controller *pci_bus_to_hose(int bus)
139 {
140         struct pci_controller *hose;
141
142         for (hose = hose_head; hose; hose = hose->next) {
143                 if (bus >= hose->first_busno && bus <= hose->last_busno)
144                         return hose;
145         }
146
147         printf("pci_bus_to_hose() failed\n");
148         return NULL;
149 }
150
151 struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
152 {
153         struct pci_controller *hose;
154
155         for (hose = hose_head; hose; hose = hose->next) {
156                 if (hose->cfg_addr == cfg_addr)
157                         return hose;
158         }
159
160         return NULL;
161 }
162
163 int pci_last_busno(void)
164 {
165         struct pci_controller *hose = hose_head;
166
167         if (!hose)
168                 return -1;
169
170         while (hose->next)
171                 hose = hose->next;
172
173         return hose->last_busno;
174 }
175
176 pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
177 {
178         struct pci_controller * hose;
179         u16 vendor, device;
180         u8 header_type;
181         pci_dev_t bdf;
182         int i, bus, found_multi = 0;
183
184         for (hose = hose_head; hose; hose = hose->next) {
185 #ifdef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
186                 for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
187 #else
188                 for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
189 #endif
190                         for (bdf = PCI_BDF(bus, 0, 0);
191 #if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
192                              bdf < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
193                                 PCI_MAX_PCI_FUNCTIONS - 1);
194 #else
195                              bdf < PCI_BDF(bus + 1, 0, 0);
196 #endif
197                              bdf += PCI_BDF(0, 0, 1)) {
198                                 if (pci_skip_dev(hose, bdf))
199                                         continue;
200
201                                 if (!PCI_FUNC(bdf)) {
202                                         pci_read_config_byte(bdf,
203                                                              PCI_HEADER_TYPE,
204                                                              &header_type);
205
206                                         found_multi = header_type & 0x80;
207                                 } else {
208                                         if (!found_multi)
209                                                 continue;
210                                 }
211
212                                 pci_read_config_word(bdf,
213                                                      PCI_VENDOR_ID,
214                                                      &vendor);
215                                 pci_read_config_word(bdf,
216                                                      PCI_DEVICE_ID,
217                                                      &device);
218
219                                 for (i = 0; ids[i].vendor != 0; i++) {
220                                         if (vendor == ids[i].vendor &&
221                                             device == ids[i].device) {
222                                                 if (index <= 0)
223                                                         return bdf;
224
225                                                 index--;
226                                         }
227                                 }
228                         }
229         }
230
231         return -1;
232 }
233
234 pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
235 {
236         static struct pci_device_id ids[2] = {{}, {0, 0}};
237
238         ids[0].vendor = vendor;
239         ids[0].device = device;
240
241         return pci_find_devices(ids, index);
242 }
243
244 /*
245  *
246  */
247
248 int __pci_hose_phys_to_bus(struct pci_controller *hose,
249                                 phys_addr_t phys_addr,
250                                 unsigned long flags,
251                                 unsigned long skip_mask,
252                                 pci_addr_t *ba)
253 {
254         struct pci_region *res;
255         pci_addr_t bus_addr;
256         int i;
257
258         for (i = 0; i < hose->region_count; i++) {
259                 res = &hose->regions[i];
260
261                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
262                         continue;
263
264                 if (res->flags & skip_mask)
265                         continue;
266
267                 bus_addr = phys_addr - res->phys_start + res->bus_start;
268
269                 if (bus_addr >= res->bus_start &&
270                         bus_addr < res->bus_start + res->size) {
271                         *ba = bus_addr;
272                         return 0;
273                 }
274         }
275
276         return 1;
277 }
278
279 pci_addr_t pci_hose_phys_to_bus (struct pci_controller *hose,
280                                     phys_addr_t phys_addr,
281                                     unsigned long flags)
282 {
283         pci_addr_t bus_addr = 0;
284         int ret;
285
286         if (!hose) {
287                 puts("pci_hose_phys_to_bus: invalid hose\n");
288                 return bus_addr;
289         }
290
291         /*
292          * if PCI_REGION_MEM is set we do a two pass search with preference
293          * on matches that don't have PCI_REGION_SYS_MEMORY set
294          */
295         if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
296                 ret = __pci_hose_phys_to_bus(hose, phys_addr,
297                                 flags, PCI_REGION_SYS_MEMORY, &bus_addr);
298                 if (!ret)
299                         return bus_addr;
300         }
301
302         ret = __pci_hose_phys_to_bus(hose, phys_addr, flags, 0, &bus_addr);
303
304         if (ret)
305                 puts("pci_hose_phys_to_bus: invalid physical address\n");
306
307         return bus_addr;
308 }
309
310 int __pci_hose_bus_to_phys(struct pci_controller *hose,
311                                 pci_addr_t bus_addr,
312                                 unsigned long flags,
313                                 unsigned long skip_mask,
314                                 phys_addr_t *pa)
315 {
316         struct pci_region *res;
317         int i;
318
319         for (i = 0; i < hose->region_count; i++) {
320                 res = &hose->regions[i];
321
322                 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
323                         continue;
324
325                 if (res->flags & skip_mask)
326                         continue;
327
328                 if (bus_addr >= res->bus_start &&
329                         (bus_addr - res->bus_start) < res->size) {
330                         *pa = (bus_addr - res->bus_start + res->phys_start);
331                         return 0;
332                 }
333         }
334
335         return 1;
336 }
337
338 phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
339                                  pci_addr_t bus_addr,
340                                  unsigned long flags)
341 {
342         phys_addr_t phys_addr = 0;
343         int ret;
344
345         if (!hose) {
346                 puts("pci_hose_bus_to_phys: invalid hose\n");
347                 return phys_addr;
348         }
349
350         /*
351          * if PCI_REGION_MEM is set we do a two pass search with preference
352          * on matches that don't have PCI_REGION_SYS_MEMORY set
353          */
354         if ((flags & PCI_REGION_MEM) == PCI_REGION_MEM) {
355                 ret = __pci_hose_bus_to_phys(hose, bus_addr,
356                                 flags, PCI_REGION_SYS_MEMORY, &phys_addr);
357                 if (!ret)
358                         return phys_addr;
359         }
360
361         ret = __pci_hose_bus_to_phys(hose, bus_addr, flags, 0, &phys_addr);
362
363         if (ret)
364                 puts("pci_hose_bus_to_phys: invalid physical address\n");
365
366         return phys_addr;
367 }
368
369 void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
370                      u32 addr_and_ctrl)
371 {
372         int bar;
373
374         bar = PCI_BASE_ADDRESS_0 + barnum * 4;
375         pci_hose_write_config_dword(hose, dev, bar, addr_and_ctrl);
376 }
377
378 u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum)
379 {
380         u32 addr;
381         int bar;
382
383         bar = PCI_BASE_ADDRESS_0 + barnum * 4;
384         pci_hose_read_config_dword(hose, dev, bar, &addr);
385         if (addr & PCI_BASE_ADDRESS_SPACE_IO)
386                 return addr & PCI_BASE_ADDRESS_IO_MASK;
387         else
388                 return addr & PCI_BASE_ADDRESS_MEM_MASK;
389 }
390
391 int pci_hose_config_device(struct pci_controller *hose,
392                            pci_dev_t dev,
393                            unsigned long io,
394                            pci_addr_t mem,
395                            unsigned long command)
396 {
397         u32 bar_response;
398         unsigned int old_command;
399         pci_addr_t bar_value;
400         pci_size_t bar_size;
401         unsigned char pin;
402         int bar, found_mem64;
403
404         debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
405                 (u64)mem, command);
406
407         pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
408
409         for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
410                 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
411                 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
412
413                 if (!bar_response)
414                         continue;
415
416                 found_mem64 = 0;
417
418                 /* Check the BAR type and set our address mask */
419                 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
420                         bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
421                         /* round up region base address to a multiple of size */
422                         io = ((io - 1) | (bar_size - 1)) + 1;
423                         bar_value = io;
424                         /* compute new region base address */
425                         io = io + bar_size;
426                 } else {
427                         if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
428                                 PCI_BASE_ADDRESS_MEM_TYPE_64) {
429                                 u32 bar_response_upper;
430                                 u64 bar64;
431                                 pci_hose_write_config_dword(hose, dev, bar + 4,
432                                         0xffffffff);
433                                 pci_hose_read_config_dword(hose, dev, bar + 4,
434                                         &bar_response_upper);
435
436                                 bar64 = ((u64)bar_response_upper << 32) | bar_response;
437
438                                 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
439                                 found_mem64 = 1;
440                         } else {
441                                 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
442                         }
443
444                         /* round up region base address to multiple of size */
445                         mem = ((mem - 1) | (bar_size - 1)) + 1;
446                         bar_value = mem;
447                         /* compute new region base address */
448                         mem = mem + bar_size;
449                 }
450
451                 /* Write it out and update our limit */
452                 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
453
454                 if (found_mem64) {
455                         bar += 4;
456 #ifdef CONFIG_SYS_PCI_64BIT
457                         pci_hose_write_config_dword(hose, dev, bar,
458                                 (u32)(bar_value >> 32));
459 #else
460                         pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
461 #endif
462                 }
463         }
464
465         /* Configure Cache Line Size Register */
466         pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
467
468         /* Configure Latency Timer */
469         pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
470
471         /* Disable interrupt line, if device says it wants to use interrupts */
472         pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
473         if (pin != 0) {
474                 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, 0xff);
475         }
476
477         pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
478         pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
479                                      (old_command & 0xffff0000) | command);
480
481         return 0;
482 }
483
484 /*
485  *
486  */
487
488 struct pci_config_table *pci_find_config(struct pci_controller *hose,
489                                          unsigned short class,
490                                          unsigned int vendor,
491                                          unsigned int device,
492                                          unsigned int bus,
493                                          unsigned int dev,
494                                          unsigned int func)
495 {
496         struct pci_config_table *table;
497
498         for (table = hose->config_table; table && table->vendor; table++) {
499                 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
500                     (table->device == PCI_ANY_ID || table->device == device) &&
501                     (table->class  == PCI_ANY_ID || table->class  == class)  &&
502                     (table->bus    == PCI_ANY_ID || table->bus    == bus)    &&
503                     (table->dev    == PCI_ANY_ID || table->dev    == dev)    &&
504                     (table->func   == PCI_ANY_ID || table->func   == func)) {
505                         return table;
506                 }
507         }
508
509         return NULL;
510 }
511
512 void pci_cfgfunc_config_device(struct pci_controller *hose,
513                                pci_dev_t dev,
514                                struct pci_config_table *entry)
515 {
516         pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
517                 entry->priv[2]);
518 }
519
520 void pci_cfgfunc_do_nothing(struct pci_controller *hose,
521                             pci_dev_t dev, struct pci_config_table *entry)
522 {
523 }
524
525 /*
526  * HJF: Changed this to return int. I think this is required
527  * to get the correct result when scanning bridges
528  */
529 extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
530
531 #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI_SCAN_SHOW)
532 const char * pci_class_str(u8 class)
533 {
534         switch (class) {
535         case PCI_CLASS_NOT_DEFINED:
536                 return "Build before PCI Rev2.0";
537                 break;
538         case PCI_BASE_CLASS_STORAGE:
539                 return "Mass storage controller";
540                 break;
541         case PCI_BASE_CLASS_NETWORK:
542                 return "Network controller";
543                 break;
544         case PCI_BASE_CLASS_DISPLAY:
545                 return "Display controller";
546                 break;
547         case PCI_BASE_CLASS_MULTIMEDIA:
548                 return "Multimedia device";
549                 break;
550         case PCI_BASE_CLASS_MEMORY:
551                 return "Memory controller";
552                 break;
553         case PCI_BASE_CLASS_BRIDGE:
554                 return "Bridge device";
555                 break;
556         case PCI_BASE_CLASS_COMMUNICATION:
557                 return "Simple comm. controller";
558                 break;
559         case PCI_BASE_CLASS_SYSTEM:
560                 return "Base system peripheral";
561                 break;
562         case PCI_BASE_CLASS_INPUT:
563                 return "Input device";
564                 break;
565         case PCI_BASE_CLASS_DOCKING:
566                 return "Docking station";
567                 break;
568         case PCI_BASE_CLASS_PROCESSOR:
569                 return "Processor";
570                 break;
571         case PCI_BASE_CLASS_SERIAL:
572                 return "Serial bus controller";
573                 break;
574         case PCI_BASE_CLASS_INTELLIGENT:
575                 return "Intelligent controller";
576                 break;
577         case PCI_BASE_CLASS_SATELLITE:
578                 return "Satellite controller";
579                 break;
580         case PCI_BASE_CLASS_CRYPT:
581                 return "Cryptographic device";
582                 break;
583         case PCI_BASE_CLASS_SIGNAL_PROCESSING:
584                 return "DSP";
585                 break;
586         case PCI_CLASS_OTHERS:
587                 return "Does not fit any class";
588                 break;
589         default:
590         return  "???";
591                 break;
592         };
593 }
594 #endif /* CONFIG_CMD_PCI || CONFIG_PCI_SCAN_SHOW */
595
596 __weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
597 {
598         /*
599          * Check if pci device should be skipped in configuration
600          */
601         if (dev == PCI_BDF(hose->first_busno, 0, 0)) {
602 #if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
603                 /*
604                  * Only skip configuration if "pciconfighost" is not set
605                  */
606                 if (getenv("pciconfighost") == NULL)
607                         return 1;
608 #else
609                 return 1;
610 #endif
611         }
612
613         return 0;
614 }
615
616 #ifdef CONFIG_PCI_SCAN_SHOW
617 __weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
618 {
619         if (dev == PCI_BDF(hose->first_busno, 0, 0))
620                 return 0;
621
622         return 1;
623 }
624 #endif /* CONFIG_PCI_SCAN_SHOW */
625
626 int pci_hose_scan_bus(struct pci_controller *hose, int bus)
627 {
628         unsigned int sub_bus, found_multi = 0;
629         unsigned short vendor, device, class;
630         unsigned char header_type;
631 #ifndef CONFIG_PCI_PNP
632         struct pci_config_table *cfg;
633 #endif
634         pci_dev_t dev;
635 #ifdef CONFIG_PCI_SCAN_SHOW
636         static int indent = 0;
637 #endif
638
639         sub_bus = bus;
640
641         for (dev =  PCI_BDF(bus,0,0);
642              dev <  PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
643                                 PCI_MAX_PCI_FUNCTIONS - 1);
644              dev += PCI_BDF(0, 0, 1)) {
645
646                 if (pci_skip_dev(hose, dev))
647                         continue;
648
649                 if (PCI_FUNC(dev) && !found_multi)
650                         continue;
651
652                 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
653
654                 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
655
656                 if (vendor == 0xffff || vendor == 0x0000)
657                         continue;
658
659                 if (!PCI_FUNC(dev))
660                         found_multi = header_type & 0x80;
661
662                 debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
663                         PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
664
665                 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
666                 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
667
668 #ifdef CONFIG_PCI_FIXUP_DEV
669                 board_pci_fixup_dev(hose, dev, vendor, device, class);
670 #endif
671
672 #ifdef CONFIG_PCI_SCAN_SHOW
673                 indent++;
674
675                 /* Print leading space, including bus indentation */
676                 printf("%*c", indent + 1, ' ');
677
678                 if (pci_print_dev(hose, dev)) {
679                         printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
680                                PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
681                                vendor, device, pci_class_str(class >> 8));
682                 }
683 #endif
684
685 #ifdef CONFIG_PCI_PNP
686                 sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
687                               sub_bus);
688 #else
689                 cfg = pci_find_config(hose, class, vendor, device,
690                                       PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
691                 if (cfg) {
692                         cfg->config_device(hose, dev, cfg);
693                         sub_bus = max(sub_bus,
694                                       (unsigned int)hose->current_busno);
695                 }
696 #endif
697
698 #ifdef CONFIG_PCI_SCAN_SHOW
699                 indent--;
700 #endif
701
702                 if (hose->fixup_irq)
703                         hose->fixup_irq(hose, dev);
704         }
705
706         return sub_bus;
707 }
708
709 int pci_hose_scan(struct pci_controller *hose)
710 {
711 #if defined(CONFIG_PCI_BOOTDELAY)
712         static int pcidelay_done;
713         char *s;
714         int i;
715
716         if (!pcidelay_done) {
717                 /* wait "pcidelay" ms (if defined)... */
718                 s = getenv("pcidelay");
719                 if (s) {
720                         int val = simple_strtoul(s, NULL, 10);
721                         for (i = 0; i < val; i++)
722                                 udelay(1000);
723                 }
724                 pcidelay_done = 1;
725         }
726 #endif /* CONFIG_PCI_BOOTDELAY */
727
728         /*
729          * Start scan at current_busno.
730          * PCIe will start scan at first_busno+1.
731          */
732         /* For legacy support, ensure current >= first */
733         if (hose->first_busno > hose->current_busno)
734                 hose->current_busno = hose->first_busno;
735 #ifdef CONFIG_PCI_PNP
736         pciauto_config_init(hose);
737 #endif
738         return pci_hose_scan_bus(hose, hose->current_busno);
739 }
740
741 void pci_init(void)
742 {
743         hose_head = NULL;
744
745         /* now call board specific pci_init()... */
746         pci_init_board();
747 }
748
749 /* Returns the address of the requested capability structure within the
750  * device's PCI configuration space or 0 in case the device does not
751  * support it.
752  * */
753 int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
754                              int cap)
755 {
756         int pos;
757         u8 hdr_type;
758
759         pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
760
761         pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
762
763         if (pos)
764                 pos = pci_find_cap(hose, dev, pos, cap);
765
766         return pos;
767 }
768
769 /* Find the header pointer to the Capabilities*/
770 int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
771                             u8 hdr_type)
772 {
773         u16 status;
774
775         pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
776
777         if (!(status & PCI_STATUS_CAP_LIST))
778                 return 0;
779
780         switch (hdr_type) {
781         case PCI_HEADER_TYPE_NORMAL:
782         case PCI_HEADER_TYPE_BRIDGE:
783                 return PCI_CAPABILITY_LIST;
784         case PCI_HEADER_TYPE_CARDBUS:
785                 return PCI_CB_CAPABILITY_LIST;
786         default:
787                 return 0;
788         }
789 }
790
791 int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
792 {
793         int ttl = PCI_FIND_CAP_TTL;
794         u8 id;
795         u8 next_pos;
796
797         while (ttl--) {
798                 pci_hose_read_config_byte(hose, dev, pos, &next_pos);
799                 if (next_pos < CAP_START_POS)
800                         break;
801                 next_pos &= ~3;
802                 pos = (int) next_pos;
803                 pci_hose_read_config_byte(hose, dev,
804                                           pos + PCI_CAP_LIST_ID, &id);
805                 if (id == 0xff)
806                         break;
807                 if (id == cap)
808                         return pos;
809                 pos += PCI_CAP_LIST_NEXT;
810         }
811         return 0;
812 }