1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Bus Services, see include/linux/pci.h for further explanation.
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
11 #include <linux/acpi.h>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
16 #include <linux/msi.h>
18 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/module.h>
22 #include <linux/spinlock.h>
23 #include <linux/string.h>
24 #include <linux/log2.h>
25 #include <linux/logic_pio.h>
26 #include <linux/pm_wakeup.h>
27 #include <linux/interrupt.h>
28 #include <linux/device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/pci_hotplug.h>
31 #include <linux/vmalloc.h>
33 #include <linux/aer.h>
34 #include <linux/bitfield.h>
37 DEFINE_MUTEX(pci_slot_mutex);
39 const char *pci_power_names[] = {
40 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
42 EXPORT_SYMBOL_GPL(pci_power_names);
44 int isa_dma_bridge_buggy;
45 EXPORT_SYMBOL(isa_dma_bridge_buggy);
48 EXPORT_SYMBOL(pci_pci_problems);
50 unsigned int pci_pm_d3hot_delay;
52 static void pci_pme_list_scan(struct work_struct *work);
54 static LIST_HEAD(pci_pme_list);
55 static DEFINE_MUTEX(pci_pme_list_mutex);
56 static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
58 struct pci_pme_device {
59 struct list_head list;
63 #define PME_TIMEOUT 1000 /* How long between PME checks */
65 static void pci_dev_d3_sleep(struct pci_dev *dev)
67 unsigned int delay = dev->d3hot_delay;
69 if (delay < pci_pm_d3hot_delay)
70 delay = pci_pm_d3hot_delay;
76 bool pci_reset_supported(struct pci_dev *dev)
78 return dev->reset_methods[0] != 0;
81 #ifdef CONFIG_PCI_DOMAINS
82 int pci_domains_supported = 1;
85 #define DEFAULT_CARDBUS_IO_SIZE (256)
86 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
87 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
88 unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
89 unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
91 #define DEFAULT_HOTPLUG_IO_SIZE (256)
92 #define DEFAULT_HOTPLUG_MMIO_SIZE (2*1024*1024)
93 #define DEFAULT_HOTPLUG_MMIO_PREF_SIZE (2*1024*1024)
94 /* hpiosize=nn can override this */
95 unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
97 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
98 * pci=hpmmioprefsize=nnM overrides prefetchable MMIO size;
99 * pci=hpmemsize=nnM overrides both
101 unsigned long pci_hotplug_mmio_size = DEFAULT_HOTPLUG_MMIO_SIZE;
102 unsigned long pci_hotplug_mmio_pref_size = DEFAULT_HOTPLUG_MMIO_PREF_SIZE;
104 #define DEFAULT_HOTPLUG_BUS_SIZE 1
105 unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
108 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
109 #ifdef CONFIG_PCIE_BUS_TUNE_OFF
110 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_TUNE_OFF;
111 #elif defined CONFIG_PCIE_BUS_SAFE
112 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE;
113 #elif defined CONFIG_PCIE_BUS_PERFORMANCE
114 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE;
115 #elif defined CONFIG_PCIE_BUS_PEER2PEER
116 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PEER2PEER;
118 enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
122 * The default CLS is used if arch didn't set CLS explicitly and not
123 * all pci devices agree on the same value. Arch can override either
124 * the dfl or actual value as it sees fit. Don't forget this is
125 * measured in 32-bit words, not bytes.
127 u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
128 u8 pci_cache_line_size;
131 * If we set up a device for bus mastering, we need to check the latency
132 * timer as certain BIOSes forget to set it properly.
134 unsigned int pcibios_max_latency = 255;
136 /* If set, the PCIe ARI capability will not be used. */
137 static bool pcie_ari_disabled;
139 /* If set, the PCIe ATS capability will not be used. */
140 static bool pcie_ats_disabled;
142 /* If set, the PCI config space of each device is printed during boot. */
145 bool pci_ats_disabled(void)
147 return pcie_ats_disabled;
149 EXPORT_SYMBOL_GPL(pci_ats_disabled);
151 /* Disable bridge_d3 for all PCIe ports */
152 static bool pci_bridge_d3_disable;
153 /* Force bridge_d3 for all PCIe ports */
154 static bool pci_bridge_d3_force;
156 static int __init pcie_port_pm_setup(char *str)
158 if (!strcmp(str, "off"))
159 pci_bridge_d3_disable = true;
160 else if (!strcmp(str, "force"))
161 pci_bridge_d3_force = true;
164 __setup("pcie_port_pm=", pcie_port_pm_setup);
166 /* Time to wait after a reset for device to become responsive */
167 #define PCIE_RESET_READY_POLL_MS 60000
170 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
171 * @bus: pointer to PCI bus structure to search
173 * Given a PCI bus, returns the highest PCI bus number present in the set
174 * including the given PCI bus and its list of child PCI buses.
176 unsigned char pci_bus_max_busnr(struct pci_bus *bus)
179 unsigned char max, n;
181 max = bus->busn_res.end;
182 list_for_each_entry(tmp, &bus->children, node) {
183 n = pci_bus_max_busnr(tmp);
189 EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
192 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
193 * @pdev: the PCI device
195 * Returns error bits set in PCI_STATUS and clears them.
197 int pci_status_get_and_clear_errors(struct pci_dev *pdev)
202 ret = pci_read_config_word(pdev, PCI_STATUS, &status);
203 if (ret != PCIBIOS_SUCCESSFUL)
206 status &= PCI_STATUS_ERROR_BITS;
208 pci_write_config_word(pdev, PCI_STATUS, status);
212 EXPORT_SYMBOL_GPL(pci_status_get_and_clear_errors);
214 #ifdef CONFIG_HAS_IOMEM
215 static void __iomem *__pci_ioremap_resource(struct pci_dev *pdev, int bar,
218 struct resource *res = &pdev->resource[bar];
219 resource_size_t start = res->start;
220 resource_size_t size = resource_size(res);
223 * Make sure the BAR is actually a memory resource, not an IO resource
225 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
226 pci_err(pdev, "can't ioremap BAR %d: %pR\n", bar, res);
231 return ioremap_wc(start, size);
233 return ioremap(start, size);
236 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
238 return __pci_ioremap_resource(pdev, bar, false);
240 EXPORT_SYMBOL_GPL(pci_ioremap_bar);
242 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
244 return __pci_ioremap_resource(pdev, bar, true);
246 EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
250 * pci_dev_str_match_path - test if a path string matches a device
251 * @dev: the PCI device to test
252 * @path: string to match the device against
253 * @endptr: pointer to the string after the match
255 * Test if a string (typically from a kernel parameter) formatted as a
256 * path of device/function addresses matches a PCI device. The string must
259 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
261 * A path for a device can be obtained using 'lspci -t'. Using a path
262 * is more robust against bus renumbering than using only a single bus,
263 * device and function address.
265 * Returns 1 if the string matches the device, 0 if it does not and
266 * a negative error code if it fails to parse the string.
268 static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,
272 int seg, bus, slot, func;
276 *endptr = strchrnul(path, ';');
278 wpath = kmemdup_nul(path, *endptr - path, GFP_ATOMIC);
283 p = strrchr(wpath, '/');
286 ret = sscanf(p, "/%x.%x%c", &slot, &func, &end);
292 if (dev->devfn != PCI_DEVFN(slot, func)) {
298 * Note: we don't need to get a reference to the upstream
299 * bridge because we hold a reference to the top level
300 * device which should hold a reference to the bridge,
303 dev = pci_upstream_bridge(dev);
312 ret = sscanf(wpath, "%x:%x:%x.%x%c", &seg, &bus, &slot,
316 ret = sscanf(wpath, "%x:%x.%x%c", &bus, &slot, &func, &end);
323 ret = (seg == pci_domain_nr(dev->bus) &&
324 bus == dev->bus->number &&
325 dev->devfn == PCI_DEVFN(slot, func));
333 * pci_dev_str_match - test if a string matches a device
334 * @dev: the PCI device to test
335 * @p: string to match the device against
336 * @endptr: pointer to the string after the match
338 * Test if a string (typically from a kernel parameter) matches a specified
339 * PCI device. The string may be of one of the following formats:
341 * [<domain>:]<bus>:<device>.<func>[/<device>.<func>]*
342 * pci:<vendor>:<device>[:<subvendor>:<subdevice>]
344 * The first format specifies a PCI bus/device/function address which
345 * may change if new hardware is inserted, if motherboard firmware changes,
346 * or due to changes caused in kernel parameters. If the domain is
347 * left unspecified, it is taken to be 0. In order to be robust against
348 * bus renumbering issues, a path of PCI device/function numbers may be used
349 * to address the specific device. The path for a device can be determined
350 * through the use of 'lspci -t'.
352 * The second format matches devices using IDs in the configuration
353 * space which may match multiple devices in the system. A value of 0
354 * for any field will match all devices. (Note: this differs from
355 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
356 * legacy reasons and convenience so users don't have to specify
357 * FFFFFFFFs on the command line.)
359 * Returns 1 if the string matches the device, 0 if it does not and
360 * a negative error code if the string cannot be parsed.
362 static int pci_dev_str_match(struct pci_dev *dev, const char *p,
367 unsigned short vendor, device, subsystem_vendor, subsystem_device;
369 if (strncmp(p, "pci:", 4) == 0) {
370 /* PCI vendor/device (subvendor/subdevice) IDs are specified */
372 ret = sscanf(p, "%hx:%hx:%hx:%hx%n", &vendor, &device,
373 &subsystem_vendor, &subsystem_device, &count);
375 ret = sscanf(p, "%hx:%hx%n", &vendor, &device, &count);
379 subsystem_vendor = 0;
380 subsystem_device = 0;
385 if ((!vendor || vendor == dev->vendor) &&
386 (!device || device == dev->device) &&
387 (!subsystem_vendor ||
388 subsystem_vendor == dev->subsystem_vendor) &&
389 (!subsystem_device ||
390 subsystem_device == dev->subsystem_device))
394 * PCI Bus, Device, Function IDs are specified
395 * (optionally, may include a path of devfns following it)
397 ret = pci_dev_str_match_path(dev, p, &p);
412 static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
413 u8 pos, int cap, int *ttl)
418 pci_bus_read_config_byte(bus, devfn, pos, &pos);
424 pci_bus_read_config_word(bus, devfn, pos, &ent);
436 static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
439 int ttl = PCI_FIND_CAP_TTL;
441 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
444 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
446 return __pci_find_next_cap(dev->bus, dev->devfn,
447 pos + PCI_CAP_LIST_NEXT, cap);
449 EXPORT_SYMBOL_GPL(pci_find_next_capability);
451 static u8 __pci_bus_find_cap_start(struct pci_bus *bus,
452 unsigned int devfn, u8 hdr_type)
456 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
457 if (!(status & PCI_STATUS_CAP_LIST))
461 case PCI_HEADER_TYPE_NORMAL:
462 case PCI_HEADER_TYPE_BRIDGE:
463 return PCI_CAPABILITY_LIST;
464 case PCI_HEADER_TYPE_CARDBUS:
465 return PCI_CB_CAPABILITY_LIST;
472 * pci_find_capability - query for devices' capabilities
473 * @dev: PCI device to query
474 * @cap: capability code
476 * Tell if a device supports a given PCI capability.
477 * Returns the address of the requested capability structure within the
478 * device's PCI configuration space or 0 in case the device does not
479 * support it. Possible values for @cap include:
481 * %PCI_CAP_ID_PM Power Management
482 * %PCI_CAP_ID_AGP Accelerated Graphics Port
483 * %PCI_CAP_ID_VPD Vital Product Data
484 * %PCI_CAP_ID_SLOTID Slot Identification
485 * %PCI_CAP_ID_MSI Message Signalled Interrupts
486 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
487 * %PCI_CAP_ID_PCIX PCI-X
488 * %PCI_CAP_ID_EXP PCI Express
490 u8 pci_find_capability(struct pci_dev *dev, int cap)
494 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
496 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
500 EXPORT_SYMBOL(pci_find_capability);
503 * pci_bus_find_capability - query for devices' capabilities
504 * @bus: the PCI bus to query
505 * @devfn: PCI device to query
506 * @cap: capability code
508 * Like pci_find_capability() but works for PCI devices that do not have a
509 * pci_dev structure set up yet.
511 * Returns the address of the requested capability structure within the
512 * device's PCI configuration space or 0 in case the device does not
515 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
519 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
521 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
523 pos = __pci_find_next_cap(bus, devfn, pos, cap);
527 EXPORT_SYMBOL(pci_bus_find_capability);
530 * pci_find_next_ext_capability - Find an extended capability
531 * @dev: PCI device to query
532 * @start: address at which to start looking (0 to start at beginning of list)
533 * @cap: capability code
535 * Returns the address of the next matching extended capability structure
536 * within the device's PCI configuration space or 0 if the device does
537 * not support it. Some capabilities can occur several times, e.g., the
538 * vendor-specific capability, and this provides a way to find them all.
540 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap)
544 u16 pos = PCI_CFG_SPACE_SIZE;
546 /* minimum 8 bytes per capability */
547 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
549 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
555 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
559 * If we have no capabilities, this is indicated by cap ID,
560 * cap version and next pointer all being 0.
566 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
569 pos = PCI_EXT_CAP_NEXT(header);
570 if (pos < PCI_CFG_SPACE_SIZE)
573 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
579 EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
582 * pci_find_ext_capability - Find an extended capability
583 * @dev: PCI device to query
584 * @cap: capability code
586 * Returns the address of the requested extended capability structure
587 * within the device's PCI configuration space or 0 if the device does
588 * not support it. Possible values for @cap include:
590 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
591 * %PCI_EXT_CAP_ID_VC Virtual Channel
592 * %PCI_EXT_CAP_ID_DSN Device Serial Number
593 * %PCI_EXT_CAP_ID_PWR Power Budgeting
595 u16 pci_find_ext_capability(struct pci_dev *dev, int cap)
597 return pci_find_next_ext_capability(dev, 0, cap);
599 EXPORT_SYMBOL_GPL(pci_find_ext_capability);
602 * pci_get_dsn - Read and return the 8-byte Device Serial Number
603 * @dev: PCI device to query
605 * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
608 * Returns the DSN, or zero if the capability does not exist.
610 u64 pci_get_dsn(struct pci_dev *dev)
616 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DSN);
621 * The Device Serial Number is two dwords offset 4 bytes from the
622 * capability position. The specification says that the first dword is
623 * the lower half, and the second dword is the upper half.
626 pci_read_config_dword(dev, pos, &dword);
628 pci_read_config_dword(dev, pos + 4, &dword);
629 dsn |= ((u64)dword) << 32;
633 EXPORT_SYMBOL_GPL(pci_get_dsn);
635 static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap)
637 int rc, ttl = PCI_FIND_CAP_TTL;
640 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
641 mask = HT_3BIT_CAP_MASK;
643 mask = HT_5BIT_CAP_MASK;
645 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
646 PCI_CAP_ID_HT, &ttl);
648 rc = pci_read_config_byte(dev, pos + 3, &cap);
649 if (rc != PCIBIOS_SUCCESSFUL)
652 if ((cap & mask) == ht_cap)
655 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
656 pos + PCI_CAP_LIST_NEXT,
657 PCI_CAP_ID_HT, &ttl);
664 * pci_find_next_ht_capability - query a device's HyperTransport capabilities
665 * @dev: PCI device to query
666 * @pos: Position from which to continue searching
667 * @ht_cap: HyperTransport capability code
669 * To be used in conjunction with pci_find_ht_capability() to search for
670 * all capabilities matching @ht_cap. @pos should always be a value returned
671 * from pci_find_ht_capability().
673 * NB. To be 100% safe against broken PCI devices, the caller should take
674 * steps to avoid an infinite loop.
676 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap)
678 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
680 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
683 * pci_find_ht_capability - query a device's HyperTransport capabilities
684 * @dev: PCI device to query
685 * @ht_cap: HyperTransport capability code
687 * Tell if a device supports a given HyperTransport capability.
688 * Returns an address within the device's PCI configuration space
689 * or 0 in case the device does not support the request capability.
690 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
691 * which has a HyperTransport capability matching @ht_cap.
693 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
697 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
699 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
703 EXPORT_SYMBOL_GPL(pci_find_ht_capability);
706 * pci_find_vsec_capability - Find a vendor-specific extended capability
707 * @dev: PCI device to query
708 * @vendor: Vendor ID for which capability is defined
709 * @cap: Vendor-specific capability ID
711 * If @dev has Vendor ID @vendor, search for a VSEC capability with
712 * VSEC ID @cap. If found, return the capability offset in
713 * config space; otherwise return 0.
715 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap)
720 if (vendor != dev->vendor)
723 while ((vsec = pci_find_next_ext_capability(dev, vsec,
724 PCI_EXT_CAP_ID_VNDR))) {
725 if (pci_read_config_dword(dev, vsec + PCI_VNDR_HEADER,
726 &header) == PCIBIOS_SUCCESSFUL &&
727 PCI_VNDR_HEADER_ID(header) == cap)
733 EXPORT_SYMBOL_GPL(pci_find_vsec_capability);
736 * pci_find_parent_resource - return resource region of parent bus of given
738 * @dev: PCI device structure contains resources to be searched
739 * @res: child resource record for which parent is sought
741 * For given resource region of given device, return the resource region of
742 * parent bus the given region is contained in.
744 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
745 struct resource *res)
747 const struct pci_bus *bus = dev->bus;
751 pci_bus_for_each_resource(bus, r, i) {
754 if (resource_contains(r, res)) {
757 * If the window is prefetchable but the BAR is
758 * not, the allocator made a mistake.
760 if (r->flags & IORESOURCE_PREFETCH &&
761 !(res->flags & IORESOURCE_PREFETCH))
765 * If we're below a transparent bridge, there may
766 * be both a positively-decoded aperture and a
767 * subtractively-decoded region that contain the BAR.
768 * We want the positively-decoded one, so this depends
769 * on pci_bus_for_each_resource() giving us those
777 EXPORT_SYMBOL(pci_find_parent_resource);
780 * pci_find_resource - Return matching PCI device resource
781 * @dev: PCI device to query
782 * @res: Resource to look for
784 * Goes over standard PCI resources (BARs) and checks if the given resource
785 * is partially or fully contained in any of them. In that case the
786 * matching resource is returned, %NULL otherwise.
788 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
792 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
793 struct resource *r = &dev->resource[i];
795 if (r->start && resource_contains(r, res))
801 EXPORT_SYMBOL(pci_find_resource);
804 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
805 * @dev: the PCI device to operate on
806 * @pos: config space offset of status word
807 * @mask: mask of bit(s) to care about in status word
809 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
811 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
815 /* Wait for Transaction Pending bit clean */
816 for (i = 0; i < 4; i++) {
819 msleep((1 << (i - 1)) * 100);
821 pci_read_config_word(dev, pos, &status);
822 if (!(status & mask))
829 static int pci_acs_enable;
832 * pci_request_acs - ask for ACS to be enabled if supported
834 void pci_request_acs(void)
839 static const char *disable_acs_redir_param;
842 * pci_disable_acs_redir - disable ACS redirect capabilities
843 * @dev: the PCI device
845 * For only devices specified in the disable_acs_redir parameter.
847 static void pci_disable_acs_redir(struct pci_dev *dev)
854 if (!disable_acs_redir_param)
857 p = disable_acs_redir_param;
859 ret = pci_dev_str_match(dev, p, &p);
861 pr_info_once("PCI: Can't parse disable_acs_redir parameter: %s\n",
862 disable_acs_redir_param);
865 } else if (ret == 1) {
870 if (*p != ';' && *p != ',') {
871 /* End of param or invalid format */
880 if (!pci_dev_specific_disable_acs_redir(dev))
885 pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
889 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
891 /* P2P Request & Completion Redirect */
892 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC);
894 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
896 pci_info(dev, "disabled ACS redirect\n");
900 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
901 * @dev: the PCI device
903 static void pci_std_enable_acs(struct pci_dev *dev)
913 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
914 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
916 /* Source Validation */
917 ctrl |= (cap & PCI_ACS_SV);
919 /* P2P Request Redirect */
920 ctrl |= (cap & PCI_ACS_RR);
922 /* P2P Completion Redirect */
923 ctrl |= (cap & PCI_ACS_CR);
925 /* Upstream Forwarding */
926 ctrl |= (cap & PCI_ACS_UF);
928 /* Enable Translation Blocking for external devices and noats */
929 if (pci_ats_disabled() || dev->external_facing || dev->untrusted)
930 ctrl |= (cap & PCI_ACS_TB);
932 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
936 * pci_enable_acs - enable ACS if hardware support it
937 * @dev: the PCI device
939 static void pci_enable_acs(struct pci_dev *dev)
942 goto disable_acs_redir;
944 if (!pci_dev_specific_enable_acs(dev))
945 goto disable_acs_redir;
947 pci_std_enable_acs(dev);
951 * Note: pci_disable_acs_redir() must be called even if ACS was not
952 * enabled by the kernel because it may have been enabled by
953 * platform firmware. So if we are told to disable it, we should
954 * always disable it after setting the kernel's default
957 pci_disable_acs_redir(dev);
961 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
962 * @dev: PCI device to have its BARs restored
964 * Restore the BAR values for a given device, so as to make it
965 * accessible by its driver.
967 static void pci_restore_bars(struct pci_dev *dev)
971 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
972 pci_update_resource(dev, i);
975 static const struct pci_platform_pm_ops *pci_platform_pm;
977 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
979 if (!ops->is_manageable || !ops->set_state || !ops->get_state ||
980 !ops->choose_state || !ops->set_wakeup || !ops->need_resume)
982 pci_platform_pm = ops;
986 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
988 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
991 static inline int platform_pci_set_power_state(struct pci_dev *dev,
994 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
997 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
999 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
1002 static inline void platform_pci_refresh_power_state(struct pci_dev *dev)
1004 if (pci_platform_pm && pci_platform_pm->refresh_state)
1005 pci_platform_pm->refresh_state(dev);
1008 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
1010 return pci_platform_pm ?
1011 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
1014 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
1016 return pci_platform_pm ?
1017 pci_platform_pm->set_wakeup(dev, enable) : -ENODEV;
1020 static inline bool platform_pci_need_resume(struct pci_dev *dev)
1022 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
1025 static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
1027 if (pci_platform_pm && pci_platform_pm->bridge_d3)
1028 return pci_platform_pm->bridge_d3(dev);
1033 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
1035 * @dev: PCI device to handle.
1036 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1039 * -EINVAL if the requested state is invalid.
1040 * -EIO if device does not support PCI PM or its PM capabilities register has a
1041 * wrong version, or device doesn't support the requested state.
1042 * 0 if device already is in the requested state.
1043 * 0 if device's power state has been successfully changed.
1045 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
1048 bool need_restore = false;
1050 /* Check if we're already there */
1051 if (dev->current_state == state)
1057 if (state < PCI_D0 || state > PCI_D3hot)
1061 * Validate transition: We can enter D0 from any state, but if
1062 * we're already in a low-power state, we can only go deeper. E.g.,
1063 * we can go from D1 to D3, but we can't go directly from D3 to D1;
1064 * we'd have to go from D3 to D0, then to D1.
1066 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
1067 && dev->current_state > state) {
1068 pci_err(dev, "invalid power transition (from %s to %s)\n",
1069 pci_power_name(dev->current_state),
1070 pci_power_name(state));
1074 /* Check if this device supports the desired state */
1075 if ((state == PCI_D1 && !dev->d1_support)
1076 || (state == PCI_D2 && !dev->d2_support))
1079 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1080 if (pmcsr == (u16) ~0) {
1081 pci_err(dev, "can't change power state from %s to %s (config space inaccessible)\n",
1082 pci_power_name(dev->current_state),
1083 pci_power_name(state));
1088 * If we're (effectively) in D3, force entire word to 0.
1089 * This doesn't affect PME_Status, disables PME_En, and
1090 * sets PowerState to 0.
1092 switch (dev->current_state) {
1096 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
1101 case PCI_UNKNOWN: /* Boot-up */
1102 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
1103 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
1104 need_restore = true;
1105 fallthrough; /* force to D0 */
1111 /* Enter specified state */
1112 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1115 * Mandatory power management transition delays; see PCI PM 1.1
1118 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
1119 pci_dev_d3_sleep(dev);
1120 else if (state == PCI_D2 || dev->current_state == PCI_D2)
1121 udelay(PCI_PM_D2_DELAY);
1123 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1124 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1125 if (dev->current_state != state)
1126 pci_info_ratelimited(dev, "refused to change power state from %s to %s\n",
1127 pci_power_name(dev->current_state),
1128 pci_power_name(state));
1131 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
1132 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
1133 * from D3hot to D0 _may_ perform an internal reset, thereby
1134 * going to "D0 Uninitialized" rather than "D0 Initialized".
1135 * For example, at least some versions of the 3c905B and the
1136 * 3c556B exhibit this behaviour.
1138 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
1139 * devices in a D3hot state at boot. Consequently, we need to
1140 * restore at least the BARs so that the device will be
1141 * accessible to its driver.
1144 pci_restore_bars(dev);
1147 pcie_aspm_pm_state_change(dev->bus->self);
1153 * pci_update_current_state - Read power state of given device and cache it
1154 * @dev: PCI device to handle.
1155 * @state: State to cache in case the device doesn't have the PM capability
1157 * The power state is read from the PMCSR register, which however is
1158 * inaccessible in D3cold. The platform firmware is therefore queried first
1159 * to detect accessibility of the register. In case the platform firmware
1160 * reports an incorrect state or the device isn't power manageable by the
1161 * platform at all, we try to detect D3cold by testing accessibility of the
1162 * vendor ID in config space.
1164 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
1166 if (platform_pci_get_power_state(dev) == PCI_D3cold ||
1167 !pci_device_is_present(dev)) {
1168 dev->current_state = PCI_D3cold;
1169 } else if (dev->pm_cap) {
1172 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1173 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1175 dev->current_state = state;
1180 * pci_refresh_power_state - Refresh the given device's power state data
1181 * @dev: Target PCI device.
1183 * Ask the platform to refresh the devices power state information and invoke
1184 * pci_update_current_state() to update its current PCI power state.
1186 void pci_refresh_power_state(struct pci_dev *dev)
1188 if (platform_pci_power_manageable(dev))
1189 platform_pci_refresh_power_state(dev);
1191 pci_update_current_state(dev, dev->current_state);
1195 * pci_platform_power_transition - Use platform to change device power state
1196 * @dev: PCI device to handle.
1197 * @state: State to put the device into.
1199 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
1203 if (platform_pci_power_manageable(dev)) {
1204 error = platform_pci_set_power_state(dev, state);
1206 pci_update_current_state(dev, state);
1210 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
1211 dev->current_state = PCI_D0;
1215 EXPORT_SYMBOL_GPL(pci_platform_power_transition);
1217 static int pci_resume_one(struct pci_dev *pci_dev, void *ign)
1219 pm_request_resume(&pci_dev->dev);
1224 * pci_resume_bus - Walk given bus and runtime resume devices on it
1225 * @bus: Top bus of the subtree to walk.
1227 void pci_resume_bus(struct pci_bus *bus)
1230 pci_walk_bus(bus, pci_resume_one, NULL);
1233 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
1239 * After reset, the device should not silently discard config
1240 * requests, but it may still indicate that it needs more time by
1241 * responding to them with CRS completions. The Root Port will
1242 * generally synthesize ~0 data to complete the read (except when
1243 * CRS SV is enabled and the read was for the Vendor ID; in that
1244 * case it synthesizes 0x0001 data).
1246 * Wait for the device to return a non-CRS completion. Read the
1247 * Command register instead of Vendor ID so we don't have to
1248 * contend with the CRS SV value.
1250 pci_read_config_dword(dev, PCI_COMMAND, &id);
1252 if (delay > timeout) {
1253 pci_warn(dev, "not ready %dms after %s; giving up\n",
1254 delay - 1, reset_type);
1259 pci_info(dev, "not ready %dms after %s; waiting\n",
1260 delay - 1, reset_type);
1264 pci_read_config_dword(dev, PCI_COMMAND, &id);
1268 pci_info(dev, "ready %dms after %s\n", delay - 1,
1275 * pci_power_up - Put the given device into D0
1276 * @dev: PCI device to power up
1278 int pci_power_up(struct pci_dev *dev)
1280 pci_platform_power_transition(dev, PCI_D0);
1283 * Mandatory power management transition delays are handled in
1284 * pci_pm_resume_noirq() and pci_pm_runtime_resume() of the
1285 * corresponding bridge.
1287 if (dev->runtime_d3cold) {
1289 * When powering on a bridge from D3cold, the whole hierarchy
1290 * may be powered on into D0uninitialized state, resume them to
1291 * give them a chance to suspend again
1293 pci_resume_bus(dev->subordinate);
1296 return pci_raw_set_power_state(dev, PCI_D0);
1300 * __pci_dev_set_current_state - Set current state of a PCI device
1301 * @dev: Device to handle
1302 * @data: pointer to state to be set
1304 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
1306 pci_power_t state = *(pci_power_t *)data;
1308 dev->current_state = state;
1313 * pci_bus_set_current_state - Walk given bus and set current state of devices
1314 * @bus: Top bus of the subtree to walk.
1315 * @state: state to be set
1317 void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
1320 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
1324 * pci_set_power_state - Set the power state of a PCI device
1325 * @dev: PCI device to handle.
1326 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
1328 * Transition a device to a new power state, using the platform firmware and/or
1329 * the device's PCI PM registers.
1332 * -EINVAL if the requested state is invalid.
1333 * -EIO if device does not support PCI PM or its PM capabilities register has a
1334 * wrong version, or device doesn't support the requested state.
1335 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1336 * 0 if device already is in the requested state.
1337 * 0 if the transition is to D3 but D3 is not supported.
1338 * 0 if device's power state has been successfully changed.
1340 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1344 /* Bound the state we're entering */
1345 if (state > PCI_D3cold)
1347 else if (state < PCI_D0)
1349 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
1352 * If the device or the parent bridge do not support PCI
1353 * PM, ignore the request if we're doing anything other
1354 * than putting it into D0 (which would only happen on
1359 /* Check if we're already there */
1360 if (dev->current_state == state)
1363 if (state == PCI_D0)
1364 return pci_power_up(dev);
1367 * This device is quirked not to be put into D3, so don't put it in
1370 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1374 * To put device in D3cold, we put device into D3hot in native
1375 * way, then put device into D3cold with platform ops
1377 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
1380 if (pci_platform_power_transition(dev, state))
1383 /* Powering off a bridge may power off the whole hierarchy */
1384 if (state == PCI_D3cold)
1385 pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
1389 EXPORT_SYMBOL(pci_set_power_state);
1392 * pci_choose_state - Choose the power state of a PCI device
1393 * @dev: PCI device to be suspended
1394 * @state: target sleep state for the whole system. This is the value
1395 * that is passed to suspend() function.
1397 * Returns PCI power state suitable for given device and given system
1400 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
1407 ret = platform_pci_choose_state(dev);
1408 if (ret != PCI_POWER_ERROR)
1411 switch (state.event) {
1414 case PM_EVENT_FREEZE:
1415 case PM_EVENT_PRETHAW:
1416 /* REVISIT both freeze and pre-thaw "should" use D0 */
1417 case PM_EVENT_SUSPEND:
1418 case PM_EVENT_HIBERNATE:
1421 pci_info(dev, "unrecognized suspend event %d\n",
1427 EXPORT_SYMBOL(pci_choose_state);
1429 #define PCI_EXP_SAVE_REGS 7
1431 static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
1432 u16 cap, bool extended)
1434 struct pci_cap_saved_state *tmp;
1436 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
1437 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
1443 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1445 return _pci_find_saved_cap(dev, cap, false);
1448 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1450 return _pci_find_saved_cap(dev, cap, true);
1453 static int pci_save_pcie_state(struct pci_dev *dev)
1456 struct pci_cap_saved_state *save_state;
1459 if (!pci_is_pcie(dev))
1462 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1464 pci_err(dev, "buffer not found in %s\n", __func__);
1468 cap = (u16 *)&save_state->cap.data[0];
1469 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1470 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1471 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1472 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1473 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1474 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1475 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1480 static void pci_restore_pcie_state(struct pci_dev *dev)
1483 struct pci_cap_saved_state *save_state;
1486 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1490 cap = (u16 *)&save_state->cap.data[0];
1491 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1492 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1493 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1494 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1495 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1496 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1497 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1500 static int pci_save_pcix_state(struct pci_dev *dev)
1503 struct pci_cap_saved_state *save_state;
1505 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1509 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1511 pci_err(dev, "buffer not found in %s\n", __func__);
1515 pci_read_config_word(dev, pos + PCI_X_CMD,
1516 (u16 *)save_state->cap.data);
1521 static void pci_restore_pcix_state(struct pci_dev *dev)
1524 struct pci_cap_saved_state *save_state;
1527 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1528 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1529 if (!save_state || !pos)
1531 cap = (u16 *)&save_state->cap.data[0];
1533 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1536 static void pci_save_ltr_state(struct pci_dev *dev)
1539 struct pci_cap_saved_state *save_state;
1542 if (!pci_is_pcie(dev))
1545 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1549 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1551 pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
1555 cap = (u16 *)&save_state->cap.data[0];
1556 pci_read_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap++);
1557 pci_read_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, cap++);
1560 static void pci_restore_ltr_state(struct pci_dev *dev)
1562 struct pci_cap_saved_state *save_state;
1566 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1567 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1568 if (!save_state || !ltr)
1571 cap = (u16 *)&save_state->cap.data[0];
1572 pci_write_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap++);
1573 pci_write_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, *cap++);
1577 * pci_save_state - save the PCI configuration space of a device before
1579 * @dev: PCI device that we're dealing with
1581 int pci_save_state(struct pci_dev *dev)
1584 /* XXX: 100% dword access ok here? */
1585 for (i = 0; i < 16; i++) {
1586 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1587 pci_dbg(dev, "saving config space at offset %#x (reading %#x)\n",
1588 i * 4, dev->saved_config_space[i]);
1590 dev->state_saved = true;
1592 i = pci_save_pcie_state(dev);
1596 i = pci_save_pcix_state(dev);
1600 pci_save_ltr_state(dev);
1601 pci_save_dpc_state(dev);
1602 pci_save_aer_state(dev);
1603 pci_save_ptm_state(dev);
1604 return pci_save_vc_state(dev);
1606 EXPORT_SYMBOL(pci_save_state);
1608 static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1609 u32 saved_val, int retry, bool force)
1613 pci_read_config_dword(pdev, offset, &val);
1614 if (!force && val == saved_val)
1618 pci_dbg(pdev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1619 offset, val, saved_val);
1620 pci_write_config_dword(pdev, offset, saved_val);
1624 pci_read_config_dword(pdev, offset, &val);
1625 if (val == saved_val)
1632 static void pci_restore_config_space_range(struct pci_dev *pdev,
1633 int start, int end, int retry,
1638 for (index = end; index >= start; index--)
1639 pci_restore_config_dword(pdev, 4 * index,
1640 pdev->saved_config_space[index],
1644 static void pci_restore_config_space(struct pci_dev *pdev)
1646 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1647 pci_restore_config_space_range(pdev, 10, 15, 0, false);
1648 /* Restore BARs before the command register. */
1649 pci_restore_config_space_range(pdev, 4, 9, 10, false);
1650 pci_restore_config_space_range(pdev, 0, 3, 0, false);
1651 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
1652 pci_restore_config_space_range(pdev, 12, 15, 0, false);
1655 * Force rewriting of prefetch registers to avoid S3 resume
1656 * issues on Intel PCI bridges that occur when these
1657 * registers are not explicitly written.
1659 pci_restore_config_space_range(pdev, 9, 11, 0, true);
1660 pci_restore_config_space_range(pdev, 0, 8, 0, false);
1662 pci_restore_config_space_range(pdev, 0, 15, 0, false);
1666 static void pci_restore_rebar_state(struct pci_dev *pdev)
1668 unsigned int pos, nbars, i;
1671 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
1675 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1676 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
1677 PCI_REBAR_CTRL_NBAR_SHIFT;
1679 for (i = 0; i < nbars; i++, pos += 8) {
1680 struct resource *res;
1683 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
1684 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
1685 res = pdev->resource + bar_idx;
1686 size = pci_rebar_bytes_to_size(resource_size(res));
1687 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
1688 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
1689 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
1694 * pci_restore_state - Restore the saved state of a PCI device
1695 * @dev: PCI device that we're dealing with
1697 void pci_restore_state(struct pci_dev *dev)
1699 if (!dev->state_saved)
1703 * Restore max latencies (in the LTR capability) before enabling
1704 * LTR itself (in the PCIe capability).
1706 pci_restore_ltr_state(dev);
1708 pci_restore_pcie_state(dev);
1709 pci_restore_pasid_state(dev);
1710 pci_restore_pri_state(dev);
1711 pci_restore_ats_state(dev);
1712 pci_restore_vc_state(dev);
1713 pci_restore_rebar_state(dev);
1714 pci_restore_dpc_state(dev);
1715 pci_restore_ptm_state(dev);
1717 pci_aer_clear_status(dev);
1718 pci_restore_aer_state(dev);
1720 pci_restore_config_space(dev);
1722 pci_restore_pcix_state(dev);
1723 pci_restore_msi_state(dev);
1725 /* Restore ACS and IOV configuration state */
1726 pci_enable_acs(dev);
1727 pci_restore_iov_state(dev);
1729 dev->state_saved = false;
1731 EXPORT_SYMBOL(pci_restore_state);
1733 struct pci_saved_state {
1734 u32 config_space[16];
1735 struct pci_cap_saved_data cap[];
1739 * pci_store_saved_state - Allocate and return an opaque struct containing
1740 * the device saved state.
1741 * @dev: PCI device that we're dealing with
1743 * Return NULL if no state or error.
1745 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1747 struct pci_saved_state *state;
1748 struct pci_cap_saved_state *tmp;
1749 struct pci_cap_saved_data *cap;
1752 if (!dev->state_saved)
1755 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1757 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1758 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1760 state = kzalloc(size, GFP_KERNEL);
1764 memcpy(state->config_space, dev->saved_config_space,
1765 sizeof(state->config_space));
1768 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1769 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1770 memcpy(cap, &tmp->cap, len);
1771 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1773 /* Empty cap_save terminates list */
1777 EXPORT_SYMBOL_GPL(pci_store_saved_state);
1780 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1781 * @dev: PCI device that we're dealing with
1782 * @state: Saved state returned from pci_store_saved_state()
1784 int pci_load_saved_state(struct pci_dev *dev,
1785 struct pci_saved_state *state)
1787 struct pci_cap_saved_data *cap;
1789 dev->state_saved = false;
1794 memcpy(dev->saved_config_space, state->config_space,
1795 sizeof(state->config_space));
1799 struct pci_cap_saved_state *tmp;
1801 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1802 if (!tmp || tmp->cap.size != cap->size)
1805 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1806 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1807 sizeof(struct pci_cap_saved_data) + cap->size);
1810 dev->state_saved = true;
1813 EXPORT_SYMBOL_GPL(pci_load_saved_state);
1816 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1817 * and free the memory allocated for it.
1818 * @dev: PCI device that we're dealing with
1819 * @state: Pointer to saved state returned from pci_store_saved_state()
1821 int pci_load_and_free_saved_state(struct pci_dev *dev,
1822 struct pci_saved_state **state)
1824 int ret = pci_load_saved_state(dev, *state);
1829 EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1831 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1833 return pci_enable_resources(dev, bars);
1836 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1839 struct pci_dev *bridge;
1843 err = pci_set_power_state(dev, PCI_D0);
1844 if (err < 0 && err != -EIO)
1847 bridge = pci_upstream_bridge(dev);
1849 pcie_aspm_powersave_config_link(bridge);
1851 err = pcibios_enable_device(dev, bars);
1854 pci_fixup_device(pci_fixup_enable, dev);
1856 if (dev->msi_enabled || dev->msix_enabled)
1859 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1861 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1862 if (cmd & PCI_COMMAND_INTX_DISABLE)
1863 pci_write_config_word(dev, PCI_COMMAND,
1864 cmd & ~PCI_COMMAND_INTX_DISABLE);
1871 * pci_reenable_device - Resume abandoned device
1872 * @dev: PCI device to be resumed
1874 * NOTE: This function is a backend of pci_default_resume() and is not supposed
1875 * to be called by normal code, write proper resume handler and use it instead.
1877 int pci_reenable_device(struct pci_dev *dev)
1879 if (pci_is_enabled(dev))
1880 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1883 EXPORT_SYMBOL(pci_reenable_device);
1885 static void pci_enable_bridge(struct pci_dev *dev)
1887 struct pci_dev *bridge;
1890 bridge = pci_upstream_bridge(dev);
1892 pci_enable_bridge(bridge);
1894 if (pci_is_enabled(dev)) {
1895 if (!dev->is_busmaster)
1896 pci_set_master(dev);
1900 retval = pci_enable_device(dev);
1902 pci_err(dev, "Error enabling bridge (%d), continuing\n",
1904 pci_set_master(dev);
1907 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1909 struct pci_dev *bridge;
1914 * Power state could be unknown at this point, either due to a fresh
1915 * boot or a device removal call. So get the current power state
1916 * so that things like MSI message writing will behave as expected
1917 * (e.g. if the device really is in D0 at enable time).
1919 pci_update_current_state(dev, dev->current_state);
1921 if (atomic_inc_return(&dev->enable_cnt) > 1)
1922 return 0; /* already enabled */
1924 bridge = pci_upstream_bridge(dev);
1926 pci_enable_bridge(bridge);
1928 /* only skip sriov related */
1929 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1930 if (dev->resource[i].flags & flags)
1932 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
1933 if (dev->resource[i].flags & flags)
1936 err = do_pci_enable_device(dev, bars);
1938 atomic_dec(&dev->enable_cnt);
1943 * pci_enable_device_io - Initialize a device for use with IO space
1944 * @dev: PCI device to be initialized
1946 * Initialize device before it's used by a driver. Ask low-level code
1947 * to enable I/O resources. Wake up the device if it was suspended.
1948 * Beware, this function can fail.
1950 int pci_enable_device_io(struct pci_dev *dev)
1952 return pci_enable_device_flags(dev, IORESOURCE_IO);
1954 EXPORT_SYMBOL(pci_enable_device_io);
1957 * pci_enable_device_mem - Initialize a device for use with Memory space
1958 * @dev: PCI device to be initialized
1960 * Initialize device before it's used by a driver. Ask low-level code
1961 * to enable Memory resources. Wake up the device if it was suspended.
1962 * Beware, this function can fail.
1964 int pci_enable_device_mem(struct pci_dev *dev)
1966 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1968 EXPORT_SYMBOL(pci_enable_device_mem);
1971 * pci_enable_device - Initialize device before it's used by a driver.
1972 * @dev: PCI device to be initialized
1974 * Initialize device before it's used by a driver. Ask low-level code
1975 * to enable I/O and memory. Wake up the device if it was suspended.
1976 * Beware, this function can fail.
1978 * Note we don't actually enable the device many times if we call
1979 * this function repeatedly (we just increment the count).
1981 int pci_enable_device(struct pci_dev *dev)
1983 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1985 EXPORT_SYMBOL(pci_enable_device);
1988 * Managed PCI resources. This manages device on/off, INTx/MSI/MSI-X
1989 * on/off and BAR regions. pci_dev itself records MSI/MSI-X status, so
1990 * there's no need to track it separately. pci_devres is initialized
1991 * when a device is enabled using managed PCI device enable interface.
1994 unsigned int enabled:1;
1995 unsigned int pinned:1;
1996 unsigned int orig_intx:1;
1997 unsigned int restore_intx:1;
2002 static void pcim_release(struct device *gendev, void *res)
2004 struct pci_dev *dev = to_pci_dev(gendev);
2005 struct pci_devres *this = res;
2008 if (dev->msi_enabled)
2009 pci_disable_msi(dev);
2010 if (dev->msix_enabled)
2011 pci_disable_msix(dev);
2013 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
2014 if (this->region_mask & (1 << i))
2015 pci_release_region(dev, i);
2020 if (this->restore_intx)
2021 pci_intx(dev, this->orig_intx);
2023 if (this->enabled && !this->pinned)
2024 pci_disable_device(dev);
2027 static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
2029 struct pci_devres *dr, *new_dr;
2031 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
2035 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
2038 return devres_get(&pdev->dev, new_dr, NULL, NULL);
2041 static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
2043 if (pci_is_managed(pdev))
2044 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
2049 * pcim_enable_device - Managed pci_enable_device()
2050 * @pdev: PCI device to be initialized
2052 * Managed pci_enable_device().
2054 int pcim_enable_device(struct pci_dev *pdev)
2056 struct pci_devres *dr;
2059 dr = get_pci_dr(pdev);
2065 rc = pci_enable_device(pdev);
2067 pdev->is_managed = 1;
2072 EXPORT_SYMBOL(pcim_enable_device);
2075 * pcim_pin_device - Pin managed PCI device
2076 * @pdev: PCI device to pin
2078 * Pin managed PCI device @pdev. Pinned device won't be disabled on
2079 * driver detach. @pdev must have been enabled with
2080 * pcim_enable_device().
2082 void pcim_pin_device(struct pci_dev *pdev)
2084 struct pci_devres *dr;
2086 dr = find_pci_dr(pdev);
2087 WARN_ON(!dr || !dr->enabled);
2091 EXPORT_SYMBOL(pcim_pin_device);
2094 * pcibios_add_device - provide arch specific hooks when adding device dev
2095 * @dev: the PCI device being added
2097 * Permits the platform to provide architecture specific functionality when
2098 * devices are added. This is the default implementation. Architecture
2099 * implementations can override this.
2101 int __weak pcibios_add_device(struct pci_dev *dev)
2107 * pcibios_release_device - provide arch specific hooks when releasing
2109 * @dev: the PCI device being released
2111 * Permits the platform to provide architecture specific functionality when
2112 * devices are released. This is the default implementation. Architecture
2113 * implementations can override this.
2115 void __weak pcibios_release_device(struct pci_dev *dev) {}
2118 * pcibios_disable_device - disable arch specific PCI resources for device dev
2119 * @dev: the PCI device to disable
2121 * Disables architecture specific PCI resources for the device. This
2122 * is the default implementation. Architecture implementations can
2125 void __weak pcibios_disable_device(struct pci_dev *dev) {}
2128 * pcibios_penalize_isa_irq - penalize an ISA IRQ
2129 * @irq: ISA IRQ to penalize
2130 * @active: IRQ active or not
2132 * Permits the platform to provide architecture-specific functionality when
2133 * penalizing ISA IRQs. This is the default implementation. Architecture
2134 * implementations can override this.
2136 void __weak pcibios_penalize_isa_irq(int irq, int active) {}
2138 static void do_pci_disable_device(struct pci_dev *dev)
2142 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
2143 if (pci_command & PCI_COMMAND_MASTER) {
2144 pci_command &= ~PCI_COMMAND_MASTER;
2145 pci_write_config_word(dev, PCI_COMMAND, pci_command);
2148 pcibios_disable_device(dev);
2152 * pci_disable_enabled_device - Disable device without updating enable_cnt
2153 * @dev: PCI device to disable
2155 * NOTE: This function is a backend of PCI power management routines and is
2156 * not supposed to be called drivers.
2158 void pci_disable_enabled_device(struct pci_dev *dev)
2160 if (pci_is_enabled(dev))
2161 do_pci_disable_device(dev);
2165 * pci_disable_device - Disable PCI device after use
2166 * @dev: PCI device to be disabled
2168 * Signal to the system that the PCI device is not in use by the system
2169 * anymore. This only involves disabling PCI bus-mastering, if active.
2171 * Note we don't actually disable the device until all callers of
2172 * pci_enable_device() have called pci_disable_device().
2174 void pci_disable_device(struct pci_dev *dev)
2176 struct pci_devres *dr;
2178 dr = find_pci_dr(dev);
2182 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
2183 "disabling already-disabled device");
2185 if (atomic_dec_return(&dev->enable_cnt) != 0)
2188 do_pci_disable_device(dev);
2190 dev->is_busmaster = 0;
2192 EXPORT_SYMBOL(pci_disable_device);
2195 * pcibios_set_pcie_reset_state - set reset state for device dev
2196 * @dev: the PCIe device reset
2197 * @state: Reset state to enter into
2199 * Set the PCIe reset state for the device. This is the default
2200 * implementation. Architecture implementations can override this.
2202 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
2203 enum pcie_reset_state state)
2209 * pci_set_pcie_reset_state - set reset state for device dev
2210 * @dev: the PCIe device reset
2211 * @state: Reset state to enter into
2213 * Sets the PCI reset state for the device.
2215 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
2217 return pcibios_set_pcie_reset_state(dev, state);
2219 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
2221 void pcie_clear_device_status(struct pci_dev *dev)
2225 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);
2226 pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);
2230 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2231 * @dev: PCIe root port or event collector.
2233 void pcie_clear_root_pme_status(struct pci_dev *dev)
2235 pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
2239 * pci_check_pme_status - Check if given device has generated PME.
2240 * @dev: Device to check.
2242 * Check the PME status of the device and if set, clear it and clear PME enable
2243 * (if set). Return 'true' if PME status and PME enable were both set or
2244 * 'false' otherwise.
2246 bool pci_check_pme_status(struct pci_dev *dev)
2255 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
2256 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
2257 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
2260 /* Clear PME status. */
2261 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2262 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
2263 /* Disable PME to avoid interrupt flood. */
2264 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2268 pci_write_config_word(dev, pmcsr_pos, pmcsr);
2274 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2275 * @dev: Device to handle.
2276 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
2278 * Check if @dev has generated PME and queue a resume request for it in that
2281 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
2283 if (pme_poll_reset && dev->pme_poll)
2284 dev->pme_poll = false;
2286 if (pci_check_pme_status(dev)) {
2287 pci_wakeup_event(dev);
2288 pm_request_resume(&dev->dev);
2294 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2295 * @bus: Top bus of the subtree to walk.
2297 void pci_pme_wakeup_bus(struct pci_bus *bus)
2300 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
2305 * pci_pme_capable - check the capability of PCI device to generate PME#
2306 * @dev: PCI device to handle.
2307 * @state: PCI state from which device will issue PME#.
2309 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
2314 return !!(dev->pme_support & (1 << state));
2316 EXPORT_SYMBOL(pci_pme_capable);
2318 static void pci_pme_list_scan(struct work_struct *work)
2320 struct pci_pme_device *pme_dev, *n;
2322 mutex_lock(&pci_pme_list_mutex);
2323 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
2324 if (pme_dev->dev->pme_poll) {
2325 struct pci_dev *bridge;
2327 bridge = pme_dev->dev->bus->self;
2329 * If bridge is in low power state, the
2330 * configuration space of subordinate devices
2331 * may be not accessible
2333 if (bridge && bridge->current_state != PCI_D0)
2336 * If the device is in D3cold it should not be
2339 if (pme_dev->dev->current_state == PCI_D3cold)
2342 pci_pme_wakeup(pme_dev->dev, NULL);
2344 list_del(&pme_dev->list);
2348 if (!list_empty(&pci_pme_list))
2349 queue_delayed_work(system_freezable_wq, &pci_pme_work,
2350 msecs_to_jiffies(PME_TIMEOUT));
2351 mutex_unlock(&pci_pme_list_mutex);
2354 static void __pci_pme_active(struct pci_dev *dev, bool enable)
2358 if (!dev->pme_support)
2361 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2362 /* Clear PME_Status by writing 1 to it and enable PME# */
2363 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
2365 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2367 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2371 * pci_pme_restore - Restore PME configuration after config space restore.
2372 * @dev: PCI device to update.
2374 void pci_pme_restore(struct pci_dev *dev)
2378 if (!dev->pme_support)
2381 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2382 if (dev->wakeup_prepared) {
2383 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2384 pmcsr &= ~PCI_PM_CTRL_PME_STATUS;
2386 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
2387 pmcsr |= PCI_PM_CTRL_PME_STATUS;
2389 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2393 * pci_pme_active - enable or disable PCI device's PME# function
2394 * @dev: PCI device to handle.
2395 * @enable: 'true' to enable PME# generation; 'false' to disable it.
2397 * The caller must verify that the device is capable of generating PME# before
2398 * calling this function with @enable equal to 'true'.
2400 void pci_pme_active(struct pci_dev *dev, bool enable)
2402 __pci_pme_active(dev, enable);
2405 * PCI (as opposed to PCIe) PME requires that the device have
2406 * its PME# line hooked up correctly. Not all hardware vendors
2407 * do this, so the PME never gets delivered and the device
2408 * remains asleep. The easiest way around this is to
2409 * periodically walk the list of suspended devices and check
2410 * whether any have their PME flag set. The assumption is that
2411 * we'll wake up often enough anyway that this won't be a huge
2412 * hit, and the power savings from the devices will still be a
2415 * Although PCIe uses in-band PME message instead of PME# line
2416 * to report PME, PME does not work for some PCIe devices in
2417 * reality. For example, there are devices that set their PME
2418 * status bits, but don't really bother to send a PME message;
2419 * there are PCI Express Root Ports that don't bother to
2420 * trigger interrupts when they receive PME messages from the
2421 * devices below. So PME poll is used for PCIe devices too.
2424 if (dev->pme_poll) {
2425 struct pci_pme_device *pme_dev;
2427 pme_dev = kmalloc(sizeof(struct pci_pme_device),
2430 pci_warn(dev, "can't enable PME#\n");
2434 mutex_lock(&pci_pme_list_mutex);
2435 list_add(&pme_dev->list, &pci_pme_list);
2436 if (list_is_singular(&pci_pme_list))
2437 queue_delayed_work(system_freezable_wq,
2439 msecs_to_jiffies(PME_TIMEOUT));
2440 mutex_unlock(&pci_pme_list_mutex);
2442 mutex_lock(&pci_pme_list_mutex);
2443 list_for_each_entry(pme_dev, &pci_pme_list, list) {
2444 if (pme_dev->dev == dev) {
2445 list_del(&pme_dev->list);
2450 mutex_unlock(&pci_pme_list_mutex);
2454 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
2456 EXPORT_SYMBOL(pci_pme_active);
2459 * __pci_enable_wake - enable PCI device as wakeup event source
2460 * @dev: PCI device affected
2461 * @state: PCI state from which device will issue wakeup events
2462 * @enable: True to enable event generation; false to disable
2464 * This enables the device as a wakeup event source, or disables it.
2465 * When such events involves platform-specific hooks, those hooks are
2466 * called automatically by this routine.
2468 * Devices with legacy power management (no standard PCI PM capabilities)
2469 * always require such platform hooks.
2472 * 0 is returned on success
2473 * -EINVAL is returned if device is not supposed to wake up the system
2474 * Error code depending on the platform is returned if both the platform and
2475 * the native mechanism fail to enable the generation of wake-up events
2477 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
2482 * Bridges that are not power-manageable directly only signal
2483 * wakeup on behalf of subordinate devices which is set up
2484 * elsewhere, so skip them. However, bridges that are
2485 * power-manageable may signal wakeup for themselves (for example,
2486 * on a hotplug event) and they need to be covered here.
2488 if (!pci_power_manageable(dev))
2491 /* Don't do the same thing twice in a row for one device. */
2492 if (!!enable == !!dev->wakeup_prepared)
2496 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
2497 * Anderson we should be doing PME# wake enable followed by ACPI wake
2498 * enable. To disable wake-up we call the platform first, for symmetry.
2505 * Enable PME signaling if the device can signal PME from
2506 * D3cold regardless of whether or not it can signal PME from
2507 * the current target state, because that will allow it to
2508 * signal PME when the hierarchy above it goes into D3cold and
2509 * the device itself ends up in D3cold as a result of that.
2511 if (pci_pme_capable(dev, state) || pci_pme_capable(dev, PCI_D3cold))
2512 pci_pme_active(dev, true);
2515 error = platform_pci_set_wakeup(dev, true);
2519 dev->wakeup_prepared = true;
2521 platform_pci_set_wakeup(dev, false);
2522 pci_pme_active(dev, false);
2523 dev->wakeup_prepared = false;
2530 * pci_enable_wake - change wakeup settings for a PCI device
2531 * @pci_dev: Target device
2532 * @state: PCI state from which device will issue wakeup events
2533 * @enable: Whether or not to enable event generation
2535 * If @enable is set, check device_may_wakeup() for the device before calling
2536 * __pci_enable_wake() for it.
2538 int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable)
2540 if (enable && !device_may_wakeup(&pci_dev->dev))
2543 return __pci_enable_wake(pci_dev, state, enable);
2545 EXPORT_SYMBOL(pci_enable_wake);
2548 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2549 * @dev: PCI device to prepare
2550 * @enable: True to enable wake-up event generation; false to disable
2552 * Many drivers want the device to wake up the system from D3_hot or D3_cold
2553 * and this function allows them to set that up cleanly - pci_enable_wake()
2554 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2555 * ordering constraints.
2557 * This function only returns error code if the device is not allowed to wake
2558 * up the system from sleep or it is not capable of generating PME# from both
2559 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2561 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2563 return pci_pme_capable(dev, PCI_D3cold) ?
2564 pci_enable_wake(dev, PCI_D3cold, enable) :
2565 pci_enable_wake(dev, PCI_D3hot, enable);
2567 EXPORT_SYMBOL(pci_wake_from_d3);
2570 * pci_target_state - find an appropriate low power state for a given PCI dev
2572 * @wakeup: Whether or not wakeup functionality will be enabled for the device.
2574 * Use underlying platform code to find a supported low power state for @dev.
2575 * If the platform can't manage @dev, return the deepest state from which it
2576 * can generate wake events, based on any available PME info.
2578 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2580 pci_power_t target_state = PCI_D3hot;
2582 if (platform_pci_power_manageable(dev)) {
2584 * Call the platform to find the target state for the device.
2586 pci_power_t state = platform_pci_choose_state(dev);
2589 case PCI_POWER_ERROR:
2594 if (pci_no_d1d2(dev))
2598 target_state = state;
2601 return target_state;
2605 target_state = PCI_D0;
2608 * If the device is in D3cold even though it's not power-manageable by
2609 * the platform, it may have been powered down by non-standard means.
2610 * Best to let it slumber.
2612 if (dev->current_state == PCI_D3cold)
2613 target_state = PCI_D3cold;
2615 if (wakeup && dev->pme_support) {
2616 pci_power_t state = target_state;
2619 * Find the deepest state from which the device can generate
2622 while (state && !(dev->pme_support & (1 << state)))
2627 else if (dev->pme_support & 1)
2631 return target_state;
2635 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2636 * into a sleep state
2637 * @dev: Device to handle.
2639 * Choose the power state appropriate for the device depending on whether
2640 * it can wake up the system and/or is power manageable by the platform
2641 * (PCI_D3hot is the default) and put the device into that state.
2643 int pci_prepare_to_sleep(struct pci_dev *dev)
2645 bool wakeup = device_may_wakeup(&dev->dev);
2646 pci_power_t target_state = pci_target_state(dev, wakeup);
2649 if (target_state == PCI_POWER_ERROR)
2653 * There are systems (for example, Intel mobile chips since Coffee
2654 * Lake) where the power drawn while suspended can be significantly
2655 * reduced by disabling PTM on PCIe root ports as this allows the
2656 * port to enter a lower-power PM state and the SoC to reach a
2657 * lower-power idle state as a whole.
2659 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2660 pci_disable_ptm(dev);
2662 pci_enable_wake(dev, target_state, wakeup);
2664 error = pci_set_power_state(dev, target_state);
2667 pci_enable_wake(dev, target_state, false);
2668 pci_restore_ptm_state(dev);
2673 EXPORT_SYMBOL(pci_prepare_to_sleep);
2676 * pci_back_from_sleep - turn PCI device on during system-wide transition
2677 * into working state
2678 * @dev: Device to handle.
2680 * Disable device's system wake-up capability and put it into D0.
2682 int pci_back_from_sleep(struct pci_dev *dev)
2684 pci_enable_wake(dev, PCI_D0, false);
2685 return pci_set_power_state(dev, PCI_D0);
2687 EXPORT_SYMBOL(pci_back_from_sleep);
2690 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2691 * @dev: PCI device being suspended.
2693 * Prepare @dev to generate wake-up events at run time and put it into a low
2696 int pci_finish_runtime_suspend(struct pci_dev *dev)
2698 pci_power_t target_state;
2701 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2702 if (target_state == PCI_POWER_ERROR)
2705 dev->runtime_d3cold = target_state == PCI_D3cold;
2708 * There are systems (for example, Intel mobile chips since Coffee
2709 * Lake) where the power drawn while suspended can be significantly
2710 * reduced by disabling PTM on PCIe root ports as this allows the
2711 * port to enter a lower-power PM state and the SoC to reach a
2712 * lower-power idle state as a whole.
2714 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2715 pci_disable_ptm(dev);
2717 __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2719 error = pci_set_power_state(dev, target_state);
2722 pci_enable_wake(dev, target_state, false);
2723 pci_restore_ptm_state(dev);
2724 dev->runtime_d3cold = false;
2731 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2732 * @dev: Device to check.
2734 * Return true if the device itself is capable of generating wake-up events
2735 * (through the platform or using the native PCIe PME) or if the device supports
2736 * PME and one of its upstream bridges can generate wake-up events.
2738 bool pci_dev_run_wake(struct pci_dev *dev)
2740 struct pci_bus *bus = dev->bus;
2742 if (!dev->pme_support)
2745 /* PME-capable in principle, but not from the target power state */
2746 if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2749 if (device_can_wakeup(&dev->dev))
2752 while (bus->parent) {
2753 struct pci_dev *bridge = bus->self;
2755 if (device_can_wakeup(&bridge->dev))
2761 /* We have reached the root bus. */
2763 return device_can_wakeup(bus->bridge);
2767 EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2770 * pci_dev_need_resume - Check if it is necessary to resume the device.
2771 * @pci_dev: Device to check.
2773 * Return 'true' if the device is not runtime-suspended or it has to be
2774 * reconfigured due to wakeup settings difference between system and runtime
2775 * suspend, or the current power state of it is not suitable for the upcoming
2776 * (system-wide) transition.
2778 bool pci_dev_need_resume(struct pci_dev *pci_dev)
2780 struct device *dev = &pci_dev->dev;
2781 pci_power_t target_state;
2783 if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev))
2786 target_state = pci_target_state(pci_dev, device_may_wakeup(dev));
2789 * If the earlier platform check has not triggered, D3cold is just power
2790 * removal on top of D3hot, so no need to resume the device in that
2793 return target_state != pci_dev->current_state &&
2794 target_state != PCI_D3cold &&
2795 pci_dev->current_state != PCI_D3hot;
2799 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2800 * @pci_dev: Device to check.
2802 * If the device is suspended and it is not configured for system wakeup,
2803 * disable PME for it to prevent it from waking up the system unnecessarily.
2805 * Note that if the device's power state is D3cold and the platform check in
2806 * pci_dev_need_resume() has not triggered, the device's configuration need not
2809 void pci_dev_adjust_pme(struct pci_dev *pci_dev)
2811 struct device *dev = &pci_dev->dev;
2813 spin_lock_irq(&dev->power.lock);
2815 if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) &&
2816 pci_dev->current_state < PCI_D3cold)
2817 __pci_pme_active(pci_dev, false);
2819 spin_unlock_irq(&dev->power.lock);
2823 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2824 * @pci_dev: Device to handle.
2826 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2827 * it might have been disabled during the prepare phase of system suspend if
2828 * the device was not configured for system wakeup.
2830 void pci_dev_complete_resume(struct pci_dev *pci_dev)
2832 struct device *dev = &pci_dev->dev;
2834 if (!pci_dev_run_wake(pci_dev))
2837 spin_lock_irq(&dev->power.lock);
2839 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2840 __pci_pme_active(pci_dev, true);
2842 spin_unlock_irq(&dev->power.lock);
2845 void pci_config_pm_runtime_get(struct pci_dev *pdev)
2847 struct device *dev = &pdev->dev;
2848 struct device *parent = dev->parent;
2851 pm_runtime_get_sync(parent);
2852 pm_runtime_get_noresume(dev);
2854 * pdev->current_state is set to PCI_D3cold during suspending,
2855 * so wait until suspending completes
2857 pm_runtime_barrier(dev);
2859 * Only need to resume devices in D3cold, because config
2860 * registers are still accessible for devices suspended but
2863 if (pdev->current_state == PCI_D3cold)
2864 pm_runtime_resume(dev);
2867 void pci_config_pm_runtime_put(struct pci_dev *pdev)
2869 struct device *dev = &pdev->dev;
2870 struct device *parent = dev->parent;
2872 pm_runtime_put(dev);
2874 pm_runtime_put_sync(parent);
2877 static const struct dmi_system_id bridge_d3_blacklist[] = {
2881 * Gigabyte X299 root port is not marked as hotplug capable
2882 * which allows Linux to power manage it. However, this
2883 * confuses the BIOS SMI handler so don't power manage root
2884 * ports on that system.
2886 .ident = "X299 DESIGNARE EX-CF",
2888 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
2889 DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
2894 * Downstream device is not accessible after putting a root port
2895 * into D3cold and back into D0 on Elo i2.
2899 DMI_MATCH(DMI_SYS_VENDOR, "Elo Touch Solutions"),
2900 DMI_MATCH(DMI_PRODUCT_NAME, "Elo i2"),
2901 DMI_MATCH(DMI_PRODUCT_VERSION, "RevB"),
2909 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2910 * @bridge: Bridge to check
2912 * This function checks if it is possible to move the bridge to D3.
2913 * Currently we only allow D3 for recent enough PCIe ports and Thunderbolt.
2915 bool pci_bridge_d3_possible(struct pci_dev *bridge)
2917 if (!pci_is_pcie(bridge))
2920 switch (pci_pcie_type(bridge)) {
2921 case PCI_EXP_TYPE_ROOT_PORT:
2922 case PCI_EXP_TYPE_UPSTREAM:
2923 case PCI_EXP_TYPE_DOWNSTREAM:
2924 if (pci_bridge_d3_disable)
2928 * Hotplug ports handled by firmware in System Management Mode
2929 * may not be put into D3 by the OS (Thunderbolt on non-Macs).
2931 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge))
2934 if (pci_bridge_d3_force)
2937 /* Even the oldest 2010 Thunderbolt controller supports D3. */
2938 if (bridge->is_thunderbolt)
2941 /* Platform might know better if the bridge supports D3 */
2942 if (platform_pci_bridge_d3(bridge))
2946 * Hotplug ports handled natively by the OS were not validated
2947 * by vendors for runtime D3 at least until 2018 because there
2948 * was no OS support.
2950 if (bridge->is_hotplug_bridge)
2953 if (dmi_check_system(bridge_d3_blacklist))
2957 * It should be safe to put PCIe ports from 2015 or newer
2960 if (dmi_get_bios_year() >= 2015)
2968 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2970 bool *d3cold_ok = data;
2972 if (/* The device needs to be allowed to go D3cold ... */
2973 dev->no_d3cold || !dev->d3cold_allowed ||
2975 /* ... and if it is wakeup capable to do so from D3cold. */
2976 (device_may_wakeup(&dev->dev) &&
2977 !pci_pme_capable(dev, PCI_D3cold)) ||
2979 /* If it is a bridge it must be allowed to go to D3. */
2980 !pci_power_manageable(dev))
2988 * pci_bridge_d3_update - Update bridge D3 capabilities
2989 * @dev: PCI device which is changed
2991 * Update upstream bridge PM capabilities accordingly depending on if the
2992 * device PM configuration was changed or the device is being removed. The
2993 * change is also propagated upstream.
2995 void pci_bridge_d3_update(struct pci_dev *dev)
2997 bool remove = !device_is_registered(&dev->dev);
2998 struct pci_dev *bridge;
2999 bool d3cold_ok = true;
3001 bridge = pci_upstream_bridge(dev);
3002 if (!bridge || !pci_bridge_d3_possible(bridge))
3006 * If D3 is currently allowed for the bridge, removing one of its
3007 * children won't change that.
3009 if (remove && bridge->bridge_d3)
3013 * If D3 is currently allowed for the bridge and a child is added or
3014 * changed, disallowance of D3 can only be caused by that child, so
3015 * we only need to check that single device, not any of its siblings.
3017 * If D3 is currently not allowed for the bridge, checking the device
3018 * first may allow us to skip checking its siblings.
3021 pci_dev_check_d3cold(dev, &d3cold_ok);
3024 * If D3 is currently not allowed for the bridge, this may be caused
3025 * either by the device being changed/removed or any of its siblings,
3026 * so we need to go through all children to find out if one of them
3027 * continues to block D3.
3029 if (d3cold_ok && !bridge->bridge_d3)
3030 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
3033 if (bridge->bridge_d3 != d3cold_ok) {
3034 bridge->bridge_d3 = d3cold_ok;
3035 /* Propagate change to upstream bridges */
3036 pci_bridge_d3_update(bridge);
3041 * pci_d3cold_enable - Enable D3cold for device
3042 * @dev: PCI device to handle
3044 * This function can be used in drivers to enable D3cold from the device
3045 * they handle. It also updates upstream PCI bridge PM capabilities
3048 void pci_d3cold_enable(struct pci_dev *dev)
3050 if (dev->no_d3cold) {
3051 dev->no_d3cold = false;
3052 pci_bridge_d3_update(dev);
3055 EXPORT_SYMBOL_GPL(pci_d3cold_enable);
3058 * pci_d3cold_disable - Disable D3cold for device
3059 * @dev: PCI device to handle
3061 * This function can be used in drivers to disable D3cold from the device
3062 * they handle. It also updates upstream PCI bridge PM capabilities
3065 void pci_d3cold_disable(struct pci_dev *dev)
3067 if (!dev->no_d3cold) {
3068 dev->no_d3cold = true;
3069 pci_bridge_d3_update(dev);
3072 EXPORT_SYMBOL_GPL(pci_d3cold_disable);
3075 * pci_pm_init - Initialize PM functions of given PCI device
3076 * @dev: PCI device to handle.
3078 void pci_pm_init(struct pci_dev *dev)
3084 pm_runtime_forbid(&dev->dev);
3085 pm_runtime_set_active(&dev->dev);
3086 pm_runtime_enable(&dev->dev);
3087 device_enable_async_suspend(&dev->dev);
3088 dev->wakeup_prepared = false;
3091 dev->pme_support = 0;
3093 /* find PCI PM capability in list */
3094 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3097 /* Check device's ability to generate PME# */
3098 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
3100 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
3101 pci_err(dev, "unsupported PM cap regs version (%u)\n",
3102 pmc & PCI_PM_CAP_VER_MASK);
3107 dev->d3hot_delay = PCI_PM_D3HOT_WAIT;
3108 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
3109 dev->bridge_d3 = pci_bridge_d3_possible(dev);
3110 dev->d3cold_allowed = true;
3112 dev->d1_support = false;
3113 dev->d2_support = false;
3114 if (!pci_no_d1d2(dev)) {
3115 if (pmc & PCI_PM_CAP_D1)
3116 dev->d1_support = true;
3117 if (pmc & PCI_PM_CAP_D2)
3118 dev->d2_support = true;
3120 if (dev->d1_support || dev->d2_support)
3121 pci_info(dev, "supports%s%s\n",
3122 dev->d1_support ? " D1" : "",
3123 dev->d2_support ? " D2" : "");
3126 pmc &= PCI_PM_CAP_PME_MASK;
3128 pci_info(dev, "PME# supported from%s%s%s%s%s\n",
3129 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
3130 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
3131 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
3132 (pmc & PCI_PM_CAP_PME_D3hot) ? " D3hot" : "",
3133 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
3134 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
3135 dev->pme_poll = true;
3137 * Make device's PM flags reflect the wake-up capability, but
3138 * let the user space enable it to wake up the system as needed.
3140 device_set_wakeup_capable(&dev->dev, true);
3141 /* Disable the PME# generation functionality */
3142 pci_pme_active(dev, false);
3145 pci_read_config_word(dev, PCI_STATUS, &status);
3146 if (status & PCI_STATUS_IMM_READY)
3150 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
3152 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
3156 case PCI_EA_P_VF_MEM:
3157 flags |= IORESOURCE_MEM;
3159 case PCI_EA_P_MEM_PREFETCH:
3160 case PCI_EA_P_VF_MEM_PREFETCH:
3161 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
3164 flags |= IORESOURCE_IO;
3173 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
3176 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
3177 return &dev->resource[bei];
3178 #ifdef CONFIG_PCI_IOV
3179 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
3180 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
3181 return &dev->resource[PCI_IOV_RESOURCES +
3182 bei - PCI_EA_BEI_VF_BAR0];
3184 else if (bei == PCI_EA_BEI_ROM)
3185 return &dev->resource[PCI_ROM_RESOURCE];
3190 /* Read an Enhanced Allocation (EA) entry */
3191 static int pci_ea_read(struct pci_dev *dev, int offset)
3193 struct resource *res;
3194 int ent_size, ent_offset = offset;
3195 resource_size_t start, end;
3196 unsigned long flags;
3197 u32 dw0, bei, base, max_offset;
3199 bool support_64 = (sizeof(resource_size_t) >= 8);
3201 pci_read_config_dword(dev, ent_offset, &dw0);
3204 /* Entry size field indicates DWORDs after 1st */
3205 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
3207 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
3210 bei = (dw0 & PCI_EA_BEI) >> 4;
3211 prop = (dw0 & PCI_EA_PP) >> 8;
3214 * If the Property is in the reserved range, try the Secondary
3217 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
3218 prop = (dw0 & PCI_EA_SP) >> 16;
3219 if (prop > PCI_EA_P_BRIDGE_IO)
3222 res = pci_ea_get_resource(dev, bei, prop);
3224 pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
3228 flags = pci_ea_flags(dev, prop);
3230 pci_err(dev, "Unsupported EA properties: %#x\n", prop);
3235 pci_read_config_dword(dev, ent_offset, &base);
3236 start = (base & PCI_EA_FIELD_MASK);
3239 /* Read MaxOffset */
3240 pci_read_config_dword(dev, ent_offset, &max_offset);
3243 /* Read Base MSBs (if 64-bit entry) */
3244 if (base & PCI_EA_IS_64) {
3247 pci_read_config_dword(dev, ent_offset, &base_upper);
3250 flags |= IORESOURCE_MEM_64;
3252 /* entry starts above 32-bit boundary, can't use */
3253 if (!support_64 && base_upper)
3257 start |= ((u64)base_upper << 32);
3260 end = start + (max_offset | 0x03);
3262 /* Read MaxOffset MSBs (if 64-bit entry) */
3263 if (max_offset & PCI_EA_IS_64) {
3264 u32 max_offset_upper;
3266 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
3269 flags |= IORESOURCE_MEM_64;
3271 /* entry too big, can't use */
3272 if (!support_64 && max_offset_upper)
3276 end += ((u64)max_offset_upper << 32);
3280 pci_err(dev, "EA Entry crosses address boundary\n");
3284 if (ent_size != ent_offset - offset) {
3285 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
3286 ent_size, ent_offset - offset);
3290 res->name = pci_name(dev);
3295 if (bei <= PCI_EA_BEI_BAR5)
3296 pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3298 else if (bei == PCI_EA_BEI_ROM)
3299 pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
3301 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
3302 pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3303 bei - PCI_EA_BEI_VF_BAR0, res, prop);
3305 pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
3309 return offset + ent_size;
3312 /* Enhanced Allocation Initialization */
3313 void pci_ea_init(struct pci_dev *dev)
3320 /* find PCI EA capability in list */
3321 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
3325 /* determine the number of entries */
3326 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
3328 num_ent &= PCI_EA_NUM_ENT_MASK;
3330 offset = ea + PCI_EA_FIRST_ENT;
3332 /* Skip DWORD 2 for type 1 functions */
3333 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
3336 /* parse each EA entry */
3337 for (i = 0; i < num_ent; ++i)
3338 offset = pci_ea_read(dev, offset);
3341 static void pci_add_saved_cap(struct pci_dev *pci_dev,
3342 struct pci_cap_saved_state *new_cap)
3344 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
3348 * _pci_add_cap_save_buffer - allocate buffer for saving given
3349 * capability registers
3350 * @dev: the PCI device
3351 * @cap: the capability to allocate the buffer for
3352 * @extended: Standard or Extended capability ID
3353 * @size: requested size of the buffer
3355 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
3356 bool extended, unsigned int size)
3359 struct pci_cap_saved_state *save_state;
3362 pos = pci_find_ext_capability(dev, cap);
3364 pos = pci_find_capability(dev, cap);
3369 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
3373 save_state->cap.cap_nr = cap;
3374 save_state->cap.cap_extended = extended;
3375 save_state->cap.size = size;
3376 pci_add_saved_cap(dev, save_state);
3381 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
3383 return _pci_add_cap_save_buffer(dev, cap, false, size);
3386 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
3388 return _pci_add_cap_save_buffer(dev, cap, true, size);
3392 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3393 * @dev: the PCI device
3395 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
3399 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
3400 PCI_EXP_SAVE_REGS * sizeof(u16));
3402 pci_err(dev, "unable to preallocate PCI Express save buffer\n");
3404 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
3406 pci_err(dev, "unable to preallocate PCI-X save buffer\n");
3408 error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
3411 pci_err(dev, "unable to allocate suspend buffer for LTR\n");
3413 pci_allocate_vc_save_buffers(dev);
3416 void pci_free_cap_save_buffers(struct pci_dev *dev)
3418 struct pci_cap_saved_state *tmp;
3419 struct hlist_node *n;
3421 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
3426 * pci_configure_ari - enable or disable ARI forwarding
3427 * @dev: the PCI device
3429 * If @dev and its upstream bridge both support ARI, enable ARI in the
3430 * bridge. Otherwise, disable ARI in the bridge.
3432 void pci_configure_ari(struct pci_dev *dev)
3435 struct pci_dev *bridge;
3437 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
3440 bridge = dev->bus->self;
3444 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3445 if (!(cap & PCI_EXP_DEVCAP2_ARI))
3448 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
3449 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
3450 PCI_EXP_DEVCTL2_ARI);
3451 bridge->ari_enabled = 1;
3453 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
3454 PCI_EXP_DEVCTL2_ARI);
3455 bridge->ari_enabled = 0;
3459 static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
3464 pos = pdev->acs_cap;
3469 * Except for egress control, capabilities are either required
3470 * or only required if controllable. Features missing from the
3471 * capability field can therefore be assumed as hard-wired enabled.
3473 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
3474 acs_flags &= (cap | PCI_ACS_EC);
3476 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
3477 return (ctrl & acs_flags) == acs_flags;
3481 * pci_acs_enabled - test ACS against required flags for a given device
3482 * @pdev: device to test
3483 * @acs_flags: required PCI ACS flags
3485 * Return true if the device supports the provided flags. Automatically
3486 * filters out flags that are not implemented on multifunction devices.
3488 * Note that this interface checks the effective ACS capabilities of the
3489 * device rather than the actual capabilities. For instance, most single
3490 * function endpoints are not required to support ACS because they have no
3491 * opportunity for peer-to-peer access. We therefore return 'true'
3492 * regardless of whether the device exposes an ACS capability. This makes
3493 * it much easier for callers of this function to ignore the actual type
3494 * or topology of the device when testing ACS support.
3496 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
3500 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
3505 * Conventional PCI and PCI-X devices never support ACS, either
3506 * effectively or actually. The shared bus topology implies that
3507 * any device on the bus can receive or snoop DMA.
3509 if (!pci_is_pcie(pdev))
3512 switch (pci_pcie_type(pdev)) {
3514 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
3515 * but since their primary interface is PCI/X, we conservatively
3516 * handle them as we would a non-PCIe device.
3518 case PCI_EXP_TYPE_PCIE_BRIDGE:
3520 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
3521 * applicable... must never implement an ACS Extended Capability...".
3522 * This seems arbitrary, but we take a conservative interpretation
3523 * of this statement.
3525 case PCI_EXP_TYPE_PCI_BRIDGE:
3526 case PCI_EXP_TYPE_RC_EC:
3529 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
3530 * implement ACS in order to indicate their peer-to-peer capabilities,
3531 * regardless of whether they are single- or multi-function devices.
3533 case PCI_EXP_TYPE_DOWNSTREAM:
3534 case PCI_EXP_TYPE_ROOT_PORT:
3535 return pci_acs_flags_enabled(pdev, acs_flags);
3537 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
3538 * implemented by the remaining PCIe types to indicate peer-to-peer
3539 * capabilities, but only when they are part of a multifunction
3540 * device. The footnote for section 6.12 indicates the specific
3541 * PCIe types included here.
3543 case PCI_EXP_TYPE_ENDPOINT:
3544 case PCI_EXP_TYPE_UPSTREAM:
3545 case PCI_EXP_TYPE_LEG_END:
3546 case PCI_EXP_TYPE_RC_END:
3547 if (!pdev->multifunction)
3550 return pci_acs_flags_enabled(pdev, acs_flags);
3554 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
3555 * to single function devices with the exception of downstream ports.
3561 * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3562 * @start: starting downstream device
3563 * @end: ending upstream device or NULL to search to the root bus
3564 * @acs_flags: required flags
3566 * Walk up a device tree from start to end testing PCI ACS support. If
3567 * any step along the way does not support the required flags, return false.
3569 bool pci_acs_path_enabled(struct pci_dev *start,
3570 struct pci_dev *end, u16 acs_flags)
3572 struct pci_dev *pdev, *parent = start;
3577 if (!pci_acs_enabled(pdev, acs_flags))
3580 if (pci_is_root_bus(pdev->bus))
3581 return (end == NULL);
3583 parent = pdev->bus->self;
3584 } while (pdev != end);
3590 * pci_acs_init - Initialize ACS if hardware supports it
3591 * @dev: the PCI device
3593 void pci_acs_init(struct pci_dev *dev)
3595 dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3598 * Attempt to enable ACS regardless of capability because some Root
3599 * Ports (e.g. those quirked with *_intel_pch_acs_*) do not have
3600 * the standard ACS capability but still support ACS via those
3603 pci_enable_acs(dev);
3607 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3611 * Helper to find the position of the ctrl register for a BAR.
3612 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3613 * Returns -ENOENT if no ctrl register for the BAR could be found.
3615 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar)
3617 unsigned int pos, nbars, i;
3620 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR);
3624 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3625 nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >>
3626 PCI_REBAR_CTRL_NBAR_SHIFT;
3628 for (i = 0; i < nbars; i++, pos += 8) {
3631 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3632 bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX;
3641 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3643 * @bar: BAR to query
3645 * Get the possible sizes of a resizable BAR as bitmask defined in the spec
3646 * (bit 0=1MB, bit 19=512GB). Returns 0 if BAR isn't resizable.
3648 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar)
3653 pos = pci_rebar_find_pos(pdev, bar);
3657 pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap);
3658 cap &= PCI_REBAR_CAP_SIZES;
3660 /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */
3661 if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f &&
3662 bar == 0 && cap == 0x7000)
3667 EXPORT_SYMBOL(pci_rebar_get_possible_sizes);
3670 * pci_rebar_get_current_size - get the current size of a BAR
3672 * @bar: BAR to set size to
3674 * Read the size of a BAR from the resizable BAR config.
3675 * Returns size if found or negative error code.
3677 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar)
3682 pos = pci_rebar_find_pos(pdev, bar);
3686 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3687 return (ctrl & PCI_REBAR_CTRL_BAR_SIZE) >> PCI_REBAR_CTRL_BAR_SHIFT;
3691 * pci_rebar_set_size - set a new size for a BAR
3693 * @bar: BAR to set size to
3694 * @size: new size as defined in the spec (0=1MB, 19=512GB)
3696 * Set the new size of a BAR as defined in the spec.
3697 * Returns zero if resizing was successful, error code otherwise.
3699 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size)
3704 pos = pci_rebar_find_pos(pdev, bar);
3708 pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl);
3709 ctrl &= ~PCI_REBAR_CTRL_BAR_SIZE;
3710 ctrl |= size << PCI_REBAR_CTRL_BAR_SHIFT;
3711 pci_write_config_dword(pdev, pos + PCI_REBAR_CTRL, ctrl);
3716 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3717 * @dev: the PCI device
3718 * @cap_mask: mask of desired AtomicOp sizes, including one or more of:
3719 * PCI_EXP_DEVCAP2_ATOMIC_COMP32
3720 * PCI_EXP_DEVCAP2_ATOMIC_COMP64
3721 * PCI_EXP_DEVCAP2_ATOMIC_COMP128
3723 * Return 0 if all upstream bridges support AtomicOp routing, egress
3724 * blocking is disabled on all upstream ports, and the root port supports
3725 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3726 * AtomicOp completion), or negative otherwise.
3728 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3730 struct pci_bus *bus = dev->bus;
3731 struct pci_dev *bridge;
3735 * Per PCIe r5.0, sec 9.3.5.10, the AtomicOp Requester Enable bit
3736 * in Device Control 2 is reserved in VFs and the PF value applies
3737 * to all associated VFs.
3742 if (!pci_is_pcie(dev))
3746 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be
3747 * AtomicOp requesters. For now, we only support endpoints as
3748 * requesters and root ports as completers. No endpoints as
3749 * completers, and no peer-to-peer.
3752 switch (pci_pcie_type(dev)) {
3753 case PCI_EXP_TYPE_ENDPOINT:
3754 case PCI_EXP_TYPE_LEG_END:
3755 case PCI_EXP_TYPE_RC_END:
3761 while (bus->parent) {
3764 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
3766 switch (pci_pcie_type(bridge)) {
3767 /* Ensure switch ports support AtomicOp routing */
3768 case PCI_EXP_TYPE_UPSTREAM:
3769 case PCI_EXP_TYPE_DOWNSTREAM:
3770 if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
3774 /* Ensure root port supports all the sizes we care about */
3775 case PCI_EXP_TYPE_ROOT_PORT:
3776 if ((cap & cap_mask) != cap_mask)
3781 /* Ensure upstream ports don't block AtomicOps on egress */
3782 if (pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM) {
3783 pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2,
3785 if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK)
3792 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3793 PCI_EXP_DEVCTL2_ATOMIC_REQ);
3796 EXPORT_SYMBOL(pci_enable_atomic_ops_to_root);
3799 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
3800 * @dev: the PCI device
3801 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
3803 * Perform INTx swizzling for a device behind one level of bridge. This is
3804 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
3805 * behind bridges on add-in cards. For devices with ARI enabled, the slot
3806 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
3807 * the PCI Express Base Specification, Revision 2.1)
3809 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3813 if (pci_ari_enabled(dev->bus))
3816 slot = PCI_SLOT(dev->devfn);
3818 return (((pin - 1) + slot) % 4) + 1;
3821 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3829 while (!pci_is_root_bus(dev->bus)) {
3830 pin = pci_swizzle_interrupt_pin(dev, pin);
3831 dev = dev->bus->self;
3838 * pci_common_swizzle - swizzle INTx all the way to root bridge
3839 * @dev: the PCI device
3840 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
3842 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
3843 * bridges all the way up to a PCI root bus.
3845 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3849 while (!pci_is_root_bus(dev->bus)) {
3850 pin = pci_swizzle_interrupt_pin(dev, pin);
3851 dev = dev->bus->self;
3854 return PCI_SLOT(dev->devfn);
3856 EXPORT_SYMBOL_GPL(pci_common_swizzle);
3859 * pci_release_region - Release a PCI bar
3860 * @pdev: PCI device whose resources were previously reserved by
3861 * pci_request_region()
3862 * @bar: BAR to release
3864 * Releases the PCI I/O and memory resources previously reserved by a
3865 * successful call to pci_request_region(). Call this function only
3866 * after all use of the PCI regions has ceased.
3868 void pci_release_region(struct pci_dev *pdev, int bar)
3870 struct pci_devres *dr;
3872 if (pci_resource_len(pdev, bar) == 0)
3874 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3875 release_region(pci_resource_start(pdev, bar),
3876 pci_resource_len(pdev, bar));
3877 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3878 release_mem_region(pci_resource_start(pdev, bar),
3879 pci_resource_len(pdev, bar));
3881 dr = find_pci_dr(pdev);
3883 dr->region_mask &= ~(1 << bar);
3885 EXPORT_SYMBOL(pci_release_region);
3888 * __pci_request_region - Reserved PCI I/O and memory resource
3889 * @pdev: PCI device whose resources are to be reserved
3890 * @bar: BAR to be reserved
3891 * @res_name: Name to be associated with resource.
3892 * @exclusive: whether the region access is exclusive or not
3894 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3895 * being reserved by owner @res_name. Do not access any
3896 * address inside the PCI regions unless this call returns
3899 * If @exclusive is set, then the region is marked so that userspace
3900 * is explicitly not allowed to map the resource via /dev/mem or
3901 * sysfs MMIO access.
3903 * Returns 0 on success, or %EBUSY on error. A warning
3904 * message is also printed on failure.
3906 static int __pci_request_region(struct pci_dev *pdev, int bar,
3907 const char *res_name, int exclusive)
3909 struct pci_devres *dr;
3911 if (pci_resource_len(pdev, bar) == 0)
3914 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3915 if (!request_region(pci_resource_start(pdev, bar),
3916 pci_resource_len(pdev, bar), res_name))
3918 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
3919 if (!__request_mem_region(pci_resource_start(pdev, bar),
3920 pci_resource_len(pdev, bar), res_name,
3925 dr = find_pci_dr(pdev);
3927 dr->region_mask |= 1 << bar;
3932 pci_warn(pdev, "BAR %d: can't reserve %pR\n", bar,
3933 &pdev->resource[bar]);
3938 * pci_request_region - Reserve PCI I/O and memory resource
3939 * @pdev: PCI device whose resources are to be reserved
3940 * @bar: BAR to be reserved
3941 * @res_name: Name to be associated with resource
3943 * Mark the PCI region associated with PCI device @pdev BAR @bar as
3944 * being reserved by owner @res_name. Do not access any
3945 * address inside the PCI regions unless this call returns
3948 * Returns 0 on success, or %EBUSY on error. A warning
3949 * message is also printed on failure.
3951 int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3953 return __pci_request_region(pdev, bar, res_name, 0);
3955 EXPORT_SYMBOL(pci_request_region);
3958 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3959 * @pdev: PCI device whose resources were previously reserved
3960 * @bars: Bitmask of BARs to be released
3962 * Release selected PCI I/O and memory resources previously reserved.
3963 * Call this function only after all use of the PCI regions has ceased.
3965 void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3969 for (i = 0; i < PCI_STD_NUM_BARS; i++)
3970 if (bars & (1 << i))
3971 pci_release_region(pdev, i);
3973 EXPORT_SYMBOL(pci_release_selected_regions);
3975 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
3976 const char *res_name, int excl)
3980 for (i = 0; i < PCI_STD_NUM_BARS; i++)
3981 if (bars & (1 << i))
3982 if (__pci_request_region(pdev, i, res_name, excl))
3988 if (bars & (1 << i))
3989 pci_release_region(pdev, i);
3996 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3997 * @pdev: PCI device whose resources are to be reserved
3998 * @bars: Bitmask of BARs to be requested
3999 * @res_name: Name to be associated with resource
4001 int pci_request_selected_regions(struct pci_dev *pdev, int bars,
4002 const char *res_name)
4004 return __pci_request_selected_regions(pdev, bars, res_name, 0);
4006 EXPORT_SYMBOL(pci_request_selected_regions);
4008 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
4009 const char *res_name)
4011 return __pci_request_selected_regions(pdev, bars, res_name,
4012 IORESOURCE_EXCLUSIVE);
4014 EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
4017 * pci_release_regions - Release reserved PCI I/O and memory resources
4018 * @pdev: PCI device whose resources were previously reserved by
4019 * pci_request_regions()
4021 * Releases all PCI I/O and memory resources previously reserved by a
4022 * successful call to pci_request_regions(). Call this function only
4023 * after all use of the PCI regions has ceased.
4026 void pci_release_regions(struct pci_dev *pdev)
4028 pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1);
4030 EXPORT_SYMBOL(pci_release_regions);
4033 * pci_request_regions - Reserve PCI I/O and memory resources
4034 * @pdev: PCI device whose resources are to be reserved
4035 * @res_name: Name to be associated with resource.
4037 * Mark all PCI regions associated with PCI device @pdev as
4038 * being reserved by owner @res_name. Do not access any
4039 * address inside the PCI regions unless this call returns
4042 * Returns 0 on success, or %EBUSY on error. A warning
4043 * message is also printed on failure.
4045 int pci_request_regions(struct pci_dev *pdev, const char *res_name)
4047 return pci_request_selected_regions(pdev,
4048 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4050 EXPORT_SYMBOL(pci_request_regions);
4053 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4054 * @pdev: PCI device whose resources are to be reserved
4055 * @res_name: Name to be associated with resource.
4057 * Mark all PCI regions associated with PCI device @pdev as being reserved
4058 * by owner @res_name. Do not access any address inside the PCI regions
4059 * unless this call returns successfully.
4061 * pci_request_regions_exclusive() will mark the region so that /dev/mem
4062 * and the sysfs MMIO access will not be allowed.
4064 * Returns 0 on success, or %EBUSY on error. A warning message is also
4065 * printed on failure.
4067 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
4069 return pci_request_selected_regions_exclusive(pdev,
4070 ((1 << PCI_STD_NUM_BARS) - 1), res_name);
4072 EXPORT_SYMBOL(pci_request_regions_exclusive);
4075 * Record the PCI IO range (expressed as CPU physical address + size).
4076 * Return a negative value if an error has occurred, zero otherwise
4078 int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
4079 resource_size_t size)
4083 struct logic_pio_hwaddr *range;
4085 if (!size || addr + size < addr)
4088 range = kzalloc(sizeof(*range), GFP_ATOMIC);
4092 range->fwnode = fwnode;
4094 range->hw_start = addr;
4095 range->flags = LOGIC_PIO_CPU_MMIO;
4097 ret = logic_pio_register_range(range);
4101 /* Ignore duplicates due to deferred probing */
4109 phys_addr_t pci_pio_to_address(unsigned long pio)
4111 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
4114 if (pio >= MMIO_UPPER_LIMIT)
4117 address = logic_pio_to_hwaddr(pio);
4122 EXPORT_SYMBOL_GPL(pci_pio_to_address);
4124 unsigned long __weak pci_address_to_pio(phys_addr_t address)
4127 return logic_pio_trans_cpuaddr(address);
4129 if (address > IO_SPACE_LIMIT)
4130 return (unsigned long)-1;
4132 return (unsigned long) address;
4137 * pci_remap_iospace - Remap the memory mapped I/O space
4138 * @res: Resource describing the I/O space
4139 * @phys_addr: physical address of range to be mapped
4141 * Remap the memory mapped I/O space described by the @res and the CPU
4142 * physical address @phys_addr into virtual address space. Only
4143 * architectures that have memory mapped IO functions defined (and the
4144 * PCI_IOBASE value defined) should call this function.
4146 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
4148 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4149 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4151 if (!(res->flags & IORESOURCE_IO))
4154 if (res->end > IO_SPACE_LIMIT)
4157 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
4158 pgprot_device(PAGE_KERNEL));
4161 * This architecture does not have memory mapped I/O space,
4162 * so this function should never be called
4164 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
4168 EXPORT_SYMBOL(pci_remap_iospace);
4171 * pci_unmap_iospace - Unmap the memory mapped I/O space
4172 * @res: resource to be unmapped
4174 * Unmap the CPU virtual address @res from virtual address space. Only
4175 * architectures that have memory mapped IO functions defined (and the
4176 * PCI_IOBASE value defined) should call this function.
4178 void pci_unmap_iospace(struct resource *res)
4180 #if defined(PCI_IOBASE) && defined(CONFIG_MMU)
4181 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
4183 vunmap_range(vaddr, vaddr + resource_size(res));
4186 EXPORT_SYMBOL(pci_unmap_iospace);
4188 static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
4190 struct resource **res = ptr;
4192 pci_unmap_iospace(*res);
4196 * devm_pci_remap_iospace - Managed pci_remap_iospace()
4197 * @dev: Generic device to remap IO address for
4198 * @res: Resource describing the I/O space
4199 * @phys_addr: physical address of range to be mapped
4201 * Managed pci_remap_iospace(). Map is automatically unmapped on driver
4204 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
4205 phys_addr_t phys_addr)
4207 const struct resource **ptr;
4210 ptr = devres_alloc(devm_pci_unmap_iospace, sizeof(*ptr), GFP_KERNEL);
4214 error = pci_remap_iospace(res, phys_addr);
4219 devres_add(dev, ptr);
4224 EXPORT_SYMBOL(devm_pci_remap_iospace);
4227 * devm_pci_remap_cfgspace - Managed pci_remap_cfgspace()
4228 * @dev: Generic device to remap IO address for
4229 * @offset: Resource address to map
4230 * @size: Size of map
4232 * Managed pci_remap_cfgspace(). Map is automatically unmapped on driver
4235 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
4236 resource_size_t offset,
4237 resource_size_t size)
4239 void __iomem **ptr, *addr;
4241 ptr = devres_alloc(devm_ioremap_release, sizeof(*ptr), GFP_KERNEL);
4245 addr = pci_remap_cfgspace(offset, size);
4248 devres_add(dev, ptr);
4254 EXPORT_SYMBOL(devm_pci_remap_cfgspace);
4257 * devm_pci_remap_cfg_resource - check, request region and ioremap cfg resource
4258 * @dev: generic device to handle the resource for
4259 * @res: configuration space resource to be handled
4261 * Checks that a resource is a valid memory region, requests the memory
4262 * region and ioremaps with pci_remap_cfgspace() API that ensures the
4263 * proper PCI configuration space memory attributes are guaranteed.
4265 * All operations are managed and will be undone on driver detach.
4267 * Returns a pointer to the remapped memory or an ERR_PTR() encoded error code
4268 * on failure. Usage example::
4270 * res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4271 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4273 * return PTR_ERR(base);
4275 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
4276 struct resource *res)
4278 resource_size_t size;
4280 void __iomem *dest_ptr;
4284 if (!res || resource_type(res) != IORESOURCE_MEM) {
4285 dev_err(dev, "invalid resource\n");
4286 return IOMEM_ERR_PTR(-EINVAL);
4289 size = resource_size(res);
4292 name = devm_kasprintf(dev, GFP_KERNEL, "%s %s", dev_name(dev),
4295 name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
4297 return IOMEM_ERR_PTR(-ENOMEM);
4299 if (!devm_request_mem_region(dev, res->start, size, name)) {
4300 dev_err(dev, "can't request region for resource %pR\n", res);
4301 return IOMEM_ERR_PTR(-EBUSY);
4304 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
4306 dev_err(dev, "ioremap failed for resource %pR\n", res);
4307 devm_release_mem_region(dev, res->start, size);
4308 dest_ptr = IOMEM_ERR_PTR(-ENOMEM);
4313 EXPORT_SYMBOL(devm_pci_remap_cfg_resource);
4315 static void __pci_set_master(struct pci_dev *dev, bool enable)
4319 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
4321 cmd = old_cmd | PCI_COMMAND_MASTER;
4323 cmd = old_cmd & ~PCI_COMMAND_MASTER;
4324 if (cmd != old_cmd) {
4325 pci_dbg(dev, "%s bus mastering\n",
4326 enable ? "enabling" : "disabling");
4327 pci_write_config_word(dev, PCI_COMMAND, cmd);
4329 dev->is_busmaster = enable;
4333 * pcibios_setup - process "pci=" kernel boot arguments
4334 * @str: string used to pass in "pci=" kernel boot arguments
4336 * Process kernel boot arguments. This is the default implementation.
4337 * Architecture specific implementations can override this as necessary.
4339 char * __weak __init pcibios_setup(char *str)
4345 * pcibios_set_master - enable PCI bus-mastering for device dev
4346 * @dev: the PCI device to enable
4348 * Enables PCI bus-mastering for the device. This is the default
4349 * implementation. Architecture specific implementations can override
4350 * this if necessary.
4352 void __weak pcibios_set_master(struct pci_dev *dev)
4356 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
4357 if (pci_is_pcie(dev))
4360 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
4362 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
4363 else if (lat > pcibios_max_latency)
4364 lat = pcibios_max_latency;
4368 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
4372 * pci_set_master - enables bus-mastering for device dev
4373 * @dev: the PCI device to enable
4375 * Enables bus-mastering on the device and calls pcibios_set_master()
4376 * to do the needed arch specific settings.
4378 void pci_set_master(struct pci_dev *dev)
4380 __pci_set_master(dev, true);
4381 pcibios_set_master(dev);
4383 EXPORT_SYMBOL(pci_set_master);
4386 * pci_clear_master - disables bus-mastering for device dev
4387 * @dev: the PCI device to disable
4389 void pci_clear_master(struct pci_dev *dev)
4391 __pci_set_master(dev, false);
4393 EXPORT_SYMBOL(pci_clear_master);
4396 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4397 * @dev: the PCI device for which MWI is to be enabled
4399 * Helper function for pci_set_mwi.
4400 * Originally copied from drivers/net/acenic.c.
4401 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4403 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4405 int pci_set_cacheline_size(struct pci_dev *dev)
4409 if (!pci_cache_line_size)
4412 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
4413 equal to or multiple of the right value. */
4414 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4415 if (cacheline_size >= pci_cache_line_size &&
4416 (cacheline_size % pci_cache_line_size) == 0)
4419 /* Write the correct value. */
4420 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
4422 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4423 if (cacheline_size == pci_cache_line_size)
4426 pci_dbg(dev, "cache line size of %d is not supported\n",
4427 pci_cache_line_size << 2);
4431 EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
4434 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4435 * @dev: the PCI device for which MWI is enabled
4437 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4439 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4441 int pci_set_mwi(struct pci_dev *dev)
4443 #ifdef PCI_DISABLE_MWI
4449 rc = pci_set_cacheline_size(dev);
4453 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4454 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
4455 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
4456 cmd |= PCI_COMMAND_INVALIDATE;
4457 pci_write_config_word(dev, PCI_COMMAND, cmd);
4462 EXPORT_SYMBOL(pci_set_mwi);
4465 * pcim_set_mwi - a device-managed pci_set_mwi()
4466 * @dev: the PCI device for which MWI is enabled
4468 * Managed pci_set_mwi().
4470 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4472 int pcim_set_mwi(struct pci_dev *dev)
4474 struct pci_devres *dr;
4476 dr = find_pci_dr(dev);
4481 return pci_set_mwi(dev);
4483 EXPORT_SYMBOL(pcim_set_mwi);
4486 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4487 * @dev: the PCI device for which MWI is enabled
4489 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4490 * Callers are not required to check the return value.
4492 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4494 int pci_try_set_mwi(struct pci_dev *dev)
4496 #ifdef PCI_DISABLE_MWI
4499 return pci_set_mwi(dev);
4502 EXPORT_SYMBOL(pci_try_set_mwi);
4505 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4506 * @dev: the PCI device to disable
4508 * Disables PCI Memory-Write-Invalidate transaction on the device
4510 void pci_clear_mwi(struct pci_dev *dev)
4512 #ifndef PCI_DISABLE_MWI
4515 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4516 if (cmd & PCI_COMMAND_INVALIDATE) {
4517 cmd &= ~PCI_COMMAND_INVALIDATE;
4518 pci_write_config_word(dev, PCI_COMMAND, cmd);
4522 EXPORT_SYMBOL(pci_clear_mwi);
4525 * pci_disable_parity - disable parity checking for device
4526 * @dev: the PCI device to operate on
4528 * Disable parity checking for device @dev
4530 void pci_disable_parity(struct pci_dev *dev)
4534 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4535 if (cmd & PCI_COMMAND_PARITY) {
4536 cmd &= ~PCI_COMMAND_PARITY;
4537 pci_write_config_word(dev, PCI_COMMAND, cmd);
4542 * pci_intx - enables/disables PCI INTx for device dev
4543 * @pdev: the PCI device to operate on
4544 * @enable: boolean: whether to enable or disable PCI INTx
4546 * Enables/disables PCI INTx for device @pdev
4548 void pci_intx(struct pci_dev *pdev, int enable)
4550 u16 pci_command, new;
4552 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
4555 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
4557 new = pci_command | PCI_COMMAND_INTX_DISABLE;
4559 if (new != pci_command) {
4560 struct pci_devres *dr;
4562 pci_write_config_word(pdev, PCI_COMMAND, new);
4564 dr = find_pci_dr(pdev);
4565 if (dr && !dr->restore_intx) {
4566 dr->restore_intx = 1;
4567 dr->orig_intx = !enable;
4571 EXPORT_SYMBOL_GPL(pci_intx);
4573 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
4575 struct pci_bus *bus = dev->bus;
4576 bool mask_updated = true;
4577 u32 cmd_status_dword;
4578 u16 origcmd, newcmd;
4579 unsigned long flags;
4583 * We do a single dword read to retrieve both command and status.
4584 * Document assumptions that make this possible.
4586 BUILD_BUG_ON(PCI_COMMAND % 4);
4587 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
4589 raw_spin_lock_irqsave(&pci_lock, flags);
4591 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4593 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
4596 * Check interrupt status register to see whether our device
4597 * triggered the interrupt (when masking) or the next IRQ is
4598 * already pending (when unmasking).
4600 if (mask != irq_pending) {
4601 mask_updated = false;
4605 origcmd = cmd_status_dword;
4606 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
4608 newcmd |= PCI_COMMAND_INTX_DISABLE;
4609 if (newcmd != origcmd)
4610 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4613 raw_spin_unlock_irqrestore(&pci_lock, flags);
4615 return mask_updated;
4619 * pci_check_and_mask_intx - mask INTx on pending interrupt
4620 * @dev: the PCI device to operate on
4622 * Check if the device dev has its INTx line asserted, mask it and return
4623 * true in that case. False is returned if no interrupt was pending.
4625 bool pci_check_and_mask_intx(struct pci_dev *dev)
4627 return pci_check_and_set_intx_mask(dev, true);
4629 EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
4632 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
4633 * @dev: the PCI device to operate on
4635 * Check if the device dev has its INTx line asserted, unmask it if not and
4636 * return true. False is returned and the mask remains active if there was
4637 * still an interrupt pending.
4639 bool pci_check_and_unmask_intx(struct pci_dev *dev)
4641 return pci_check_and_set_intx_mask(dev, false);
4643 EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
4646 * pci_wait_for_pending_transaction - wait for pending transaction
4647 * @dev: the PCI device to operate on
4649 * Return 0 if transaction is pending 1 otherwise.
4651 int pci_wait_for_pending_transaction(struct pci_dev *dev)
4653 if (!pci_is_pcie(dev))
4656 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4657 PCI_EXP_DEVSTA_TRPND);
4659 EXPORT_SYMBOL(pci_wait_for_pending_transaction);
4662 * pcie_flr - initiate a PCIe function level reset
4663 * @dev: device to reset
4665 * Initiate a function level reset unconditionally on @dev without
4666 * checking any flags and DEVCAP
4668 int pcie_flr(struct pci_dev *dev)
4670 if (!pci_wait_for_pending_transaction(dev))
4671 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4673 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4679 * Per PCIe r4.0, sec 6.6.2, a device must complete an FLR within
4680 * 100ms, but may silently discard requests while the FLR is in
4681 * progress. Wait 100ms before trying to access the device.
4685 return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4687 EXPORT_SYMBOL_GPL(pcie_flr);
4690 * pcie_reset_flr - initiate a PCIe function level reset
4691 * @dev: device to reset
4692 * @probe: if true, return 0 if device can be reset this way
4694 * Initiate a function level reset on @dev.
4696 int pcie_reset_flr(struct pci_dev *dev, bool probe)
4698 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4701 if (!(dev->devcap & PCI_EXP_DEVCAP_FLR))
4707 return pcie_flr(dev);
4709 EXPORT_SYMBOL_GPL(pcie_reset_flr);
4711 static int pci_af_flr(struct pci_dev *dev, bool probe)
4716 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4720 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4723 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4724 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
4731 * Wait for Transaction Pending bit to clear. A word-aligned test
4732 * is used, so we use the control offset rather than status and shift
4733 * the test bit to match.
4735 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4736 PCI_AF_STATUS_TP << 8))
4737 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4739 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4745 * Per Advanced Capabilities for Conventional PCI ECN, 13 April 2006,
4746 * updated 27 July 2006; a device must complete an FLR within
4747 * 100ms, but may silently discard requests while the FLR is in
4748 * progress. Wait 100ms before trying to access the device.
4752 return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4756 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4757 * @dev: Device to reset.
4758 * @probe: if true, return 0 if the device can be reset this way.
4760 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4761 * unset, it will be reinitialized internally when going from PCI_D3hot to
4762 * PCI_D0. If that's the case and the device is not in a low-power state
4763 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4765 * NOTE: This causes the caller to sleep for twice the device power transition
4766 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4767 * by default (i.e. unless the @dev's d3hot_delay field has a different value).
4768 * Moreover, only devices in D0 can be reset by this function.
4770 static int pci_pm_reset(struct pci_dev *dev, bool probe)
4774 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4777 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4778 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
4784 if (dev->current_state != PCI_D0)
4787 csr &= ~PCI_PM_CTRL_STATE_MASK;
4789 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4790 pci_dev_d3_sleep(dev);
4792 csr &= ~PCI_PM_CTRL_STATE_MASK;
4794 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4795 pci_dev_d3_sleep(dev);
4797 return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS);
4801 * pcie_wait_for_link_delay - Wait until link is active or inactive
4802 * @pdev: Bridge device
4803 * @active: waiting for active or inactive?
4804 * @delay: Delay to wait after link has become active (in ms)
4806 * Use this to wait till link becomes active or inactive.
4808 static bool pcie_wait_for_link_delay(struct pci_dev *pdev, bool active,
4816 * Some controllers might not implement link active reporting. In this
4817 * case, we wait for 1000 ms + any delay requested by the caller.
4819 if (!pdev->link_active_reporting) {
4820 msleep(timeout + delay);
4825 * PCIe r4.0 sec 6.6.1, a component must enter LTSSM Detect within 20ms,
4826 * after which we should expect an link active if the reset was
4827 * successful. If so, software must wait a minimum 100ms before sending
4828 * configuration requests to devices downstream this port.
4830 * If the link fails to activate, either the device was physically
4831 * removed or the link is permanently failed.
4836 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &lnk_status);
4837 ret = !!(lnk_status & PCI_EXP_LNKSTA_DLLLA);
4848 return ret == active;
4852 * pcie_wait_for_link - Wait until link is active or inactive
4853 * @pdev: Bridge device
4854 * @active: waiting for active or inactive?
4856 * Use this to wait till link becomes active or inactive.
4858 bool pcie_wait_for_link(struct pci_dev *pdev, bool active)
4860 return pcie_wait_for_link_delay(pdev, active, 100);
4864 * Find maximum D3cold delay required by all the devices on the bus. The
4865 * spec says 100 ms, but firmware can lower it and we allow drivers to
4866 * increase it as well.
4868 * Called with @pci_bus_sem locked for reading.
4870 static int pci_bus_max_d3cold_delay(const struct pci_bus *bus)
4872 const struct pci_dev *pdev;
4873 int min_delay = 100;
4876 list_for_each_entry(pdev, &bus->devices, bus_list) {
4877 if (pdev->d3cold_delay < min_delay)
4878 min_delay = pdev->d3cold_delay;
4879 if (pdev->d3cold_delay > max_delay)
4880 max_delay = pdev->d3cold_delay;
4883 return max(min_delay, max_delay);
4887 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
4890 * Handle necessary delays before access to the devices on the secondary
4891 * side of the bridge are permitted after D3cold to D0 transition.
4893 * For PCIe this means the delays in PCIe 5.0 section 6.6.1. For
4894 * conventional PCI it means Tpvrh + Trhfa specified in PCI 3.0 section
4897 void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev)
4899 struct pci_dev *child;
4902 if (pci_dev_is_disconnected(dev))
4905 if (!pci_is_bridge(dev) || !dev->bridge_d3)
4908 down_read(&pci_bus_sem);
4911 * We only deal with devices that are present currently on the bus.
4912 * For any hot-added devices the access delay is handled in pciehp
4913 * board_added(). In case of ACPI hotplug the firmware is expected
4914 * to configure the devices before OS is notified.
4916 if (!dev->subordinate || list_empty(&dev->subordinate->devices)) {
4917 up_read(&pci_bus_sem);
4921 /* Take d3cold_delay requirements into account */
4922 delay = pci_bus_max_d3cold_delay(dev->subordinate);
4924 up_read(&pci_bus_sem);
4928 child = list_first_entry(&dev->subordinate->devices, struct pci_dev,
4930 up_read(&pci_bus_sem);
4933 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before
4934 * accessing the device after reset (that is 1000 ms + 100 ms). In
4935 * practice this should not be needed because we don't do power
4936 * management for them (see pci_bridge_d3_possible()).
4938 if (!pci_is_pcie(dev)) {
4939 pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
4940 msleep(1000 + delay);
4945 * For PCIe downstream and root ports that do not support speeds
4946 * greater than 5 GT/s need to wait minimum 100 ms. For higher
4947 * speeds (gen3) we need to wait first for the data link layer to
4950 * However, 100 ms is the minimum and the PCIe spec says the
4951 * software must allow at least 1s before it can determine that the
4952 * device that did not respond is a broken device. There is
4953 * evidence that 100 ms is not always enough, for example certain
4954 * Titan Ridge xHCI controller does not always respond to
4955 * configuration requests if we only wait for 100 ms (see
4956 * https://bugzilla.kernel.org/show_bug.cgi?id=203885).
4958 * Therefore we wait for 100 ms and check for the device presence.
4959 * If it is still not present give it an additional 100 ms.
4961 if (!pcie_downstream_port(dev))
4964 if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {
4965 pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
4968 pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",
4970 if (!pcie_wait_for_link_delay(dev, true, delay)) {
4971 /* Did not train, no need to wait any further */
4972 pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n");
4977 if (!pci_device_is_present(child)) {
4978 pci_dbg(child, "waiting additional %d ms to become accessible\n", delay);
4983 void pci_reset_secondary_bus(struct pci_dev *dev)
4987 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
4988 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
4989 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4992 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
4993 * this to 2ms to ensure that we meet the minimum requirement.
4997 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
4998 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
5001 * Trhfa for conventional PCI is 2^25 clock cycles.
5002 * Assuming a minimum 33MHz clock this results in a 1s
5003 * delay before we can consider subordinate devices to
5004 * be re-initialized. PCIe has some ways to shorten this,
5005 * but we don't make use of them yet.
5010 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
5012 pci_reset_secondary_bus(dev);
5016 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
5017 * @dev: Bridge device
5019 * Use the bridge control register to assert reset on the secondary bus.
5020 * Devices on the secondary bus are left in power-on state.
5022 int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
5024 pcibios_reset_secondary_bus(dev);
5026 return pci_dev_wait(dev, "bus reset", PCIE_RESET_READY_POLL_MS);
5028 EXPORT_SYMBOL_GPL(pci_bridge_secondary_bus_reset);
5030 static int pci_parent_bus_reset(struct pci_dev *dev, bool probe)
5032 struct pci_dev *pdev;
5034 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
5035 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5038 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
5045 return pci_bridge_secondary_bus_reset(dev->bus->self);
5048 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, bool probe)
5052 if (!hotplug || !try_module_get(hotplug->owner))
5055 if (hotplug->ops->reset_slot)
5056 rc = hotplug->ops->reset_slot(hotplug, probe);
5058 module_put(hotplug->owner);
5063 static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe)
5065 if (dev->multifunction || dev->subordinate || !dev->slot ||
5066 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
5069 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
5072 static int pci_reset_bus_function(struct pci_dev *dev, bool probe)
5076 rc = pci_dev_reset_slot_function(dev, probe);
5079 return pci_parent_bus_reset(dev, probe);
5082 static void pci_dev_lock(struct pci_dev *dev)
5084 /* block PM suspend, driver probe, etc. */
5085 device_lock(&dev->dev);
5086 pci_cfg_access_lock(dev);
5089 /* Return 1 on successful lock, 0 on contention */
5090 int pci_dev_trylock(struct pci_dev *dev)
5092 if (device_trylock(&dev->dev)) {
5093 if (pci_cfg_access_trylock(dev))
5095 device_unlock(&dev->dev);
5100 EXPORT_SYMBOL_GPL(pci_dev_trylock);
5102 void pci_dev_unlock(struct pci_dev *dev)
5104 pci_cfg_access_unlock(dev);
5105 device_unlock(&dev->dev);
5107 EXPORT_SYMBOL_GPL(pci_dev_unlock);
5109 static void pci_dev_save_and_disable(struct pci_dev *dev)
5111 const struct pci_error_handlers *err_handler =
5112 dev->driver ? dev->driver->err_handler : NULL;
5115 * dev->driver->err_handler->reset_prepare() is protected against
5116 * races with ->remove() by the device lock, which must be held by
5119 if (err_handler && err_handler->reset_prepare)
5120 err_handler->reset_prepare(dev);
5123 * Wake-up device prior to save. PM registers default to D0 after
5124 * reset and a simple register restore doesn't reliably return
5125 * to a non-D0 state anyway.
5127 pci_set_power_state(dev, PCI_D0);
5129 pci_save_state(dev);
5131 * Disable the device by clearing the Command register, except for
5132 * INTx-disable which is set. This not only disables MMIO and I/O port
5133 * BARs, but also prevents the device from being Bus Master, preventing
5134 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
5135 * compliant devices, INTx-disable prevents legacy interrupts.
5137 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
5140 static void pci_dev_restore(struct pci_dev *dev)
5142 const struct pci_error_handlers *err_handler =
5143 dev->driver ? dev->driver->err_handler : NULL;
5145 pci_restore_state(dev);
5148 * dev->driver->err_handler->reset_done() is protected against
5149 * races with ->remove() by the device lock, which must be held by
5152 if (err_handler && err_handler->reset_done)
5153 err_handler->reset_done(dev);
5156 /* dev->reset_methods[] is a 0-terminated list of indices into this array */
5157 static const struct pci_reset_fn_method pci_reset_fn_methods[] = {
5159 { pci_dev_specific_reset, .name = "device_specific" },
5160 { pci_dev_acpi_reset, .name = "acpi" },
5161 { pcie_reset_flr, .name = "flr" },
5162 { pci_af_flr, .name = "af_flr" },
5163 { pci_pm_reset, .name = "pm" },
5164 { pci_reset_bus_function, .name = "bus" },
5167 static ssize_t reset_method_show(struct device *dev,
5168 struct device_attribute *attr, char *buf)
5170 struct pci_dev *pdev = to_pci_dev(dev);
5174 for (i = 0; i < PCI_NUM_RESET_METHODS; i++) {
5175 m = pdev->reset_methods[i];
5179 len += sysfs_emit_at(buf, len, "%s%s", len ? " " : "",
5180 pci_reset_fn_methods[m].name);
5184 len += sysfs_emit_at(buf, len, "\n");
5189 static int reset_method_lookup(const char *name)
5193 for (m = 1; m < PCI_NUM_RESET_METHODS; m++) {
5194 if (sysfs_streq(name, pci_reset_fn_methods[m].name))
5198 return 0; /* not found */
5201 static ssize_t reset_method_store(struct device *dev,
5202 struct device_attribute *attr,
5203 const char *buf, size_t count)
5205 struct pci_dev *pdev = to_pci_dev(dev);
5206 char *options, *name;
5208 u8 reset_methods[PCI_NUM_RESET_METHODS] = { 0 };
5210 if (sysfs_streq(buf, "")) {
5211 pdev->reset_methods[0] = 0;
5212 pci_warn(pdev, "All device reset methods disabled by user");
5216 if (sysfs_streq(buf, "default")) {
5217 pci_init_reset_methods(pdev);
5221 options = kstrndup(buf, count, GFP_KERNEL);
5226 while ((name = strsep(&options, " ")) != NULL) {
5227 if (sysfs_streq(name, ""))
5232 m = reset_method_lookup(name);
5234 pci_err(pdev, "Invalid reset method '%s'", name);
5238 if (pci_reset_fn_methods[m].reset_fn(pdev, PCI_RESET_PROBE)) {
5239 pci_err(pdev, "Unsupported reset method '%s'", name);
5243 if (n == PCI_NUM_RESET_METHODS - 1) {
5244 pci_err(pdev, "Too many reset methods\n");
5248 reset_methods[n++] = m;
5251 reset_methods[n] = 0;
5253 /* Warn if dev-specific supported but not highest priority */
5254 if (pci_reset_fn_methods[1].reset_fn(pdev, PCI_RESET_PROBE) == 0 &&
5255 reset_methods[0] != 1)
5256 pci_warn(pdev, "Device-specific reset disabled/de-prioritized by user");
5257 memcpy(pdev->reset_methods, reset_methods, sizeof(pdev->reset_methods));
5262 /* Leave previous methods unchanged */
5266 static DEVICE_ATTR_RW(reset_method);
5268 static struct attribute *pci_dev_reset_method_attrs[] = {
5269 &dev_attr_reset_method.attr,
5273 static umode_t pci_dev_reset_method_attr_is_visible(struct kobject *kobj,
5274 struct attribute *a, int n)
5276 struct pci_dev *pdev = to_pci_dev(kobj_to_dev(kobj));
5278 if (!pci_reset_supported(pdev))
5284 const struct attribute_group pci_dev_reset_method_attr_group = {
5285 .attrs = pci_dev_reset_method_attrs,
5286 .is_visible = pci_dev_reset_method_attr_is_visible,
5290 * __pci_reset_function_locked - reset a PCI device function while holding
5291 * the @dev mutex lock.
5292 * @dev: PCI device to reset
5294 * Some devices allow an individual function to be reset without affecting
5295 * other functions in the same device. The PCI device must be responsive
5296 * to PCI config space in order to use this function.
5298 * The device function is presumed to be unused and the caller is holding
5299 * the device mutex lock when this function is called.
5301 * Resetting the device will make the contents of PCI configuration space
5302 * random, so any caller of this must be prepared to reinitialise the
5303 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
5306 * Returns 0 if the device function was successfully reset or negative if the
5307 * device doesn't support resetting a single function.
5309 int __pci_reset_function_locked(struct pci_dev *dev)
5311 int i, m, rc = -ENOTTY;
5316 * A reset method returns -ENOTTY if it doesn't support this device and
5317 * we should try the next method.
5319 * If it returns 0 (success), we're finished. If it returns any other
5320 * error, we're also finished: this indicates that further reset
5321 * mechanisms might be broken on the device.
5323 for (i = 0; i < PCI_NUM_RESET_METHODS; i++) {
5324 m = dev->reset_methods[i];
5328 rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_DO_RESET);
5337 EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
5340 * pci_init_reset_methods - check whether device can be safely reset
5341 * and store supported reset mechanisms.
5342 * @dev: PCI device to check for reset mechanisms
5344 * Some devices allow an individual function to be reset without affecting
5345 * other functions in the same device. The PCI device must be in D0-D3hot
5348 * Stores reset mechanisms supported by device in reset_methods byte array
5349 * which is a member of struct pci_dev.
5351 void pci_init_reset_methods(struct pci_dev *dev)
5355 BUILD_BUG_ON(ARRAY_SIZE(pci_reset_fn_methods) != PCI_NUM_RESET_METHODS);
5360 for (m = 1; m < PCI_NUM_RESET_METHODS; m++) {
5361 rc = pci_reset_fn_methods[m].reset_fn(dev, PCI_RESET_PROBE);
5363 dev->reset_methods[i++] = m;
5364 else if (rc != -ENOTTY)
5368 dev->reset_methods[i] = 0;
5372 * pci_reset_function - quiesce and reset a PCI device function
5373 * @dev: PCI device to reset
5375 * Some devices allow an individual function to be reset without affecting
5376 * other functions in the same device. The PCI device must be responsive
5377 * to PCI config space in order to use this function.
5379 * This function does not just reset the PCI portion of a device, but
5380 * clears all the state associated with the device. This function differs
5381 * from __pci_reset_function_locked() in that it saves and restores device state
5382 * over the reset and takes the PCI device lock.
5384 * Returns 0 if the device function was successfully reset or negative if the
5385 * device doesn't support resetting a single function.
5387 int pci_reset_function(struct pci_dev *dev)
5391 if (!pci_reset_supported(dev))
5395 pci_dev_save_and_disable(dev);
5397 rc = __pci_reset_function_locked(dev);
5399 pci_dev_restore(dev);
5400 pci_dev_unlock(dev);
5404 EXPORT_SYMBOL_GPL(pci_reset_function);
5407 * pci_reset_function_locked - quiesce and reset a PCI device function
5408 * @dev: PCI device to reset
5410 * Some devices allow an individual function to be reset without affecting
5411 * other functions in the same device. The PCI device must be responsive
5412 * to PCI config space in order to use this function.
5414 * This function does not just reset the PCI portion of a device, but
5415 * clears all the state associated with the device. This function differs
5416 * from __pci_reset_function_locked() in that it saves and restores device state
5417 * over the reset. It also differs from pci_reset_function() in that it
5418 * requires the PCI device lock to be held.
5420 * Returns 0 if the device function was successfully reset or negative if the
5421 * device doesn't support resetting a single function.
5423 int pci_reset_function_locked(struct pci_dev *dev)
5427 if (!pci_reset_supported(dev))
5430 pci_dev_save_and_disable(dev);
5432 rc = __pci_reset_function_locked(dev);
5434 pci_dev_restore(dev);
5438 EXPORT_SYMBOL_GPL(pci_reset_function_locked);
5441 * pci_try_reset_function - quiesce and reset a PCI device function
5442 * @dev: PCI device to reset
5444 * Same as above, except return -EAGAIN if unable to lock device.
5446 int pci_try_reset_function(struct pci_dev *dev)
5450 if (!pci_reset_supported(dev))
5453 if (!pci_dev_trylock(dev))
5456 pci_dev_save_and_disable(dev);
5457 rc = __pci_reset_function_locked(dev);
5458 pci_dev_restore(dev);
5459 pci_dev_unlock(dev);
5463 EXPORT_SYMBOL_GPL(pci_try_reset_function);
5465 /* Do any devices on or below this bus prevent a bus reset? */
5466 static bool pci_bus_resetable(struct pci_bus *bus)
5468 struct pci_dev *dev;
5471 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5474 list_for_each_entry(dev, &bus->devices, bus_list) {
5475 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5476 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5483 /* Lock devices from the top of the tree down */
5484 static void pci_bus_lock(struct pci_bus *bus)
5486 struct pci_dev *dev;
5488 list_for_each_entry(dev, &bus->devices, bus_list) {
5490 if (dev->subordinate)
5491 pci_bus_lock(dev->subordinate);
5495 /* Unlock devices from the bottom of the tree up */
5496 static void pci_bus_unlock(struct pci_bus *bus)
5498 struct pci_dev *dev;
5500 list_for_each_entry(dev, &bus->devices, bus_list) {
5501 if (dev->subordinate)
5502 pci_bus_unlock(dev->subordinate);
5503 pci_dev_unlock(dev);
5507 /* Return 1 on successful lock, 0 on contention */
5508 static int pci_bus_trylock(struct pci_bus *bus)
5510 struct pci_dev *dev;
5512 list_for_each_entry(dev, &bus->devices, bus_list) {
5513 if (!pci_dev_trylock(dev))
5515 if (dev->subordinate) {
5516 if (!pci_bus_trylock(dev->subordinate)) {
5517 pci_dev_unlock(dev);
5525 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
5526 if (dev->subordinate)
5527 pci_bus_unlock(dev->subordinate);
5528 pci_dev_unlock(dev);
5533 /* Do any devices on or below this slot prevent a bus reset? */
5534 static bool pci_slot_resetable(struct pci_slot *slot)
5536 struct pci_dev *dev;
5538 if (slot->bus->self &&
5539 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET))
5542 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5543 if (!dev->slot || dev->slot != slot)
5545 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5546 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5553 /* Lock devices from the top of the tree down */
5554 static void pci_slot_lock(struct pci_slot *slot)
5556 struct pci_dev *dev;
5558 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5559 if (!dev->slot || dev->slot != slot)
5562 if (dev->subordinate)
5563 pci_bus_lock(dev->subordinate);
5567 /* Unlock devices from the bottom of the tree up */
5568 static void pci_slot_unlock(struct pci_slot *slot)
5570 struct pci_dev *dev;
5572 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5573 if (!dev->slot || dev->slot != slot)
5575 if (dev->subordinate)
5576 pci_bus_unlock(dev->subordinate);
5577 pci_dev_unlock(dev);
5581 /* Return 1 on successful lock, 0 on contention */
5582 static int pci_slot_trylock(struct pci_slot *slot)
5584 struct pci_dev *dev;
5586 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5587 if (!dev->slot || dev->slot != slot)
5589 if (!pci_dev_trylock(dev))
5591 if (dev->subordinate) {
5592 if (!pci_bus_trylock(dev->subordinate)) {
5593 pci_dev_unlock(dev);
5601 list_for_each_entry_continue_reverse(dev,
5602 &slot->bus->devices, bus_list) {
5603 if (!dev->slot || dev->slot != slot)
5605 if (dev->subordinate)
5606 pci_bus_unlock(dev->subordinate);
5607 pci_dev_unlock(dev);
5613 * Save and disable devices from the top of the tree down while holding
5614 * the @dev mutex lock for the entire tree.
5616 static void pci_bus_save_and_disable_locked(struct pci_bus *bus)
5618 struct pci_dev *dev;
5620 list_for_each_entry(dev, &bus->devices, bus_list) {
5621 pci_dev_save_and_disable(dev);
5622 if (dev->subordinate)
5623 pci_bus_save_and_disable_locked(dev->subordinate);
5628 * Restore devices from top of the tree down while holding @dev mutex lock
5629 * for the entire tree. Parent bridges need to be restored before we can
5630 * get to subordinate devices.
5632 static void pci_bus_restore_locked(struct pci_bus *bus)
5634 struct pci_dev *dev;
5636 list_for_each_entry(dev, &bus->devices, bus_list) {
5637 pci_dev_restore(dev);
5638 if (dev->subordinate)
5639 pci_bus_restore_locked(dev->subordinate);
5644 * Save and disable devices from the top of the tree down while holding
5645 * the @dev mutex lock for the entire tree.
5647 static void pci_slot_save_and_disable_locked(struct pci_slot *slot)
5649 struct pci_dev *dev;
5651 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5652 if (!dev->slot || dev->slot != slot)
5654 pci_dev_save_and_disable(dev);
5655 if (dev->subordinate)
5656 pci_bus_save_and_disable_locked(dev->subordinate);
5661 * Restore devices from top of the tree down while holding @dev mutex lock
5662 * for the entire tree. Parent bridges need to be restored before we can
5663 * get to subordinate devices.
5665 static void pci_slot_restore_locked(struct pci_slot *slot)
5667 struct pci_dev *dev;
5669 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5670 if (!dev->slot || dev->slot != slot)
5672 pci_dev_restore(dev);
5673 if (dev->subordinate)
5674 pci_bus_restore_locked(dev->subordinate);
5678 static int pci_slot_reset(struct pci_slot *slot, bool probe)
5682 if (!slot || !pci_slot_resetable(slot))
5686 pci_slot_lock(slot);
5690 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
5693 pci_slot_unlock(slot);
5699 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5700 * @slot: PCI slot to probe
5702 * Return 0 if slot can be reset, negative if a slot reset is not supported.
5704 int pci_probe_reset_slot(struct pci_slot *slot)
5706 return pci_slot_reset(slot, PCI_RESET_PROBE);
5708 EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
5711 * __pci_reset_slot - Try to reset a PCI slot
5712 * @slot: PCI slot to reset
5714 * A PCI bus may host multiple slots, each slot may support a reset mechanism
5715 * independent of other slots. For instance, some slots may support slot power
5716 * control. In the case of a 1:1 bus to slot architecture, this function may
5717 * wrap the bus reset to avoid spurious slot related events such as hotplug.
5718 * Generally a slot reset should be attempted before a bus reset. All of the
5719 * function of the slot and any subordinate buses behind the slot are reset
5720 * through this function. PCI config space of all devices in the slot and
5721 * behind the slot is saved before and restored after reset.
5723 * Same as above except return -EAGAIN if the slot cannot be locked
5725 static int __pci_reset_slot(struct pci_slot *slot)
5729 rc = pci_slot_reset(slot, PCI_RESET_PROBE);
5733 if (pci_slot_trylock(slot)) {
5734 pci_slot_save_and_disable_locked(slot);
5736 rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET);
5737 pci_slot_restore_locked(slot);
5738 pci_slot_unlock(slot);
5745 static int pci_bus_reset(struct pci_bus *bus, bool probe)
5749 if (!bus->self || !pci_bus_resetable(bus))
5759 ret = pci_bridge_secondary_bus_reset(bus->self);
5761 pci_bus_unlock(bus);
5767 * pci_bus_error_reset - reset the bridge's subordinate bus
5768 * @bridge: The parent device that connects to the bus to reset
5770 * This function will first try to reset the slots on this bus if the method is
5771 * available. If slot reset fails or is not available, this will fall back to a
5772 * secondary bus reset.
5774 int pci_bus_error_reset(struct pci_dev *bridge)
5776 struct pci_bus *bus = bridge->subordinate;
5777 struct pci_slot *slot;
5782 mutex_lock(&pci_slot_mutex);
5783 if (list_empty(&bus->slots))
5786 list_for_each_entry(slot, &bus->slots, list)
5787 if (pci_probe_reset_slot(slot))
5790 list_for_each_entry(slot, &bus->slots, list)
5791 if (pci_slot_reset(slot, PCI_RESET_DO_RESET))
5794 mutex_unlock(&pci_slot_mutex);
5797 mutex_unlock(&pci_slot_mutex);
5798 return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET);
5802 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5803 * @bus: PCI bus to probe
5805 * Return 0 if bus can be reset, negative if a bus reset is not supported.
5807 int pci_probe_reset_bus(struct pci_bus *bus)
5809 return pci_bus_reset(bus, PCI_RESET_PROBE);
5811 EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
5814 * __pci_reset_bus - Try to reset a PCI bus
5815 * @bus: top level PCI bus to reset
5817 * Same as above except return -EAGAIN if the bus cannot be locked
5819 static int __pci_reset_bus(struct pci_bus *bus)
5823 rc = pci_bus_reset(bus, PCI_RESET_PROBE);
5827 if (pci_bus_trylock(bus)) {
5828 pci_bus_save_and_disable_locked(bus);
5830 rc = pci_bridge_secondary_bus_reset(bus->self);
5831 pci_bus_restore_locked(bus);
5832 pci_bus_unlock(bus);
5840 * pci_reset_bus - Try to reset a PCI bus
5841 * @pdev: top level PCI device to reset via slot/bus
5843 * Same as above except return -EAGAIN if the bus cannot be locked
5845 int pci_reset_bus(struct pci_dev *pdev)
5847 return (!pci_probe_reset_slot(pdev->slot)) ?
5848 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus);
5850 EXPORT_SYMBOL_GPL(pci_reset_bus);
5853 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5854 * @dev: PCI device to query
5856 * Returns mmrbc: maximum designed memory read count in bytes or
5857 * appropriate error value.
5859 int pcix_get_max_mmrbc(struct pci_dev *dev)
5864 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5868 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5871 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
5873 EXPORT_SYMBOL(pcix_get_max_mmrbc);
5876 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5877 * @dev: PCI device to query
5879 * Returns mmrbc: maximum memory read count in bytes or appropriate error
5882 int pcix_get_mmrbc(struct pci_dev *dev)
5887 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5891 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5894 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
5896 EXPORT_SYMBOL(pcix_get_mmrbc);
5899 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5900 * @dev: PCI device to query
5901 * @mmrbc: maximum memory read count in bytes
5902 * valid values are 512, 1024, 2048, 4096
5904 * If possible sets maximum memory read byte count, some bridges have errata
5905 * that prevent this.
5907 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
5913 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
5916 v = ffs(mmrbc) - 10;
5918 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5922 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5925 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
5928 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5931 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
5933 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
5936 cmd &= ~PCI_X_CMD_MAX_READ;
5938 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
5943 EXPORT_SYMBOL(pcix_set_mmrbc);
5946 * pcie_get_readrq - get PCI Express read request size
5947 * @dev: PCI device to query
5949 * Returns maximum memory read request in bytes or appropriate error value.
5951 int pcie_get_readrq(struct pci_dev *dev)
5955 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5957 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
5959 EXPORT_SYMBOL(pcie_get_readrq);
5962 * pcie_set_readrq - set PCI Express maximum memory read request
5963 * @dev: PCI device to query
5964 * @rq: maximum memory read count in bytes
5965 * valid values are 128, 256, 512, 1024, 2048, 4096
5967 * If possible sets maximum memory read request in bytes
5969 int pcie_set_readrq(struct pci_dev *dev, int rq)
5974 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
5978 * If using the "performance" PCIe config, we clamp the read rq
5979 * size to the max packet size to keep the host bridge from
5980 * generating requests larger than we can cope with.
5982 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
5983 int mps = pcie_get_mps(dev);
5989 v = (ffs(rq) - 8) << 12;
5991 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5992 PCI_EXP_DEVCTL_READRQ, v);
5994 return pcibios_err_to_errno(ret);
5996 EXPORT_SYMBOL(pcie_set_readrq);
5999 * pcie_get_mps - get PCI Express maximum payload size
6000 * @dev: PCI device to query
6002 * Returns maximum payload size in bytes
6004 int pcie_get_mps(struct pci_dev *dev)
6008 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
6010 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6012 EXPORT_SYMBOL(pcie_get_mps);
6015 * pcie_set_mps - set PCI Express maximum payload size
6016 * @dev: PCI device to query
6017 * @mps: maximum payload size in bytes
6018 * valid values are 128, 256, 512, 1024, 2048, 4096
6020 * If possible sets maximum payload size
6022 int pcie_set_mps(struct pci_dev *dev, int mps)
6027 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
6031 if (v > dev->pcie_mpss)
6035 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
6036 PCI_EXP_DEVCTL_PAYLOAD, v);
6038 return pcibios_err_to_errno(ret);
6040 EXPORT_SYMBOL(pcie_set_mps);
6043 * pcie_bandwidth_available - determine minimum link settings of a PCIe
6044 * device and its bandwidth limitation
6045 * @dev: PCI device to query
6046 * @limiting_dev: storage for device causing the bandwidth limitation
6047 * @speed: storage for speed of limiting device
6048 * @width: storage for width of limiting device
6050 * Walk up the PCI device chain and find the point where the minimum
6051 * bandwidth is available. Return the bandwidth available there and (if
6052 * limiting_dev, speed, and width pointers are supplied) information about
6053 * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of
6056 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
6057 enum pci_bus_speed *speed,
6058 enum pcie_link_width *width)
6061 enum pci_bus_speed next_speed;
6062 enum pcie_link_width next_width;
6066 *speed = PCI_SPEED_UNKNOWN;
6068 *width = PCIE_LNK_WIDTH_UNKNOWN;
6073 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
6075 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
6076 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
6077 PCI_EXP_LNKSTA_NLW_SHIFT;
6079 next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed);
6081 /* Check if current device limits the total bandwidth */
6082 if (!bw || next_bw <= bw) {
6086 *limiting_dev = dev;
6088 *speed = next_speed;
6090 *width = next_width;
6093 dev = pci_upstream_bridge(dev);
6098 EXPORT_SYMBOL(pcie_bandwidth_available);
6101 * pcie_get_speed_cap - query for the PCI device's link speed capability
6102 * @dev: PCI device to query
6104 * Query the PCI device speed capability. Return the maximum link speed
6105 * supported by the device.
6107 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
6109 u32 lnkcap2, lnkcap;
6112 * Link Capabilities 2 was added in PCIe r3.0, sec 7.8.18. The
6113 * implementation note there recommends using the Supported Link
6114 * Speeds Vector in Link Capabilities 2 when supported.
6116 * Without Link Capabilities 2, i.e., prior to PCIe r3.0, software
6117 * should use the Supported Link Speeds field in Link Capabilities,
6118 * where only 2.5 GT/s and 5.0 GT/s speeds were defined.
6120 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
6122 /* PCIe r3.0-compliant */
6124 return PCIE_LNKCAP2_SLS2SPEED(lnkcap2);
6126 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6127 if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_5_0GB)
6128 return PCIE_SPEED_5_0GT;
6129 else if ((lnkcap & PCI_EXP_LNKCAP_SLS) == PCI_EXP_LNKCAP_SLS_2_5GB)
6130 return PCIE_SPEED_2_5GT;
6132 return PCI_SPEED_UNKNOWN;
6134 EXPORT_SYMBOL(pcie_get_speed_cap);
6137 * pcie_get_width_cap - query for the PCI device's link width capability
6138 * @dev: PCI device to query
6140 * Query the PCI device width capability. Return the maximum link width
6141 * supported by the device.
6143 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
6147 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
6149 return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4;
6151 return PCIE_LNK_WIDTH_UNKNOWN;
6153 EXPORT_SYMBOL(pcie_get_width_cap);
6156 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
6158 * @speed: storage for link speed
6159 * @width: storage for link width
6161 * Calculate a PCI device's link bandwidth by querying for its link speed
6162 * and width, multiplying them, and applying encoding overhead. The result
6163 * is in Mb/s, i.e., megabits/second of raw bandwidth.
6165 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
6166 enum pcie_link_width *width)
6168 *speed = pcie_get_speed_cap(dev);
6169 *width = pcie_get_width_cap(dev);
6171 if (*speed == PCI_SPEED_UNKNOWN || *width == PCIE_LNK_WIDTH_UNKNOWN)
6174 return *width * PCIE_SPEED2MBS_ENC(*speed);
6178 * __pcie_print_link_status - Report the PCI device's link speed and width
6179 * @dev: PCI device to query
6180 * @verbose: Print info even when enough bandwidth is available
6182 * If the available bandwidth at the device is less than the device is
6183 * capable of, report the device's maximum possible bandwidth and the
6184 * upstream link that limits its performance. If @verbose, always print
6185 * the available bandwidth, even if the device isn't constrained.
6187 void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
6189 enum pcie_link_width width, width_cap;
6190 enum pci_bus_speed speed, speed_cap;
6191 struct pci_dev *limiting_dev = NULL;
6192 u32 bw_avail, bw_cap;
6194 bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
6195 bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
6197 if (bw_avail >= bw_cap && verbose)
6198 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
6199 bw_cap / 1000, bw_cap % 1000,
6200 pci_speed_string(speed_cap), width_cap);
6201 else if (bw_avail < bw_cap)
6202 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
6203 bw_avail / 1000, bw_avail % 1000,
6204 pci_speed_string(speed), width,
6205 limiting_dev ? pci_name(limiting_dev) : "<unknown>",
6206 bw_cap / 1000, bw_cap % 1000,
6207 pci_speed_string(speed_cap), width_cap);
6211 * pcie_print_link_status - Report the PCI device's link speed and width
6212 * @dev: PCI device to query
6214 * Report the available bandwidth at the device.
6216 void pcie_print_link_status(struct pci_dev *dev)
6218 __pcie_print_link_status(dev, true);
6220 EXPORT_SYMBOL(pcie_print_link_status);
6223 * pci_select_bars - Make BAR mask from the type of resource
6224 * @dev: the PCI device for which BAR mask is made
6225 * @flags: resource type mask to be selected
6227 * This helper routine makes bar mask from the type of resource.
6229 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
6232 for (i = 0; i < PCI_NUM_RESOURCES; i++)
6233 if (pci_resource_flags(dev, i) & flags)
6237 EXPORT_SYMBOL(pci_select_bars);
6239 /* Some architectures require additional programming to enable VGA */
6240 static arch_set_vga_state_t arch_set_vga_state;
6242 void __init pci_register_set_vga_state(arch_set_vga_state_t func)
6244 arch_set_vga_state = func; /* NULL disables */
6247 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
6248 unsigned int command_bits, u32 flags)
6250 if (arch_set_vga_state)
6251 return arch_set_vga_state(dev, decode, command_bits,
6257 * pci_set_vga_state - set VGA decode state on device and parents if requested
6258 * @dev: the PCI device
6259 * @decode: true = enable decoding, false = disable decoding
6260 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
6261 * @flags: traverse ancestors and change bridges
6262 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
6264 int pci_set_vga_state(struct pci_dev *dev, bool decode,
6265 unsigned int command_bits, u32 flags)
6267 struct pci_bus *bus;
6268 struct pci_dev *bridge;
6272 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
6274 /* ARCH specific VGA enables */
6275 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
6279 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
6280 pci_read_config_word(dev, PCI_COMMAND, &cmd);
6282 cmd |= command_bits;
6284 cmd &= ~command_bits;
6285 pci_write_config_word(dev, PCI_COMMAND, cmd);
6288 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
6295 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
6298 cmd |= PCI_BRIDGE_CTL_VGA;
6300 cmd &= ~PCI_BRIDGE_CTL_VGA;
6301 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
6310 bool pci_pr3_present(struct pci_dev *pdev)
6312 struct acpi_device *adev;
6317 adev = ACPI_COMPANION(&pdev->dev);
6321 return adev->power.flags.power_resources &&
6322 acpi_has_method(adev->handle, "_PR3");
6324 EXPORT_SYMBOL_GPL(pci_pr3_present);
6328 * pci_add_dma_alias - Add a DMA devfn alias for a device
6329 * @dev: the PCI device for which alias is added
6330 * @devfn_from: alias slot and function
6331 * @nr_devfns: number of subsequent devfns to alias
6333 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6334 * which is used to program permissible bus-devfn source addresses for DMA
6335 * requests in an IOMMU. These aliases factor into IOMMU group creation
6336 * and are useful for devices generating DMA requests beyond or different
6337 * from their logical bus-devfn. Examples include device quirks where the
6338 * device simply uses the wrong devfn, as well as non-transparent bridges
6339 * where the alias may be a proxy for devices in another domain.
6341 * IOMMU group creation is performed during device discovery or addition,
6342 * prior to any potential DMA mapping and therefore prior to driver probing
6343 * (especially for userspace assigned devices where IOMMU group definition
6344 * cannot be left as a userspace activity). DMA aliases should therefore
6345 * be configured via quirks, such as the PCI fixup header quirk.
6347 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns)
6351 nr_devfns = min(nr_devfns, (unsigned) MAX_NR_DEVFNS - devfn_from);
6352 devfn_to = devfn_from + nr_devfns - 1;
6354 if (!dev->dma_alias_mask)
6355 dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL);
6356 if (!dev->dma_alias_mask) {
6357 pci_warn(dev, "Unable to allocate DMA alias mask\n");
6361 bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns);
6364 pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
6365 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from));
6366 else if (nr_devfns > 1)
6367 pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",
6368 PCI_SLOT(devfn_from), PCI_FUNC(devfn_from),
6369 PCI_SLOT(devfn_to), PCI_FUNC(devfn_to));
6372 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
6374 return (dev1->dma_alias_mask &&
6375 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
6376 (dev2->dma_alias_mask &&
6377 test_bit(dev1->devfn, dev2->dma_alias_mask)) ||
6378 pci_real_dma_dev(dev1) == dev2 ||
6379 pci_real_dma_dev(dev2) == dev1;
6382 bool pci_device_is_present(struct pci_dev *pdev)
6386 if (pci_dev_is_disconnected(pdev))
6388 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
6390 EXPORT_SYMBOL_GPL(pci_device_is_present);
6392 void pci_ignore_hotplug(struct pci_dev *dev)
6394 struct pci_dev *bridge = dev->bus->self;
6396 dev->ignore_hotplug = 1;
6397 /* Propagate the "ignore hotplug" setting to the parent bridge. */
6399 bridge->ignore_hotplug = 1;
6401 EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
6404 * pci_real_dma_dev - Get PCI DMA device for PCI device
6405 * @dev: the PCI device that may have a PCI DMA alias
6407 * Permits the platform to provide architecture-specific functionality to
6408 * devices needing to alias DMA to another PCI device on another PCI bus. If
6409 * the PCI device is on the same bus, it is recommended to use
6410 * pci_add_dma_alias(). This is the default implementation. Architecture
6411 * implementations can override this.
6413 struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev)
6418 resource_size_t __weak pcibios_default_alignment(void)
6424 * Arches that don't want to expose struct resource to userland as-is in
6425 * sysfs and /proc can implement their own pci_resource_to_user().
6427 void __weak pci_resource_to_user(const struct pci_dev *dev, int bar,
6428 const struct resource *rsrc,
6429 resource_size_t *start, resource_size_t *end)
6431 *start = rsrc->start;
6435 static char *resource_alignment_param;
6436 static DEFINE_SPINLOCK(resource_alignment_lock);
6439 * pci_specified_resource_alignment - get resource alignment specified by user.
6440 * @dev: the PCI device to get
6441 * @resize: whether or not to change resources' size when reassigning alignment
6443 * RETURNS: Resource alignment if it is specified.
6444 * Zero if it is not specified.
6446 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
6449 int align_order, count;
6450 resource_size_t align = pcibios_default_alignment();
6454 spin_lock(&resource_alignment_lock);
6455 p = resource_alignment_param;
6458 if (pci_has_flag(PCI_PROBE_ONLY)) {
6460 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
6466 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
6469 if (align_order > 63) {
6470 pr_err("PCI: Invalid requested alignment (order %d)\n",
6472 align_order = PAGE_SHIFT;
6475 align_order = PAGE_SHIFT;
6478 ret = pci_dev_str_match(dev, p, &p);
6481 align = 1ULL << align_order;
6483 } else if (ret < 0) {
6484 pr_err("PCI: Can't parse resource_alignment parameter: %s\n",
6489 if (*p != ';' && *p != ',') {
6490 /* End of param or invalid format */
6496 spin_unlock(&resource_alignment_lock);
6500 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
6501 resource_size_t align, bool resize)
6503 struct resource *r = &dev->resource[bar];
6504 resource_size_t size;
6506 if (!(r->flags & IORESOURCE_MEM))
6509 if (r->flags & IORESOURCE_PCI_FIXED) {
6510 pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
6511 bar, r, (unsigned long long)align);
6515 size = resource_size(r);
6520 * Increase the alignment of the resource. There are two ways we
6523 * 1) Increase the size of the resource. BARs are aligned on their
6524 * size, so when we reallocate space for this resource, we'll
6525 * allocate it with the larger alignment. This also prevents
6526 * assignment of any other BARs inside the alignment region, so
6527 * if we're requesting page alignment, this means no other BARs
6528 * will share the page.
6530 * The disadvantage is that this makes the resource larger than
6531 * the hardware BAR, which may break drivers that compute things
6532 * based on the resource size, e.g., to find registers at a
6533 * fixed offset before the end of the BAR.
6535 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and
6536 * set r->start to the desired alignment. By itself this
6537 * doesn't prevent other BARs being put inside the alignment
6538 * region, but if we realign *every* resource of every device in
6539 * the system, none of them will share an alignment region.
6541 * When the user has requested alignment for only some devices via
6542 * the "pci=resource_alignment" argument, "resize" is true and we
6543 * use the first method. Otherwise we assume we're aligning all
6544 * devices and we use the second.
6547 pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
6548 bar, r, (unsigned long long)align);
6554 r->flags &= ~IORESOURCE_SIZEALIGN;
6555 r->flags |= IORESOURCE_STARTALIGN;
6557 r->end = r->start + size - 1;
6559 r->flags |= IORESOURCE_UNSET;
6563 * This function disables memory decoding and releases memory resources
6564 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
6565 * It also rounds up size to specified alignment.
6566 * Later on, the kernel will assign page-aligned memory resource back
6569 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
6573 resource_size_t align;
6575 bool resize = false;
6578 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
6579 * 3.4.1.11. Their resources are allocated from the space
6580 * described by the VF BARx register in the PF's SR-IOV capability.
6581 * We can't influence their alignment here.
6586 /* check if specified PCI is target device to reassign */
6587 align = pci_specified_resource_alignment(dev, &resize);
6591 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
6592 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
6593 pci_warn(dev, "Can't reassign resources to host bridge\n");
6597 pci_read_config_word(dev, PCI_COMMAND, &command);
6598 command &= ~PCI_COMMAND_MEMORY;
6599 pci_write_config_word(dev, PCI_COMMAND, command);
6601 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
6602 pci_request_resource_alignment(dev, i, align, resize);
6605 * Need to disable bridge's resource window,
6606 * to enable the kernel to reassign new resource
6609 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
6610 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
6611 r = &dev->resource[i];
6612 if (!(r->flags & IORESOURCE_MEM))
6614 r->flags |= IORESOURCE_UNSET;
6615 r->end = resource_size(r) - 1;
6618 pci_disable_bridge_window(dev);
6622 static ssize_t resource_alignment_show(struct bus_type *bus, char *buf)
6626 spin_lock(&resource_alignment_lock);
6627 if (resource_alignment_param)
6628 count = sysfs_emit(buf, "%s\n", resource_alignment_param);
6629 spin_unlock(&resource_alignment_lock);
6634 static ssize_t resource_alignment_store(struct bus_type *bus,
6635 const char *buf, size_t count)
6637 char *param, *old, *end;
6639 if (count >= (PAGE_SIZE - 1))
6642 param = kstrndup(buf, count, GFP_KERNEL);
6646 end = strchr(param, '\n');
6650 spin_lock(&resource_alignment_lock);
6651 old = resource_alignment_param;
6652 if (strlen(param)) {
6653 resource_alignment_param = param;
6656 resource_alignment_param = NULL;
6658 spin_unlock(&resource_alignment_lock);
6665 static BUS_ATTR_RW(resource_alignment);
6667 static int __init pci_resource_alignment_sysfs_init(void)
6669 return bus_create_file(&pci_bus_type,
6670 &bus_attr_resource_alignment);
6672 late_initcall(pci_resource_alignment_sysfs_init);
6674 static void pci_no_domains(void)
6676 #ifdef CONFIG_PCI_DOMAINS
6677 pci_domains_supported = 0;
6681 #ifdef CONFIG_PCI_DOMAINS_GENERIC
6682 static atomic_t __domain_nr = ATOMIC_INIT(-1);
6684 static int pci_get_new_domain_nr(void)
6686 return atomic_inc_return(&__domain_nr);
6689 static int of_pci_bus_find_domain_nr(struct device *parent)
6691 static int use_dt_domains = -1;
6695 domain = of_get_pci_domain_nr(parent->of_node);
6698 * Check DT domain and use_dt_domains values.
6700 * If DT domain property is valid (domain >= 0) and
6701 * use_dt_domains != 0, the DT assignment is valid since this means
6702 * we have not previously allocated a domain number by using
6703 * pci_get_new_domain_nr(); we should also update use_dt_domains to
6704 * 1, to indicate that we have just assigned a domain number from
6707 * If DT domain property value is not valid (ie domain < 0), and we
6708 * have not previously assigned a domain number from DT
6709 * (use_dt_domains != 1) we should assign a domain number by
6712 * pci_get_new_domain_nr()
6714 * API and update the use_dt_domains value to keep track of method we
6715 * are using to assign domain numbers (use_dt_domains = 0).
6717 * All other combinations imply we have a platform that is trying
6718 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
6719 * which is a recipe for domain mishandling and it is prevented by
6720 * invalidating the domain value (domain = -1) and printing a
6721 * corresponding error.
6723 if (domain >= 0 && use_dt_domains) {
6725 } else if (domain < 0 && use_dt_domains != 1) {
6727 domain = pci_get_new_domain_nr();
6730 pr_err("Node %pOF has ", parent->of_node);
6731 pr_err("Inconsistent \"linux,pci-domain\" property in DT\n");
6738 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
6740 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
6741 acpi_pci_bus_find_domain_nr(bus);
6746 * pci_ext_cfg_avail - can we access extended PCI config space?
6748 * Returns 1 if we can access PCI extended config space (offsets
6749 * greater than 0xff). This is the default implementation. Architecture
6750 * implementations can override this.
6752 int __weak pci_ext_cfg_avail(void)
6757 void __weak pci_fixup_cardbus(struct pci_bus *bus)
6760 EXPORT_SYMBOL(pci_fixup_cardbus);
6762 static int __init pci_setup(char *str)
6765 char *k = strchr(str, ',');
6768 if (*str && (str = pcibios_setup(str)) && *str) {
6769 if (!strcmp(str, "nomsi")) {
6771 } else if (!strncmp(str, "noats", 5)) {
6772 pr_info("PCIe: ATS is disabled\n");
6773 pcie_ats_disabled = true;
6774 } else if (!strcmp(str, "noaer")) {
6776 } else if (!strcmp(str, "earlydump")) {
6777 pci_early_dump = true;
6778 } else if (!strncmp(str, "realloc=", 8)) {
6779 pci_realloc_get_opt(str + 8);
6780 } else if (!strncmp(str, "realloc", 7)) {
6781 pci_realloc_get_opt("on");
6782 } else if (!strcmp(str, "nodomains")) {
6784 } else if (!strncmp(str, "noari", 5)) {
6785 pcie_ari_disabled = true;
6786 } else if (!strncmp(str, "cbiosize=", 9)) {
6787 pci_cardbus_io_size = memparse(str + 9, &str);
6788 } else if (!strncmp(str, "cbmemsize=", 10)) {
6789 pci_cardbus_mem_size = memparse(str + 10, &str);
6790 } else if (!strncmp(str, "resource_alignment=", 19)) {
6791 resource_alignment_param = str + 19;
6792 } else if (!strncmp(str, "ecrc=", 5)) {
6793 pcie_ecrc_get_policy(str + 5);
6794 } else if (!strncmp(str, "hpiosize=", 9)) {
6795 pci_hotplug_io_size = memparse(str + 9, &str);
6796 } else if (!strncmp(str, "hpmmiosize=", 11)) {
6797 pci_hotplug_mmio_size = memparse(str + 11, &str);
6798 } else if (!strncmp(str, "hpmmioprefsize=", 15)) {
6799 pci_hotplug_mmio_pref_size = memparse(str + 15, &str);
6800 } else if (!strncmp(str, "hpmemsize=", 10)) {
6801 pci_hotplug_mmio_size = memparse(str + 10, &str);
6802 pci_hotplug_mmio_pref_size = pci_hotplug_mmio_size;
6803 } else if (!strncmp(str, "hpbussize=", 10)) {
6804 pci_hotplug_bus_size =
6805 simple_strtoul(str + 10, &str, 0);
6806 if (pci_hotplug_bus_size > 0xff)
6807 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
6808 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
6809 pcie_bus_config = PCIE_BUS_TUNE_OFF;
6810 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
6811 pcie_bus_config = PCIE_BUS_SAFE;
6812 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
6813 pcie_bus_config = PCIE_BUS_PERFORMANCE;
6814 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
6815 pcie_bus_config = PCIE_BUS_PEER2PEER;
6816 } else if (!strncmp(str, "pcie_scan_all", 13)) {
6817 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
6818 } else if (!strncmp(str, "disable_acs_redir=", 18)) {
6819 disable_acs_redir_param = str + 18;
6821 pr_err("PCI: Unknown option `%s'\n", str);
6828 early_param("pci", pci_setup);
6831 * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
6832 * in pci_setup(), above, to point to data in the __initdata section which
6833 * will be freed after the init sequence is complete. We can't allocate memory
6834 * in pci_setup() because some architectures do not have any memory allocation
6835 * service available during an early_param() call. So we allocate memory and
6836 * copy the variable here before the init section is freed.
6839 static int __init pci_realloc_setup_params(void)
6841 resource_alignment_param = kstrdup(resource_alignment_param,
6843 disable_acs_redir_param = kstrdup(disable_acs_redir_param, GFP_KERNEL);
6847 pure_initcall(pci_realloc_setup_params);