1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2014 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
15 #include <dm/device-internal.h>
17 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
18 #include <asm/fsp/fsp_support.h>
20 #include "pci_internal.h"
22 DECLARE_GLOBAL_DATA_PTR;
24 int pci_get_bus(int busnum, struct udevice **busp)
28 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
30 /* Since buses may not be numbered yet try a little harder with bus 0 */
32 ret = uclass_first_device_err(UCLASS_PCI, busp);
35 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
41 struct udevice *pci_get_controller(struct udevice *dev)
43 while (device_is_on_pci_bus(dev))
49 pci_dev_t dm_pci_get_bdf(const struct udevice *dev)
51 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
52 struct udevice *bus = dev->parent;
55 * This error indicates that @dev is a device on an unprobed PCI bus.
56 * The bus likely has bus=seq == -1, so the PCI_ADD_BUS() macro below
57 * will produce a bad BDF>
59 * A common cause of this problem is that this function is called in the
60 * ofdata_to_platdata() method of @dev. Accessing the PCI bus in that
61 * method is not allowed, since it has not yet been probed. To fix this,
62 * move that access to the probe() method of @dev instead.
64 if (!device_active(bus))
65 log_err("PCI: Device '%s' on unprobed bus '%s'\n", dev->name,
67 return PCI_ADD_BUS(bus->seq, pplat->devfn);
71 * pci_get_bus_max() - returns the bus number of the last active bus
73 * @return last bus number, or -1 if no active buses
75 static int pci_get_bus_max(void)
81 ret = uclass_get(UCLASS_PCI, &uc);
82 uclass_foreach_dev(bus, uc) {
87 debug("%s: ret=%d\n", __func__, ret);
92 int pci_last_busno(void)
94 return pci_get_bus_max();
97 int pci_get_ff(enum pci_size_t size)
109 static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
112 struct fdt_pci_addr addr;
116 dev_for_each_subnode(node, bus) {
117 ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
122 if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
130 int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
131 struct udevice **devp)
135 for (device_find_first_child(bus, &dev);
137 device_find_next_child(&dev)) {
138 struct pci_child_platdata *pplat;
140 pplat = dev_get_parent_platdata(dev);
141 if (pplat && pplat->devfn == find_devfn) {
150 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
155 ret = pci_get_bus(PCI_BUS(bdf), &bus);
158 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
161 static int pci_device_matches_ids(struct udevice *dev,
162 struct pci_device_id *ids)
164 struct pci_child_platdata *pplat;
167 pplat = dev_get_parent_platdata(dev);
170 for (i = 0; ids[i].vendor != 0; i++) {
171 if (pplat->vendor == ids[i].vendor &&
172 pplat->device == ids[i].device)
179 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
180 int *indexp, struct udevice **devp)
184 /* Scan all devices on this bus */
185 for (device_find_first_child(bus, &dev);
187 device_find_next_child(&dev)) {
188 if (pci_device_matches_ids(dev, ids) >= 0) {
189 if ((*indexp)-- <= 0) {
199 int pci_find_device_id(struct pci_device_id *ids, int index,
200 struct udevice **devp)
204 /* Scan all known buses */
205 for (uclass_first_device(UCLASS_PCI, &bus);
207 uclass_next_device(&bus)) {
208 if (!pci_bus_find_devices(bus, ids, &index, devp))
216 static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
217 unsigned int device, int *indexp,
218 struct udevice **devp)
220 struct pci_child_platdata *pplat;
223 for (device_find_first_child(bus, &dev);
225 device_find_next_child(&dev)) {
226 pplat = dev_get_parent_platdata(dev);
227 if (pplat->vendor == vendor && pplat->device == device) {
238 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
239 struct udevice **devp)
243 /* Scan all known buses */
244 for (uclass_first_device(UCLASS_PCI, &bus);
246 uclass_next_device(&bus)) {
247 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
248 return device_probe(*devp);
255 int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
259 /* Scan all known buses */
260 for (pci_find_first_device(&dev);
262 pci_find_next_device(&dev)) {
263 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
265 if (pplat->class == find_class && !index--) {
267 return device_probe(*devp);
275 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
276 unsigned long value, enum pci_size_t size)
278 struct dm_pci_ops *ops;
280 ops = pci_get_ops(bus);
281 if (!ops->write_config)
283 return ops->write_config(bus, bdf, offset, value, size);
286 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
292 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
298 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
301 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
302 enum pci_size_t size)
307 ret = pci_get_bus(PCI_BUS(bdf), &bus);
311 return pci_bus_write_config(bus, bdf, offset, value, size);
314 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
315 enum pci_size_t size)
319 for (bus = dev; device_is_on_pci_bus(bus);)
321 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
325 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
327 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
330 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
332 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
335 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
337 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
340 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
342 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
345 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
347 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
350 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
352 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
355 int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
356 unsigned long *valuep, enum pci_size_t size)
358 struct dm_pci_ops *ops;
360 ops = pci_get_ops(bus);
361 if (!ops->read_config)
363 return ops->read_config(bus, bdf, offset, valuep, size);
366 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
367 enum pci_size_t size)
372 ret = pci_get_bus(PCI_BUS(bdf), &bus);
376 return pci_bus_read_config(bus, bdf, offset, valuep, size);
379 int dm_pci_read_config(const struct udevice *dev, int offset,
380 unsigned long *valuep, enum pci_size_t size)
382 const struct udevice *bus;
384 for (bus = dev; device_is_on_pci_bus(bus);)
386 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
390 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
395 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
403 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
408 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
416 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
421 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
429 int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep)
434 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
442 int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep)
447 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
455 int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep)
460 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
468 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
473 ret = dm_pci_read_config8(dev, offset, &val);
479 return dm_pci_write_config8(dev, offset, val);
482 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
487 ret = dm_pci_read_config16(dev, offset, &val);
493 return dm_pci_write_config16(dev, offset, val);
496 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
501 ret = dm_pci_read_config32(dev, offset, &val);
507 return dm_pci_write_config32(dev, offset, val);
510 static void set_vga_bridge_bits(struct udevice *dev)
512 struct udevice *parent = dev->parent;
515 while (parent->seq != 0) {
516 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
517 bc |= PCI_BRIDGE_CTL_VGA;
518 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
519 parent = parent->parent;
523 int pci_auto_config_devices(struct udevice *bus)
525 struct pci_controller *hose = bus->uclass_priv;
526 struct pci_child_platdata *pplat;
527 unsigned int sub_bus;
532 debug("%s: start\n", __func__);
533 pciauto_config_init(hose);
534 for (ret = device_find_first_child(bus, &dev);
536 ret = device_find_next_child(&dev)) {
537 unsigned int max_bus;
540 debug("%s: device %s\n", __func__, dev->name);
541 if (dev_read_bool(dev, "pci,no-autoconfig"))
543 ret = dm_pciauto_config_device(dev);
547 sub_bus = max(sub_bus, max_bus);
549 pplat = dev_get_parent_platdata(dev);
550 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
551 set_vga_bridge_bits(dev);
553 debug("%s: done\n", __func__);
558 int pci_generic_mmap_write_config(
559 const struct udevice *bus,
560 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
565 enum pci_size_t size)
569 if (addr_f(bus, bdf, offset, &address) < 0)
574 writeb(value, address);
577 writew(value, address);
580 writel(value, address);
587 int pci_generic_mmap_read_config(
588 const struct udevice *bus,
589 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
594 enum pci_size_t size)
598 if (addr_f(bus, bdf, offset, &address) < 0) {
599 *valuep = pci_get_ff(size);
605 *valuep = readb(address);
608 *valuep = readw(address);
611 *valuep = readl(address);
618 int dm_pci_hose_probe_bus(struct udevice *bus)
623 debug("%s\n", __func__);
625 sub_bus = pci_get_bus_max() + 1;
626 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
627 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
629 ret = device_probe(bus);
631 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
635 if (sub_bus != bus->seq) {
636 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
637 __func__, bus->name, bus->seq, sub_bus);
640 sub_bus = pci_get_bus_max();
641 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
647 * pci_match_one_device - Tell if a PCI device structure has a matching
648 * PCI device id structure
649 * @id: single PCI device id structure to match
650 * @find: the PCI device id structure to match against
652 * Returns true if the finding pci_device_id structure matched or false if
655 static bool pci_match_one_id(const struct pci_device_id *id,
656 const struct pci_device_id *find)
658 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
659 (id->device == PCI_ANY_ID || id->device == find->device) &&
660 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
661 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
662 !((id->class ^ find->class) & id->class_mask))
669 * pci_find_and_bind_driver() - Find and bind the right PCI driver
671 * This only looks at certain fields in the descriptor.
673 * @parent: Parent bus
674 * @find_id: Specification of the driver to find
675 * @bdf: Bus/device/function addreess - see PCI_BDF()
676 * @devp: Returns a pointer to the device created
677 * @return 0 if OK, -EPERM if the device is not needed before relocation and
678 * therefore was not created, other -ve value on error
680 static int pci_find_and_bind_driver(struct udevice *parent,
681 struct pci_device_id *find_id,
682 pci_dev_t bdf, struct udevice **devp)
684 struct pci_driver_entry *start, *entry;
685 ofnode node = ofnode_null();
694 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
695 find_id->vendor, find_id->device);
697 /* Determine optional OF node */
698 pci_dev_find_ofnode(parent, bdf, &node);
700 if (ofnode_valid(node) && !ofnode_is_available(node)) {
701 debug("%s: Ignoring disabled device\n", __func__);
705 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
706 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
707 for (entry = start; entry != start + n_ents; entry++) {
708 const struct pci_device_id *id;
710 const struct driver *drv;
712 for (id = entry->match;
713 id->vendor || id->subvendor || id->class_mask;
715 if (!pci_match_one_id(id, find_id))
721 * In the pre-relocation phase, we only bind devices
722 * whose driver has the DM_FLAG_PRE_RELOC set, to save
723 * precious memory space as on some platforms as that
724 * space is pretty limited (ie: using Cache As RAM).
726 if (!(gd->flags & GD_FLG_RELOC) &&
727 !(drv->flags & DM_FLAG_PRE_RELOC))
731 * We could pass the descriptor to the driver as
732 * platdata (instead of NULL) and allow its bind()
733 * method to return -ENOENT if it doesn't support this
734 * device. That way we could continue the search to
735 * find another driver. For now this doesn't seem
736 * necesssary, so just bind the first match.
738 ret = device_bind_ofnode(parent, drv, drv->name, NULL,
742 debug("%s: Match found: %s\n", __func__, drv->name);
743 dev->driver_data = id->driver_data;
749 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
751 * In the pre-relocation phase, we only bind bridge devices to save
752 * precious memory space as on some platforms as that space is pretty
753 * limited (ie: using Cache As RAM).
755 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
758 /* Bind a generic driver so that the device can be used */
759 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
764 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
766 ret = device_bind_driver_to_node(parent, drv, str, node, devp);
768 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
772 debug("%s: No match found: bound generic driver instead\n", __func__);
777 debug("%s: No match found: error %d\n", __func__, ret);
781 int pci_bind_bus_devices(struct udevice *bus)
783 ulong vendor, device;
790 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
791 PCI_MAX_PCI_FUNCTIONS - 1);
792 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
793 bdf += PCI_BDF(0, 0, 1)) {
794 struct pci_child_platdata *pplat;
800 if (PCI_FUNC(bdf) && !found_multi)
803 /* Check only the first access, we don't expect problems */
804 ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
809 if (vendor == 0xffff || vendor == 0x0000)
812 pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
813 &header_type, PCI_SIZE_8);
816 found_multi = header_type & 0x80;
818 debug("%s: bus %d/%s: found device %x, function %d", __func__,
819 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
820 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
822 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
826 /* Find this device in the device tree */
827 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
828 debug(": find ret=%d\n", ret);
830 /* If nothing in the device tree, bind a device */
831 if (ret == -ENODEV) {
832 struct pci_device_id find_id;
835 memset(&find_id, '\0', sizeof(find_id));
836 find_id.vendor = vendor;
837 find_id.device = device;
838 find_id.class = class;
839 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
840 pci_bus_read_config(bus, bdf,
841 PCI_SUBSYSTEM_VENDOR_ID,
843 find_id.subvendor = val & 0xffff;
844 find_id.subdevice = val >> 16;
846 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
854 /* Update the platform data */
855 pplat = dev_get_parent_platdata(dev);
856 pplat->devfn = PCI_MASK_BUS(bdf);
857 pplat->vendor = vendor;
858 pplat->device = device;
859 pplat->class = class;
864 printf("Cannot read bus configuration: %d\n", ret);
869 static void decode_regions(struct pci_controller *hose, ofnode parent_node,
872 int pci_addr_cells, addr_cells, size_cells;
873 int cells_per_record;
878 prop = ofnode_get_property(node, "ranges", &len);
880 debug("%s: Cannot decode regions\n", __func__);
884 pci_addr_cells = ofnode_read_simple_addr_cells(node);
885 addr_cells = ofnode_read_simple_addr_cells(parent_node);
886 size_cells = ofnode_read_simple_size_cells(node);
888 /* PCI addresses are always 3-cells */
890 cells_per_record = pci_addr_cells + addr_cells + size_cells;
891 hose->region_count = 0;
892 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
894 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
895 u64 pci_addr, addr, size;
901 if (len < cells_per_record)
903 flags = fdt32_to_cpu(prop[0]);
904 space_code = (flags >> 24) & 3;
905 pci_addr = fdtdec_get_number(prop + 1, 2);
906 prop += pci_addr_cells;
907 addr = fdtdec_get_number(prop, addr_cells);
909 size = fdtdec_get_number(prop, size_cells);
911 debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
912 __func__, hose->region_count, pci_addr, addr, size, space_code);
913 if (space_code & 2) {
914 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
916 } else if (space_code & 1) {
917 type = PCI_REGION_IO;
922 if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
923 type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
924 debug(" - beyond the 32-bit boundary, ignoring\n");
929 for (i = 0; i < hose->region_count; i++) {
930 if (hose->regions[i].flags == type)
934 pos = hose->region_count++;
935 debug(" - type=%d, pos=%d\n", type, pos);
936 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
939 /* Add a region for our local memory */
940 #ifdef CONFIG_NR_DRAM_BANKS
946 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
947 if (hose->region_count == MAX_PCI_REGIONS) {
948 pr_err("maximum number of regions parsed, aborting\n");
952 if (bd->bi_dram[i].size) {
953 pci_set_region(hose->regions + hose->region_count++,
954 bd->bi_dram[i].start,
955 bd->bi_dram[i].start,
957 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
961 phys_addr_t base = 0, size;
964 #ifdef CONFIG_SYS_SDRAM_BASE
965 base = CONFIG_SYS_SDRAM_BASE;
967 if (gd->pci_ram_top && gd->pci_ram_top < base + size)
968 size = gd->pci_ram_top - base;
970 pci_set_region(hose->regions + hose->region_count++, base,
971 base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
977 static int pci_uclass_pre_probe(struct udevice *bus)
979 struct pci_controller *hose;
981 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
983 hose = bus->uclass_priv;
985 /* For bridges, use the top-level PCI controller */
986 if (!device_is_on_pci_bus(bus)) {
988 decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
990 struct pci_controller *parent_hose;
992 parent_hose = dev_get_uclass_priv(bus->parent);
993 hose->ctlr = parent_hose->bus;
996 hose->first_busno = bus->seq;
997 hose->last_busno = bus->seq;
998 hose->skip_auto_config_until_reloc =
999 dev_read_bool(bus, "u-boot,skip-auto-config-until-reloc");
1004 static int pci_uclass_post_probe(struct udevice *bus)
1006 struct pci_controller *hose = dev_get_uclass_priv(bus);
1009 debug("%s: probing bus %d\n", __func__, bus->seq);
1010 ret = pci_bind_bus_devices(bus);
1014 if (CONFIG_IS_ENABLED(PCI_PNP) && ll_boot_init() &&
1015 (!hose->skip_auto_config_until_reloc ||
1016 (gd->flags & GD_FLG_RELOC))) {
1017 ret = pci_auto_config_devices(bus);
1019 return log_msg_ret("pci auto-config", ret);
1022 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
1024 * Per Intel FSP specification, we should call FSP notify API to
1025 * inform FSP that PCI enumeration has been done so that FSP will
1026 * do any necessary initialization as required by the chipset's
1027 * BIOS Writer's Guide (BWG).
1029 * Unfortunately we have to put this call here as with driver model,
1030 * the enumeration is all done on a lazy basis as needed, so until
1031 * something is touched on PCI it won't happen.
1033 * Note we only call this 1) after U-Boot is relocated, and 2)
1034 * root bus has finished probing.
1036 if ((gd->flags & GD_FLG_RELOC) && bus->seq == 0 && ll_boot_init()) {
1037 ret = fsp_init_phase_pci();
1046 static int pci_uclass_child_post_bind(struct udevice *dev)
1048 struct pci_child_platdata *pplat;
1050 if (!dev_of_valid(dev))
1053 pplat = dev_get_parent_platdata(dev);
1055 /* Extract vendor id and device id if available */
1056 ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
1058 /* Extract the devfn from fdt_pci_addr */
1059 pplat->devfn = pci_get_devfn(dev);
1064 static int pci_bridge_read_config(const struct udevice *bus, pci_dev_t bdf,
1065 uint offset, ulong *valuep,
1066 enum pci_size_t size)
1068 struct pci_controller *hose = bus->uclass_priv;
1070 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
1073 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
1074 uint offset, ulong value,
1075 enum pci_size_t size)
1077 struct pci_controller *hose = bus->uclass_priv;
1079 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
1082 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
1084 struct udevice *dev;
1088 * Scan through all the PCI controllers. On x86 there will only be one
1089 * but that is not necessarily true on other hardware.
1092 device_find_first_child(bus, &dev);
1097 ret = uclass_next_device(&bus);
1105 int pci_find_next_device(struct udevice **devp)
1107 struct udevice *child = *devp;
1108 struct udevice *bus = child->parent;
1111 /* First try all the siblings */
1114 device_find_next_child(&child);
1121 /* We ran out of siblings. Try the next bus */
1122 ret = uclass_next_device(&bus);
1126 return bus ? skip_to_next_device(bus, devp) : 0;
1129 int pci_find_first_device(struct udevice **devp)
1131 struct udevice *bus;
1135 ret = uclass_first_device(UCLASS_PCI, &bus);
1139 return skip_to_next_device(bus, devp);
1142 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1146 return (value >> ((offset & 3) * 8)) & 0xff;
1148 return (value >> ((offset & 2) * 8)) & 0xffff;
1154 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1155 enum pci_size_t size)
1158 uint val_mask, shift;
1173 shift = (offset & off_mask) * 8;
1174 ldata = (value & val_mask) << shift;
1175 mask = val_mask << shift;
1176 value = (old & ~mask) | ldata;
1181 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1182 struct pci_region **memp, struct pci_region **prefp)
1184 struct udevice *bus = pci_get_controller(dev);
1185 struct pci_controller *hose = dev_get_uclass_priv(bus);
1191 for (i = 0; i < hose->region_count; i++) {
1192 switch (hose->regions[i].flags) {
1194 if (!*iop || (*iop)->size < hose->regions[i].size)
1195 *iop = hose->regions + i;
1197 case PCI_REGION_MEM:
1198 if (!*memp || (*memp)->size < hose->regions[i].size)
1199 *memp = hose->regions + i;
1201 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1202 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1203 *prefp = hose->regions + i;
1208 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1211 u32 dm_pci_read_bar32(const struct udevice *dev, int barnum)
1216 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1217 dm_pci_read_config32(dev, bar, &addr);
1220 * If we get an invalid address, return this so that comparisons with
1221 * FDT_ADDR_T_NONE work correctly
1223 if (addr == 0xffffffff)
1225 else if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1226 return addr & PCI_BASE_ADDRESS_IO_MASK;
1228 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1231 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1235 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1236 dm_pci_write_config32(dev, bar, addr);
1239 static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1240 pci_addr_t bus_addr, unsigned long flags,
1241 unsigned long skip_mask, phys_addr_t *pa)
1243 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1244 struct pci_region *res;
1247 if (hose->region_count == 0) {
1252 for (i = 0; i < hose->region_count; i++) {
1253 res = &hose->regions[i];
1255 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1258 if (res->flags & skip_mask)
1261 if (bus_addr >= res->bus_start &&
1262 (bus_addr - res->bus_start) < res->size) {
1263 *pa = (bus_addr - res->bus_start + res->phys_start);
1271 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1272 unsigned long flags)
1274 phys_addr_t phys_addr = 0;
1275 struct udevice *ctlr;
1278 /* The root controller has the region information */
1279 ctlr = pci_get_controller(dev);
1282 * if PCI_REGION_MEM is set we do a two pass search with preference
1283 * on matches that don't have PCI_REGION_SYS_MEMORY set
1285 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1286 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1287 flags, PCI_REGION_SYS_MEMORY,
1293 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1296 puts("pci_hose_bus_to_phys: invalid physical address\n");
1301 int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1302 unsigned long flags, unsigned long skip_mask,
1305 struct pci_region *res;
1306 struct udevice *ctlr;
1307 pci_addr_t bus_addr;
1309 struct pci_controller *hose;
1311 /* The root controller has the region information */
1312 ctlr = pci_get_controller(dev);
1313 hose = dev_get_uclass_priv(ctlr);
1315 if (hose->region_count == 0) {
1320 for (i = 0; i < hose->region_count; i++) {
1321 res = &hose->regions[i];
1323 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1326 if (res->flags & skip_mask)
1329 bus_addr = phys_addr - res->phys_start + res->bus_start;
1331 if (bus_addr >= res->bus_start &&
1332 (bus_addr - res->bus_start) < res->size) {
1341 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1342 unsigned long flags)
1344 pci_addr_t bus_addr = 0;
1348 * if PCI_REGION_MEM is set we do a two pass search with preference
1349 * on matches that don't have PCI_REGION_SYS_MEMORY set
1351 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1352 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1353 PCI_REGION_SYS_MEMORY, &bus_addr);
1358 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1361 puts("pci_hose_phys_to_bus: invalid physical address\n");
1366 static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
1369 int ea_cnt, i, entry_size;
1370 int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
1374 /* EA capability structure header */
1375 dm_pci_read_config32(dev, ea_off, &ea_entry);
1376 ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
1377 ea_off += PCI_EA_FIRST_ENT;
1379 for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
1381 dm_pci_read_config32(dev, ea_off, &ea_entry);
1382 entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
1384 if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
1387 /* Base address, 1st DW */
1388 dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
1389 addr = ea_entry & PCI_EA_FIELD_MASK;
1390 if (ea_entry & PCI_EA_IS_64) {
1391 /* Base address, 2nd DW, skip over 4B MaxOffset */
1392 dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
1393 addr |= ((u64)ea_entry) << 32;
1396 /* size ignored for now */
1397 return map_physmem(addr, flags, 0);
1403 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1405 pci_addr_t pci_bus_addr;
1410 * if the function supports Enhanced Allocation use that instead of
1413 ea_off = dm_pci_find_capability(dev, PCI_CAP_ID_EA);
1415 return dm_pci_map_ea_bar(dev, bar, flags, ea_off);
1417 /* read BAR address */
1418 dm_pci_read_config32(dev, bar, &bar_response);
1419 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1422 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1423 * isn't actualy used on any platform because u-boot assumes a static
1424 * linear mapping. In the future, this could read the BAR size
1425 * and pass that as the size if needed.
1427 return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1430 static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
1432 int ttl = PCI_FIND_CAP_TTL;
1436 dm_pci_read_config8(dev, pos, &pos);
1439 if (pos < PCI_STD_HEADER_SIZEOF)
1442 dm_pci_read_config16(dev, pos, &ent);
1455 int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap)
1457 return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT,
1461 int dm_pci_find_capability(struct udevice *dev, int cap)
1467 dm_pci_read_config16(dev, PCI_STATUS, &status);
1468 if (!(status & PCI_STATUS_CAP_LIST))
1471 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
1472 if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
1473 pos = PCI_CB_CAPABILITY_LIST;
1475 pos = PCI_CAPABILITY_LIST;
1477 return _dm_pci_find_next_capability(dev, pos, cap);
1480 int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap)
1484 int pos = PCI_CFG_SPACE_SIZE;
1486 /* minimum 8 bytes per capability */
1487 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1492 dm_pci_read_config32(dev, pos, &header);
1494 * If we have no capabilities, this is indicated by cap ID,
1495 * cap version and next pointer all being 0.
1501 if (PCI_EXT_CAP_ID(header) == cap)
1504 pos = PCI_EXT_CAP_NEXT(header);
1505 if (pos < PCI_CFG_SPACE_SIZE)
1508 dm_pci_read_config32(dev, pos, &header);
1514 int dm_pci_find_ext_capability(struct udevice *dev, int cap)
1516 return dm_pci_find_next_ext_capability(dev, 0, cap);
1519 int dm_pci_flr(struct udevice *dev)
1524 /* look for PCI Express Capability */
1525 pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
1529 /* check FLR capability */
1530 dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap);
1531 if (!(cap & PCI_EXP_DEVCAP_FLR))
1534 dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0,
1535 PCI_EXP_DEVCTL_BCR_FLR);
1537 /* wait 100ms, per PCI spec */
1543 UCLASS_DRIVER(pci) = {
1546 .flags = DM_UC_FLAG_SEQ_ALIAS,
1547 .post_bind = dm_scan_fdt_dev,
1548 .pre_probe = pci_uclass_pre_probe,
1549 .post_probe = pci_uclass_post_probe,
1550 .child_post_bind = pci_uclass_child_post_bind,
1551 .per_device_auto_alloc_size = sizeof(struct pci_controller),
1552 .per_child_platdata_auto_alloc_size =
1553 sizeof(struct pci_child_platdata),
1556 static const struct dm_pci_ops pci_bridge_ops = {
1557 .read_config = pci_bridge_read_config,
1558 .write_config = pci_bridge_write_config,
1561 static const struct udevice_id pci_bridge_ids[] = {
1562 { .compatible = "pci-bridge" },
1566 U_BOOT_DRIVER(pci_bridge_drv) = {
1567 .name = "pci_bridge_drv",
1569 .of_match = pci_bridge_ids,
1570 .ops = &pci_bridge_ops,
1573 UCLASS_DRIVER(pci_generic) = {
1574 .id = UCLASS_PCI_GENERIC,
1575 .name = "pci_generic",
1578 static const struct udevice_id pci_generic_ids[] = {
1579 { .compatible = "pci-generic" },
1583 U_BOOT_DRIVER(pci_generic_drv) = {
1584 .name = "pci_generic_drv",
1585 .id = UCLASS_PCI_GENERIC,
1586 .of_match = pci_generic_ids,
1591 struct udevice *bus;
1594 * Enumerate all known controller devices. Enumeration has the side-
1595 * effect of probing them, so PCIe devices will be enumerated too.
1597 for (uclass_first_device_check(UCLASS_PCI, &bus);
1599 uclass_next_device_check(&bus)) {