1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2014 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
12 #include <dm/device-internal.h>
14 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
15 #include <asm/fsp/fsp_support.h>
17 #include "pci_internal.h"
19 DECLARE_GLOBAL_DATA_PTR;
21 int pci_get_bus(int busnum, struct udevice **busp)
25 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
27 /* Since buses may not be numbered yet try a little harder with bus 0 */
29 ret = uclass_first_device_err(UCLASS_PCI, busp);
32 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
38 struct udevice *pci_get_controller(struct udevice *dev)
40 while (device_is_on_pci_bus(dev))
46 pci_dev_t dm_pci_get_bdf(struct udevice *dev)
48 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
49 struct udevice *bus = dev->parent;
52 * This error indicates that @dev is a device on an unprobed PCI bus.
53 * The bus likely has bus=seq == -1, so the PCI_ADD_BUS() macro below
54 * will produce a bad BDF>
56 * A common cause of this problem is that this function is called in the
57 * ofdata_to_platdata() method of @dev. Accessing the PCI bus in that
58 * method is not allowed, since it has not yet been probed. To fix this,
59 * move that access to the probe() method of @dev instead.
61 if (!device_active(bus))
62 log_err("PCI: Device '%s' on unprobed bus '%s'\n", dev->name,
64 return PCI_ADD_BUS(bus->seq, pplat->devfn);
68 * pci_get_bus_max() - returns the bus number of the last active bus
70 * @return last bus number, or -1 if no active buses
72 static int pci_get_bus_max(void)
78 ret = uclass_get(UCLASS_PCI, &uc);
79 uclass_foreach_dev(bus, uc) {
84 debug("%s: ret=%d\n", __func__, ret);
89 int pci_last_busno(void)
91 return pci_get_bus_max();
94 int pci_get_ff(enum pci_size_t size)
106 static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
109 struct fdt_pci_addr addr;
113 dev_for_each_subnode(node, bus) {
114 ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
119 if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
127 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
128 struct udevice **devp)
132 for (device_find_first_child(bus, &dev);
134 device_find_next_child(&dev)) {
135 struct pci_child_platdata *pplat;
137 pplat = dev_get_parent_platdata(dev);
138 if (pplat && pplat->devfn == find_devfn) {
147 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
152 ret = pci_get_bus(PCI_BUS(bdf), &bus);
155 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
158 static int pci_device_matches_ids(struct udevice *dev,
159 struct pci_device_id *ids)
161 struct pci_child_platdata *pplat;
164 pplat = dev_get_parent_platdata(dev);
167 for (i = 0; ids[i].vendor != 0; i++) {
168 if (pplat->vendor == ids[i].vendor &&
169 pplat->device == ids[i].device)
176 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
177 int *indexp, struct udevice **devp)
181 /* Scan all devices on this bus */
182 for (device_find_first_child(bus, &dev);
184 device_find_next_child(&dev)) {
185 if (pci_device_matches_ids(dev, ids) >= 0) {
186 if ((*indexp)-- <= 0) {
196 int pci_find_device_id(struct pci_device_id *ids, int index,
197 struct udevice **devp)
201 /* Scan all known buses */
202 for (uclass_first_device(UCLASS_PCI, &bus);
204 uclass_next_device(&bus)) {
205 if (!pci_bus_find_devices(bus, ids, &index, devp))
213 static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
214 unsigned int device, int *indexp,
215 struct udevice **devp)
217 struct pci_child_platdata *pplat;
220 for (device_find_first_child(bus, &dev);
222 device_find_next_child(&dev)) {
223 pplat = dev_get_parent_platdata(dev);
224 if (pplat->vendor == vendor && pplat->device == device) {
235 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
236 struct udevice **devp)
240 /* Scan all known buses */
241 for (uclass_first_device(UCLASS_PCI, &bus);
243 uclass_next_device(&bus)) {
244 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
245 return device_probe(*devp);
252 int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
256 /* Scan all known buses */
257 for (pci_find_first_device(&dev);
259 pci_find_next_device(&dev)) {
260 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
262 if (pplat->class == find_class && !index--) {
264 return device_probe(*devp);
272 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
273 unsigned long value, enum pci_size_t size)
275 struct dm_pci_ops *ops;
277 ops = pci_get_ops(bus);
278 if (!ops->write_config)
280 return ops->write_config(bus, bdf, offset, value, size);
283 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
289 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
295 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
298 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
299 enum pci_size_t size)
304 ret = pci_get_bus(PCI_BUS(bdf), &bus);
308 return pci_bus_write_config(bus, bdf, offset, value, size);
311 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
312 enum pci_size_t size)
316 for (bus = dev; device_is_on_pci_bus(bus);)
318 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
322 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
324 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
327 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
329 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
332 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
334 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
337 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
339 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
342 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
344 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
347 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
349 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
352 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
353 unsigned long *valuep, enum pci_size_t size)
355 struct dm_pci_ops *ops;
357 ops = pci_get_ops(bus);
358 if (!ops->read_config)
360 return ops->read_config(bus, bdf, offset, valuep, size);
363 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
364 enum pci_size_t size)
369 ret = pci_get_bus(PCI_BUS(bdf), &bus);
373 return pci_bus_read_config(bus, bdf, offset, valuep, size);
376 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
377 enum pci_size_t size)
381 for (bus = dev; device_is_on_pci_bus(bus);)
383 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
387 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
392 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
400 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
405 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
413 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
418 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
426 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
431 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
439 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
444 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
452 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
457 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
465 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
470 ret = dm_pci_read_config8(dev, offset, &val);
476 return dm_pci_write_config8(dev, offset, val);
479 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
484 ret = dm_pci_read_config16(dev, offset, &val);
490 return dm_pci_write_config16(dev, offset, val);
493 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
498 ret = dm_pci_read_config32(dev, offset, &val);
504 return dm_pci_write_config32(dev, offset, val);
507 static void set_vga_bridge_bits(struct udevice *dev)
509 struct udevice *parent = dev->parent;
512 while (parent->seq != 0) {
513 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
514 bc |= PCI_BRIDGE_CTL_VGA;
515 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
516 parent = parent->parent;
520 int pci_auto_config_devices(struct udevice *bus)
522 struct pci_controller *hose = bus->uclass_priv;
523 struct pci_child_platdata *pplat;
524 unsigned int sub_bus;
529 debug("%s: start\n", __func__);
530 pciauto_config_init(hose);
531 for (ret = device_find_first_child(bus, &dev);
533 ret = device_find_next_child(&dev)) {
534 unsigned int max_bus;
537 debug("%s: device %s\n", __func__, dev->name);
538 ret = dm_pciauto_config_device(dev);
542 sub_bus = max(sub_bus, max_bus);
544 pplat = dev_get_parent_platdata(dev);
545 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
546 set_vga_bridge_bits(dev);
548 debug("%s: done\n", __func__);
553 int pci_generic_mmap_write_config(
555 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
559 enum pci_size_t size)
563 if (addr_f(bus, bdf, offset, &address) < 0)
568 writeb(value, address);
571 writew(value, address);
574 writel(value, address);
581 int pci_generic_mmap_read_config(
583 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
587 enum pci_size_t size)
591 if (addr_f(bus, bdf, offset, &address) < 0) {
592 *valuep = pci_get_ff(size);
598 *valuep = readb(address);
601 *valuep = readw(address);
604 *valuep = readl(address);
611 int dm_pci_hose_probe_bus(struct udevice *bus)
616 debug("%s\n", __func__);
618 sub_bus = pci_get_bus_max() + 1;
619 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
620 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
622 ret = device_probe(bus);
624 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
628 if (sub_bus != bus->seq) {
629 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
630 __func__, bus->name, bus->seq, sub_bus);
633 sub_bus = pci_get_bus_max();
634 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
640 * pci_match_one_device - Tell if a PCI device structure has a matching
641 * PCI device id structure
642 * @id: single PCI device id structure to match
643 * @find: the PCI device id structure to match against
645 * Returns true if the finding pci_device_id structure matched or false if
648 static bool pci_match_one_id(const struct pci_device_id *id,
649 const struct pci_device_id *find)
651 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
652 (id->device == PCI_ANY_ID || id->device == find->device) &&
653 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
654 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
655 !((id->class ^ find->class) & id->class_mask))
662 * pci_find_and_bind_driver() - Find and bind the right PCI driver
664 * This only looks at certain fields in the descriptor.
666 * @parent: Parent bus
667 * @find_id: Specification of the driver to find
668 * @bdf: Bus/device/function addreess - see PCI_BDF()
669 * @devp: Returns a pointer to the device created
670 * @return 0 if OK, -EPERM if the device is not needed before relocation and
671 * therefore was not created, other -ve value on error
673 static int pci_find_and_bind_driver(struct udevice *parent,
674 struct pci_device_id *find_id,
675 pci_dev_t bdf, struct udevice **devp)
677 struct pci_driver_entry *start, *entry;
678 ofnode node = ofnode_null();
687 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
688 find_id->vendor, find_id->device);
690 /* Determine optional OF node */
691 pci_dev_find_ofnode(parent, bdf, &node);
693 if (ofnode_valid(node) && !ofnode_is_available(node)) {
694 debug("%s: Ignoring disabled device\n", __func__);
698 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
699 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
700 for (entry = start; entry != start + n_ents; entry++) {
701 const struct pci_device_id *id;
703 const struct driver *drv;
705 for (id = entry->match;
706 id->vendor || id->subvendor || id->class_mask;
708 if (!pci_match_one_id(id, find_id))
714 * In the pre-relocation phase, we only bind devices
715 * whose driver has the DM_FLAG_PRE_RELOC set, to save
716 * precious memory space as on some platforms as that
717 * space is pretty limited (ie: using Cache As RAM).
719 if (!(gd->flags & GD_FLG_RELOC) &&
720 !(drv->flags & DM_FLAG_PRE_RELOC))
724 * We could pass the descriptor to the driver as
725 * platdata (instead of NULL) and allow its bind()
726 * method to return -ENOENT if it doesn't support this
727 * device. That way we could continue the search to
728 * find another driver. For now this doesn't seem
729 * necesssary, so just bind the first match.
731 ret = device_bind_ofnode(parent, drv, drv->name, NULL,
735 debug("%s: Match found: %s\n", __func__, drv->name);
736 dev->driver_data = id->driver_data;
742 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
744 * In the pre-relocation phase, we only bind bridge devices to save
745 * precious memory space as on some platforms as that space is pretty
746 * limited (ie: using Cache As RAM).
748 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
751 /* Bind a generic driver so that the device can be used */
752 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
757 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
759 ret = device_bind_driver_to_node(parent, drv, str, node, devp);
761 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
765 debug("%s: No match found: bound generic driver instead\n", __func__);
770 debug("%s: No match found: error %d\n", __func__, ret);
774 int pci_bind_bus_devices(struct udevice *bus)
776 ulong vendor, device;
783 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
784 PCI_MAX_PCI_FUNCTIONS - 1);
785 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
786 bdf += PCI_BDF(0, 0, 1)) {
787 struct pci_child_platdata *pplat;
793 if (PCI_FUNC(bdf) && !found_multi)
796 /* Check only the first access, we don't expect problems */
797 ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
802 if (vendor == 0xffff || vendor == 0x0000)
805 pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
806 &header_type, PCI_SIZE_8);
809 found_multi = header_type & 0x80;
811 debug("%s: bus %d/%s: found device %x, function %d", __func__,
812 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
813 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
815 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
819 /* Find this device in the device tree */
820 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
821 debug(": find ret=%d\n", ret);
823 /* If nothing in the device tree, bind a device */
824 if (ret == -ENODEV) {
825 struct pci_device_id find_id;
828 memset(&find_id, '\0', sizeof(find_id));
829 find_id.vendor = vendor;
830 find_id.device = device;
831 find_id.class = class;
832 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
833 pci_bus_read_config(bus, bdf,
834 PCI_SUBSYSTEM_VENDOR_ID,
836 find_id.subvendor = val & 0xffff;
837 find_id.subdevice = val >> 16;
839 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
847 /* Update the platform data */
848 pplat = dev_get_parent_platdata(dev);
849 pplat->devfn = PCI_MASK_BUS(bdf);
850 pplat->vendor = vendor;
851 pplat->device = device;
852 pplat->class = class;
857 printf("Cannot read bus configuration: %d\n", ret);
862 static void decode_regions(struct pci_controller *hose, ofnode parent_node,
865 int pci_addr_cells, addr_cells, size_cells;
866 int cells_per_record;
871 prop = ofnode_get_property(node, "ranges", &len);
873 debug("%s: Cannot decode regions\n", __func__);
877 pci_addr_cells = ofnode_read_simple_addr_cells(node);
878 addr_cells = ofnode_read_simple_addr_cells(parent_node);
879 size_cells = ofnode_read_simple_size_cells(node);
881 /* PCI addresses are always 3-cells */
883 cells_per_record = pci_addr_cells + addr_cells + size_cells;
884 hose->region_count = 0;
885 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
887 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
888 u64 pci_addr, addr, size;
894 if (len < cells_per_record)
896 flags = fdt32_to_cpu(prop[0]);
897 space_code = (flags >> 24) & 3;
898 pci_addr = fdtdec_get_number(prop + 1, 2);
899 prop += pci_addr_cells;
900 addr = fdtdec_get_number(prop, addr_cells);
902 size = fdtdec_get_number(prop, size_cells);
904 debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
905 __func__, hose->region_count, pci_addr, addr, size, space_code);
906 if (space_code & 2) {
907 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
909 } else if (space_code & 1) {
910 type = PCI_REGION_IO;
915 if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
916 type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
917 debug(" - beyond the 32-bit boundary, ignoring\n");
922 for (i = 0; i < hose->region_count; i++) {
923 if (hose->regions[i].flags == type)
927 pos = hose->region_count++;
928 debug(" - type=%d, pos=%d\n", type, pos);
929 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
932 /* Add a region for our local memory */
933 #ifdef CONFIG_NR_DRAM_BANKS
939 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
940 if (hose->region_count == MAX_PCI_REGIONS) {
941 pr_err("maximum number of regions parsed, aborting\n");
945 if (bd->bi_dram[i].size) {
946 pci_set_region(hose->regions + hose->region_count++,
947 bd->bi_dram[i].start,
948 bd->bi_dram[i].start,
950 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
954 phys_addr_t base = 0, size;
957 #ifdef CONFIG_SYS_SDRAM_BASE
958 base = CONFIG_SYS_SDRAM_BASE;
960 if (gd->pci_ram_top && gd->pci_ram_top < base + size)
961 size = gd->pci_ram_top - base;
963 pci_set_region(hose->regions + hose->region_count++, base,
964 base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
970 static int pci_uclass_pre_probe(struct udevice *bus)
972 struct pci_controller *hose;
974 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
976 hose = bus->uclass_priv;
978 /* For bridges, use the top-level PCI controller */
979 if (!device_is_on_pci_bus(bus)) {
981 decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
983 struct pci_controller *parent_hose;
985 parent_hose = dev_get_uclass_priv(bus->parent);
986 hose->ctlr = parent_hose->bus;
989 hose->first_busno = bus->seq;
990 hose->last_busno = bus->seq;
991 hose->skip_auto_config_until_reloc =
992 dev_read_bool(bus, "u-boot,skip-auto-config-until-reloc");
997 static int pci_uclass_post_probe(struct udevice *bus)
999 struct pci_controller *hose = dev_get_uclass_priv(bus);
1002 debug("%s: probing bus %d\n", __func__, bus->seq);
1003 ret = pci_bind_bus_devices(bus);
1007 if (CONFIG_IS_ENABLED(PCI_PNP) &&
1008 (!hose->skip_auto_config_until_reloc ||
1009 (gd->flags & GD_FLG_RELOC))) {
1010 ret = pci_auto_config_devices(bus);
1012 return log_msg_ret("pci auto-config", ret);
1015 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
1017 * Per Intel FSP specification, we should call FSP notify API to
1018 * inform FSP that PCI enumeration has been done so that FSP will
1019 * do any necessary initialization as required by the chipset's
1020 * BIOS Writer's Guide (BWG).
1022 * Unfortunately we have to put this call here as with driver model,
1023 * the enumeration is all done on a lazy basis as needed, so until
1024 * something is touched on PCI it won't happen.
1026 * Note we only call this 1) after U-Boot is relocated, and 2)
1027 * root bus has finished probing.
1029 if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
1030 ret = fsp_init_phase_pci();
1039 static int pci_uclass_child_post_bind(struct udevice *dev)
1041 struct pci_child_platdata *pplat;
1043 if (!dev_of_valid(dev))
1046 pplat = dev_get_parent_platdata(dev);
1048 /* Extract vendor id and device id if available */
1049 ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
1051 /* Extract the devfn from fdt_pci_addr */
1052 pplat->devfn = pci_get_devfn(dev);
1057 static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
1058 uint offset, ulong *valuep,
1059 enum pci_size_t size)
1061 struct pci_controller *hose = bus->uclass_priv;
1063 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
1066 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
1067 uint offset, ulong value,
1068 enum pci_size_t size)
1070 struct pci_controller *hose = bus->uclass_priv;
1072 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
1075 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
1077 struct udevice *dev;
1081 * Scan through all the PCI controllers. On x86 there will only be one
1082 * but that is not necessarily true on other hardware.
1085 device_find_first_child(bus, &dev);
1090 ret = uclass_next_device(&bus);
1098 int pci_find_next_device(struct udevice **devp)
1100 struct udevice *child = *devp;
1101 struct udevice *bus = child->parent;
1104 /* First try all the siblings */
1107 device_find_next_child(&child);
1114 /* We ran out of siblings. Try the next bus */
1115 ret = uclass_next_device(&bus);
1119 return bus ? skip_to_next_device(bus, devp) : 0;
1122 int pci_find_first_device(struct udevice **devp)
1124 struct udevice *bus;
1128 ret = uclass_first_device(UCLASS_PCI, &bus);
1132 return skip_to_next_device(bus, devp);
1135 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1139 return (value >> ((offset & 3) * 8)) & 0xff;
1141 return (value >> ((offset & 2) * 8)) & 0xffff;
1147 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1148 enum pci_size_t size)
1151 uint val_mask, shift;
1166 shift = (offset & off_mask) * 8;
1167 ldata = (value & val_mask) << shift;
1168 mask = val_mask << shift;
1169 value = (old & ~mask) | ldata;
1174 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1175 struct pci_region **memp, struct pci_region **prefp)
1177 struct udevice *bus = pci_get_controller(dev);
1178 struct pci_controller *hose = dev_get_uclass_priv(bus);
1184 for (i = 0; i < hose->region_count; i++) {
1185 switch (hose->regions[i].flags) {
1187 if (!*iop || (*iop)->size < hose->regions[i].size)
1188 *iop = hose->regions + i;
1190 case PCI_REGION_MEM:
1191 if (!*memp || (*memp)->size < hose->regions[i].size)
1192 *memp = hose->regions + i;
1194 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1195 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1196 *prefp = hose->regions + i;
1201 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1204 u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
1209 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1210 dm_pci_read_config32(dev, bar, &addr);
1211 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1212 return addr & PCI_BASE_ADDRESS_IO_MASK;
1214 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1217 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1221 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1222 dm_pci_write_config32(dev, bar, addr);
1225 static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1226 pci_addr_t bus_addr, unsigned long flags,
1227 unsigned long skip_mask, phys_addr_t *pa)
1229 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1230 struct pci_region *res;
1233 if (hose->region_count == 0) {
1238 for (i = 0; i < hose->region_count; i++) {
1239 res = &hose->regions[i];
1241 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1244 if (res->flags & skip_mask)
1247 if (bus_addr >= res->bus_start &&
1248 (bus_addr - res->bus_start) < res->size) {
1249 *pa = (bus_addr - res->bus_start + res->phys_start);
1257 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1258 unsigned long flags)
1260 phys_addr_t phys_addr = 0;
1261 struct udevice *ctlr;
1264 /* The root controller has the region information */
1265 ctlr = pci_get_controller(dev);
1268 * if PCI_REGION_MEM is set we do a two pass search with preference
1269 * on matches that don't have PCI_REGION_SYS_MEMORY set
1271 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1272 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1273 flags, PCI_REGION_SYS_MEMORY,
1279 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1282 puts("pci_hose_bus_to_phys: invalid physical address\n");
1287 int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1288 unsigned long flags, unsigned long skip_mask,
1291 struct pci_region *res;
1292 struct udevice *ctlr;
1293 pci_addr_t bus_addr;
1295 struct pci_controller *hose;
1297 /* The root controller has the region information */
1298 ctlr = pci_get_controller(dev);
1299 hose = dev_get_uclass_priv(ctlr);
1301 if (hose->region_count == 0) {
1306 for (i = 0; i < hose->region_count; i++) {
1307 res = &hose->regions[i];
1309 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1312 if (res->flags & skip_mask)
1315 bus_addr = phys_addr - res->phys_start + res->bus_start;
1317 if (bus_addr >= res->bus_start &&
1318 (bus_addr - res->bus_start) < res->size) {
1327 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1328 unsigned long flags)
1330 pci_addr_t bus_addr = 0;
1334 * if PCI_REGION_MEM is set we do a two pass search with preference
1335 * on matches that don't have PCI_REGION_SYS_MEMORY set
1337 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1338 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1339 PCI_REGION_SYS_MEMORY, &bus_addr);
1344 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1347 puts("pci_hose_phys_to_bus: invalid physical address\n");
1352 static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
1355 int ea_cnt, i, entry_size;
1356 int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
1360 /* EA capability structure header */
1361 dm_pci_read_config32(dev, ea_off, &ea_entry);
1362 ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
1363 ea_off += PCI_EA_FIRST_ENT;
1365 for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
1367 dm_pci_read_config32(dev, ea_off, &ea_entry);
1368 entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
1370 if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
1373 /* Base address, 1st DW */
1374 dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
1375 addr = ea_entry & PCI_EA_FIELD_MASK;
1376 if (ea_entry & PCI_EA_IS_64) {
1377 /* Base address, 2nd DW, skip over 4B MaxOffset */
1378 dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
1379 addr |= ((u64)ea_entry) << 32;
1382 /* size ignored for now */
1383 return map_physmem(addr, flags, 0);
1389 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1391 pci_addr_t pci_bus_addr;
1396 * if the function supports Enhanced Allocation use that instead of
1399 ea_off = dm_pci_find_capability(dev, PCI_CAP_ID_EA);
1401 return dm_pci_map_ea_bar(dev, bar, flags, ea_off);
1403 /* read BAR address */
1404 dm_pci_read_config32(dev, bar, &bar_response);
1405 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1408 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1409 * isn't actualy used on any platform because u-boot assumes a static
1410 * linear mapping. In the future, this could read the BAR size
1411 * and pass that as the size if needed.
1413 return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1416 static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
1418 int ttl = PCI_FIND_CAP_TTL;
1422 dm_pci_read_config8(dev, pos, &pos);
1425 if (pos < PCI_STD_HEADER_SIZEOF)
1428 dm_pci_read_config16(dev, pos, &ent);
1441 int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap)
1443 return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT,
1447 int dm_pci_find_capability(struct udevice *dev, int cap)
1453 dm_pci_read_config16(dev, PCI_STATUS, &status);
1454 if (!(status & PCI_STATUS_CAP_LIST))
1457 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
1458 if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
1459 pos = PCI_CB_CAPABILITY_LIST;
1461 pos = PCI_CAPABILITY_LIST;
1463 return _dm_pci_find_next_capability(dev, pos, cap);
1466 int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap)
1470 int pos = PCI_CFG_SPACE_SIZE;
1472 /* minimum 8 bytes per capability */
1473 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1478 dm_pci_read_config32(dev, pos, &header);
1480 * If we have no capabilities, this is indicated by cap ID,
1481 * cap version and next pointer all being 0.
1487 if (PCI_EXT_CAP_ID(header) == cap)
1490 pos = PCI_EXT_CAP_NEXT(header);
1491 if (pos < PCI_CFG_SPACE_SIZE)
1494 dm_pci_read_config32(dev, pos, &header);
1500 int dm_pci_find_ext_capability(struct udevice *dev, int cap)
1502 return dm_pci_find_next_ext_capability(dev, 0, cap);
1505 int dm_pci_flr(struct udevice *dev)
1510 /* look for PCI Express Capability */
1511 pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
1515 /* check FLR capability */
1516 dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap);
1517 if (!(cap & PCI_EXP_DEVCAP_FLR))
1520 dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0,
1521 PCI_EXP_DEVCTL_BCR_FLR);
1523 /* wait 100ms, per PCI spec */
1529 UCLASS_DRIVER(pci) = {
1532 .flags = DM_UC_FLAG_SEQ_ALIAS,
1533 .post_bind = dm_scan_fdt_dev,
1534 .pre_probe = pci_uclass_pre_probe,
1535 .post_probe = pci_uclass_post_probe,
1536 .child_post_bind = pci_uclass_child_post_bind,
1537 .per_device_auto_alloc_size = sizeof(struct pci_controller),
1538 .per_child_platdata_auto_alloc_size =
1539 sizeof(struct pci_child_platdata),
1542 static const struct dm_pci_ops pci_bridge_ops = {
1543 .read_config = pci_bridge_read_config,
1544 .write_config = pci_bridge_write_config,
1547 static const struct udevice_id pci_bridge_ids[] = {
1548 { .compatible = "pci-bridge" },
1552 U_BOOT_DRIVER(pci_bridge_drv) = {
1553 .name = "pci_bridge_drv",
1555 .of_match = pci_bridge_ids,
1556 .ops = &pci_bridge_ops,
1559 UCLASS_DRIVER(pci_generic) = {
1560 .id = UCLASS_PCI_GENERIC,
1561 .name = "pci_generic",
1564 static const struct udevice_id pci_generic_ids[] = {
1565 { .compatible = "pci-generic" },
1569 U_BOOT_DRIVER(pci_generic_drv) = {
1570 .name = "pci_generic_drv",
1571 .id = UCLASS_PCI_GENERIC,
1572 .of_match = pci_generic_ids,
1577 struct udevice *bus;
1580 * Enumerate all known controller devices. Enumeration has the side-
1581 * effect of probing them, so PCIe devices will be enumerated too.
1583 for (uclass_first_device_check(UCLASS_PCI, &bus);
1585 uclass_next_device_check(&bus)) {