1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2014 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
12 #include <dm/device-internal.h>
14 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
15 #include <asm/fsp/fsp_support.h>
17 #include "pci_internal.h"
19 DECLARE_GLOBAL_DATA_PTR;
21 int pci_get_bus(int busnum, struct udevice **busp)
25 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
27 /* Since buses may not be numbered yet try a little harder with bus 0 */
29 ret = uclass_first_device_err(UCLASS_PCI, busp);
32 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
38 struct udevice *pci_get_controller(struct udevice *dev)
40 while (device_is_on_pci_bus(dev))
46 pci_dev_t dm_pci_get_bdf(struct udevice *dev)
48 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
49 struct udevice *bus = dev->parent;
52 * This error indicates that @dev is a device on an unprobed PCI bus.
53 * The bus likely has bus=seq == -1, so the PCI_ADD_BUS() macro below
54 * will produce a bad BDF>
56 * A common cause of this problem is that this function is called in the
57 * ofdata_to_platdata() method of @dev. Accessing the PCI bus in that
58 * method is not allowed, since it has not yet been probed. To fix this,
59 * move that access to the probe() method of @dev instead.
61 if (!device_active(bus))
62 log_err("PCI: Device '%s' on unprobed bus '%s'\n", dev->name,
64 return PCI_ADD_BUS(bus->seq, pplat->devfn);
68 * pci_get_bus_max() - returns the bus number of the last active bus
70 * @return last bus number, or -1 if no active buses
72 static int pci_get_bus_max(void)
78 ret = uclass_get(UCLASS_PCI, &uc);
79 uclass_foreach_dev(bus, uc) {
84 debug("%s: ret=%d\n", __func__, ret);
89 int pci_last_busno(void)
91 return pci_get_bus_max();
94 int pci_get_ff(enum pci_size_t size)
106 static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
109 struct fdt_pci_addr addr;
113 dev_for_each_subnode(node, bus) {
114 ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
119 if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
127 int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
128 struct udevice **devp)
132 for (device_find_first_child(bus, &dev);
134 device_find_next_child(&dev)) {
135 struct pci_child_platdata *pplat;
137 pplat = dev_get_parent_platdata(dev);
138 if (pplat && pplat->devfn == find_devfn) {
147 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
152 ret = pci_get_bus(PCI_BUS(bdf), &bus);
155 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
158 static int pci_device_matches_ids(struct udevice *dev,
159 struct pci_device_id *ids)
161 struct pci_child_platdata *pplat;
164 pplat = dev_get_parent_platdata(dev);
167 for (i = 0; ids[i].vendor != 0; i++) {
168 if (pplat->vendor == ids[i].vendor &&
169 pplat->device == ids[i].device)
176 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
177 int *indexp, struct udevice **devp)
181 /* Scan all devices on this bus */
182 for (device_find_first_child(bus, &dev);
184 device_find_next_child(&dev)) {
185 if (pci_device_matches_ids(dev, ids) >= 0) {
186 if ((*indexp)-- <= 0) {
196 int pci_find_device_id(struct pci_device_id *ids, int index,
197 struct udevice **devp)
201 /* Scan all known buses */
202 for (uclass_first_device(UCLASS_PCI, &bus);
204 uclass_next_device(&bus)) {
205 if (!pci_bus_find_devices(bus, ids, &index, devp))
213 static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
214 unsigned int device, int *indexp,
215 struct udevice **devp)
217 struct pci_child_platdata *pplat;
220 for (device_find_first_child(bus, &dev);
222 device_find_next_child(&dev)) {
223 pplat = dev_get_parent_platdata(dev);
224 if (pplat->vendor == vendor && pplat->device == device) {
235 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
236 struct udevice **devp)
240 /* Scan all known buses */
241 for (uclass_first_device(UCLASS_PCI, &bus);
243 uclass_next_device(&bus)) {
244 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
245 return device_probe(*devp);
252 int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
256 /* Scan all known buses */
257 for (pci_find_first_device(&dev);
259 pci_find_next_device(&dev)) {
260 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
262 if (pplat->class == find_class && !index--) {
264 return device_probe(*devp);
272 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
273 unsigned long value, enum pci_size_t size)
275 struct dm_pci_ops *ops;
277 ops = pci_get_ops(bus);
278 if (!ops->write_config)
280 return ops->write_config(bus, bdf, offset, value, size);
283 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
289 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
295 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
298 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
299 enum pci_size_t size)
304 ret = pci_get_bus(PCI_BUS(bdf), &bus);
308 return pci_bus_write_config(bus, bdf, offset, value, size);
311 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
312 enum pci_size_t size)
316 for (bus = dev; device_is_on_pci_bus(bus);)
318 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
322 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
324 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
327 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
329 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
332 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
334 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
337 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
339 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
342 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
344 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
347 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
349 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
352 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
353 unsigned long *valuep, enum pci_size_t size)
355 struct dm_pci_ops *ops;
357 ops = pci_get_ops(bus);
358 if (!ops->read_config)
360 return ops->read_config(bus, bdf, offset, valuep, size);
363 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
364 enum pci_size_t size)
369 ret = pci_get_bus(PCI_BUS(bdf), &bus);
373 return pci_bus_read_config(bus, bdf, offset, valuep, size);
376 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
377 enum pci_size_t size)
381 for (bus = dev; device_is_on_pci_bus(bus);)
383 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
387 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
392 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
400 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
405 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
413 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
418 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
426 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
431 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
439 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
444 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
452 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
457 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
465 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
470 ret = dm_pci_read_config8(dev, offset, &val);
476 return dm_pci_write_config8(dev, offset, val);
479 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
484 ret = dm_pci_read_config16(dev, offset, &val);
490 return dm_pci_write_config16(dev, offset, val);
493 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
498 ret = dm_pci_read_config32(dev, offset, &val);
504 return dm_pci_write_config32(dev, offset, val);
507 static void set_vga_bridge_bits(struct udevice *dev)
509 struct udevice *parent = dev->parent;
512 while (parent->seq != 0) {
513 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
514 bc |= PCI_BRIDGE_CTL_VGA;
515 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
516 parent = parent->parent;
520 int pci_auto_config_devices(struct udevice *bus)
522 struct pci_controller *hose = bus->uclass_priv;
523 struct pci_child_platdata *pplat;
524 unsigned int sub_bus;
529 debug("%s: start\n", __func__);
530 pciauto_config_init(hose);
531 for (ret = device_find_first_child(bus, &dev);
533 ret = device_find_next_child(&dev)) {
534 unsigned int max_bus;
537 debug("%s: device %s\n", __func__, dev->name);
538 ret = dm_pciauto_config_device(dev);
542 sub_bus = max(sub_bus, max_bus);
544 pplat = dev_get_parent_platdata(dev);
545 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
546 set_vga_bridge_bits(dev);
548 debug("%s: done\n", __func__);
553 int pci_generic_mmap_write_config(
554 const struct udevice *bus,
555 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
560 enum pci_size_t size)
564 if (addr_f(bus, bdf, offset, &address) < 0)
569 writeb(value, address);
572 writew(value, address);
575 writel(value, address);
582 int pci_generic_mmap_read_config(
583 const struct udevice *bus,
584 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
589 enum pci_size_t size)
593 if (addr_f(bus, bdf, offset, &address) < 0) {
594 *valuep = pci_get_ff(size);
600 *valuep = readb(address);
603 *valuep = readw(address);
606 *valuep = readl(address);
613 int dm_pci_hose_probe_bus(struct udevice *bus)
618 debug("%s\n", __func__);
620 sub_bus = pci_get_bus_max() + 1;
621 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
622 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
624 ret = device_probe(bus);
626 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
630 if (sub_bus != bus->seq) {
631 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
632 __func__, bus->name, bus->seq, sub_bus);
635 sub_bus = pci_get_bus_max();
636 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
642 * pci_match_one_device - Tell if a PCI device structure has a matching
643 * PCI device id structure
644 * @id: single PCI device id structure to match
645 * @find: the PCI device id structure to match against
647 * Returns true if the finding pci_device_id structure matched or false if
650 static bool pci_match_one_id(const struct pci_device_id *id,
651 const struct pci_device_id *find)
653 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
654 (id->device == PCI_ANY_ID || id->device == find->device) &&
655 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
656 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
657 !((id->class ^ find->class) & id->class_mask))
664 * pci_find_and_bind_driver() - Find and bind the right PCI driver
666 * This only looks at certain fields in the descriptor.
668 * @parent: Parent bus
669 * @find_id: Specification of the driver to find
670 * @bdf: Bus/device/function addreess - see PCI_BDF()
671 * @devp: Returns a pointer to the device created
672 * @return 0 if OK, -EPERM if the device is not needed before relocation and
673 * therefore was not created, other -ve value on error
675 static int pci_find_and_bind_driver(struct udevice *parent,
676 struct pci_device_id *find_id,
677 pci_dev_t bdf, struct udevice **devp)
679 struct pci_driver_entry *start, *entry;
680 ofnode node = ofnode_null();
689 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
690 find_id->vendor, find_id->device);
692 /* Determine optional OF node */
693 pci_dev_find_ofnode(parent, bdf, &node);
695 if (ofnode_valid(node) && !ofnode_is_available(node)) {
696 debug("%s: Ignoring disabled device\n", __func__);
700 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
701 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
702 for (entry = start; entry != start + n_ents; entry++) {
703 const struct pci_device_id *id;
705 const struct driver *drv;
707 for (id = entry->match;
708 id->vendor || id->subvendor || id->class_mask;
710 if (!pci_match_one_id(id, find_id))
716 * In the pre-relocation phase, we only bind devices
717 * whose driver has the DM_FLAG_PRE_RELOC set, to save
718 * precious memory space as on some platforms as that
719 * space is pretty limited (ie: using Cache As RAM).
721 if (!(gd->flags & GD_FLG_RELOC) &&
722 !(drv->flags & DM_FLAG_PRE_RELOC))
726 * We could pass the descriptor to the driver as
727 * platdata (instead of NULL) and allow its bind()
728 * method to return -ENOENT if it doesn't support this
729 * device. That way we could continue the search to
730 * find another driver. For now this doesn't seem
731 * necesssary, so just bind the first match.
733 ret = device_bind_ofnode(parent, drv, drv->name, NULL,
737 debug("%s: Match found: %s\n", __func__, drv->name);
738 dev->driver_data = id->driver_data;
744 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
746 * In the pre-relocation phase, we only bind bridge devices to save
747 * precious memory space as on some platforms as that space is pretty
748 * limited (ie: using Cache As RAM).
750 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
753 /* Bind a generic driver so that the device can be used */
754 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
759 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
761 ret = device_bind_driver_to_node(parent, drv, str, node, devp);
763 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
767 debug("%s: No match found: bound generic driver instead\n", __func__);
772 debug("%s: No match found: error %d\n", __func__, ret);
776 int pci_bind_bus_devices(struct udevice *bus)
778 ulong vendor, device;
785 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
786 PCI_MAX_PCI_FUNCTIONS - 1);
787 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
788 bdf += PCI_BDF(0, 0, 1)) {
789 struct pci_child_platdata *pplat;
795 if (PCI_FUNC(bdf) && !found_multi)
798 /* Check only the first access, we don't expect problems */
799 ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
804 if (vendor == 0xffff || vendor == 0x0000)
807 pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
808 &header_type, PCI_SIZE_8);
811 found_multi = header_type & 0x80;
813 debug("%s: bus %d/%s: found device %x, function %d", __func__,
814 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
815 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
817 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
821 /* Find this device in the device tree */
822 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
823 debug(": find ret=%d\n", ret);
825 /* If nothing in the device tree, bind a device */
826 if (ret == -ENODEV) {
827 struct pci_device_id find_id;
830 memset(&find_id, '\0', sizeof(find_id));
831 find_id.vendor = vendor;
832 find_id.device = device;
833 find_id.class = class;
834 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
835 pci_bus_read_config(bus, bdf,
836 PCI_SUBSYSTEM_VENDOR_ID,
838 find_id.subvendor = val & 0xffff;
839 find_id.subdevice = val >> 16;
841 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
849 /* Update the platform data */
850 pplat = dev_get_parent_platdata(dev);
851 pplat->devfn = PCI_MASK_BUS(bdf);
852 pplat->vendor = vendor;
853 pplat->device = device;
854 pplat->class = class;
859 printf("Cannot read bus configuration: %d\n", ret);
864 static void decode_regions(struct pci_controller *hose, ofnode parent_node,
867 int pci_addr_cells, addr_cells, size_cells;
868 int cells_per_record;
873 prop = ofnode_get_property(node, "ranges", &len);
875 debug("%s: Cannot decode regions\n", __func__);
879 pci_addr_cells = ofnode_read_simple_addr_cells(node);
880 addr_cells = ofnode_read_simple_addr_cells(parent_node);
881 size_cells = ofnode_read_simple_size_cells(node);
883 /* PCI addresses are always 3-cells */
885 cells_per_record = pci_addr_cells + addr_cells + size_cells;
886 hose->region_count = 0;
887 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
889 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
890 u64 pci_addr, addr, size;
896 if (len < cells_per_record)
898 flags = fdt32_to_cpu(prop[0]);
899 space_code = (flags >> 24) & 3;
900 pci_addr = fdtdec_get_number(prop + 1, 2);
901 prop += pci_addr_cells;
902 addr = fdtdec_get_number(prop, addr_cells);
904 size = fdtdec_get_number(prop, size_cells);
906 debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
907 __func__, hose->region_count, pci_addr, addr, size, space_code);
908 if (space_code & 2) {
909 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
911 } else if (space_code & 1) {
912 type = PCI_REGION_IO;
917 if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
918 type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
919 debug(" - beyond the 32-bit boundary, ignoring\n");
924 for (i = 0; i < hose->region_count; i++) {
925 if (hose->regions[i].flags == type)
929 pos = hose->region_count++;
930 debug(" - type=%d, pos=%d\n", type, pos);
931 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
934 /* Add a region for our local memory */
935 #ifdef CONFIG_NR_DRAM_BANKS
941 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
942 if (hose->region_count == MAX_PCI_REGIONS) {
943 pr_err("maximum number of regions parsed, aborting\n");
947 if (bd->bi_dram[i].size) {
948 pci_set_region(hose->regions + hose->region_count++,
949 bd->bi_dram[i].start,
950 bd->bi_dram[i].start,
952 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
956 phys_addr_t base = 0, size;
959 #ifdef CONFIG_SYS_SDRAM_BASE
960 base = CONFIG_SYS_SDRAM_BASE;
962 if (gd->pci_ram_top && gd->pci_ram_top < base + size)
963 size = gd->pci_ram_top - base;
965 pci_set_region(hose->regions + hose->region_count++, base,
966 base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
972 static int pci_uclass_pre_probe(struct udevice *bus)
974 struct pci_controller *hose;
976 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
978 hose = bus->uclass_priv;
980 /* For bridges, use the top-level PCI controller */
981 if (!device_is_on_pci_bus(bus)) {
983 decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
985 struct pci_controller *parent_hose;
987 parent_hose = dev_get_uclass_priv(bus->parent);
988 hose->ctlr = parent_hose->bus;
991 hose->first_busno = bus->seq;
992 hose->last_busno = bus->seq;
993 hose->skip_auto_config_until_reloc =
994 dev_read_bool(bus, "u-boot,skip-auto-config-until-reloc");
999 static int pci_uclass_post_probe(struct udevice *bus)
1001 struct pci_controller *hose = dev_get_uclass_priv(bus);
1004 debug("%s: probing bus %d\n", __func__, bus->seq);
1005 ret = pci_bind_bus_devices(bus);
1009 if (CONFIG_IS_ENABLED(PCI_PNP) &&
1010 (!hose->skip_auto_config_until_reloc ||
1011 (gd->flags & GD_FLG_RELOC))) {
1012 ret = pci_auto_config_devices(bus);
1014 return log_msg_ret("pci auto-config", ret);
1017 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
1019 * Per Intel FSP specification, we should call FSP notify API to
1020 * inform FSP that PCI enumeration has been done so that FSP will
1021 * do any necessary initialization as required by the chipset's
1022 * BIOS Writer's Guide (BWG).
1024 * Unfortunately we have to put this call here as with driver model,
1025 * the enumeration is all done on a lazy basis as needed, so until
1026 * something is touched on PCI it won't happen.
1028 * Note we only call this 1) after U-Boot is relocated, and 2)
1029 * root bus has finished probing.
1031 if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
1032 ret = fsp_init_phase_pci();
1041 static int pci_uclass_child_post_bind(struct udevice *dev)
1043 struct pci_child_platdata *pplat;
1045 if (!dev_of_valid(dev))
1048 pplat = dev_get_parent_platdata(dev);
1050 /* Extract vendor id and device id if available */
1051 ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
1053 /* Extract the devfn from fdt_pci_addr */
1054 pplat->devfn = pci_get_devfn(dev);
1059 static int pci_bridge_read_config(const struct udevice *bus, pci_dev_t bdf,
1060 uint offset, ulong *valuep,
1061 enum pci_size_t size)
1063 struct pci_controller *hose = bus->uclass_priv;
1065 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
1068 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
1069 uint offset, ulong value,
1070 enum pci_size_t size)
1072 struct pci_controller *hose = bus->uclass_priv;
1074 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
1077 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
1079 struct udevice *dev;
1083 * Scan through all the PCI controllers. On x86 there will only be one
1084 * but that is not necessarily true on other hardware.
1087 device_find_first_child(bus, &dev);
1092 ret = uclass_next_device(&bus);
1100 int pci_find_next_device(struct udevice **devp)
1102 struct udevice *child = *devp;
1103 struct udevice *bus = child->parent;
1106 /* First try all the siblings */
1109 device_find_next_child(&child);
1116 /* We ran out of siblings. Try the next bus */
1117 ret = uclass_next_device(&bus);
1121 return bus ? skip_to_next_device(bus, devp) : 0;
1124 int pci_find_first_device(struct udevice **devp)
1126 struct udevice *bus;
1130 ret = uclass_first_device(UCLASS_PCI, &bus);
1134 return skip_to_next_device(bus, devp);
1137 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1141 return (value >> ((offset & 3) * 8)) & 0xff;
1143 return (value >> ((offset & 2) * 8)) & 0xffff;
1149 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1150 enum pci_size_t size)
1153 uint val_mask, shift;
1168 shift = (offset & off_mask) * 8;
1169 ldata = (value & val_mask) << shift;
1170 mask = val_mask << shift;
1171 value = (old & ~mask) | ldata;
1176 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1177 struct pci_region **memp, struct pci_region **prefp)
1179 struct udevice *bus = pci_get_controller(dev);
1180 struct pci_controller *hose = dev_get_uclass_priv(bus);
1186 for (i = 0; i < hose->region_count; i++) {
1187 switch (hose->regions[i].flags) {
1189 if (!*iop || (*iop)->size < hose->regions[i].size)
1190 *iop = hose->regions + i;
1192 case PCI_REGION_MEM:
1193 if (!*memp || (*memp)->size < hose->regions[i].size)
1194 *memp = hose->regions + i;
1196 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1197 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1198 *prefp = hose->regions + i;
1203 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1206 u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
1211 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1212 dm_pci_read_config32(dev, bar, &addr);
1213 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1214 return addr & PCI_BASE_ADDRESS_IO_MASK;
1216 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1219 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1223 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1224 dm_pci_write_config32(dev, bar, addr);
1227 static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1228 pci_addr_t bus_addr, unsigned long flags,
1229 unsigned long skip_mask, phys_addr_t *pa)
1231 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1232 struct pci_region *res;
1235 if (hose->region_count == 0) {
1240 for (i = 0; i < hose->region_count; i++) {
1241 res = &hose->regions[i];
1243 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1246 if (res->flags & skip_mask)
1249 if (bus_addr >= res->bus_start &&
1250 (bus_addr - res->bus_start) < res->size) {
1251 *pa = (bus_addr - res->bus_start + res->phys_start);
1259 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1260 unsigned long flags)
1262 phys_addr_t phys_addr = 0;
1263 struct udevice *ctlr;
1266 /* The root controller has the region information */
1267 ctlr = pci_get_controller(dev);
1270 * if PCI_REGION_MEM is set we do a two pass search with preference
1271 * on matches that don't have PCI_REGION_SYS_MEMORY set
1273 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1274 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1275 flags, PCI_REGION_SYS_MEMORY,
1281 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1284 puts("pci_hose_bus_to_phys: invalid physical address\n");
1289 int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1290 unsigned long flags, unsigned long skip_mask,
1293 struct pci_region *res;
1294 struct udevice *ctlr;
1295 pci_addr_t bus_addr;
1297 struct pci_controller *hose;
1299 /* The root controller has the region information */
1300 ctlr = pci_get_controller(dev);
1301 hose = dev_get_uclass_priv(ctlr);
1303 if (hose->region_count == 0) {
1308 for (i = 0; i < hose->region_count; i++) {
1309 res = &hose->regions[i];
1311 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1314 if (res->flags & skip_mask)
1317 bus_addr = phys_addr - res->phys_start + res->bus_start;
1319 if (bus_addr >= res->bus_start &&
1320 (bus_addr - res->bus_start) < res->size) {
1329 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1330 unsigned long flags)
1332 pci_addr_t bus_addr = 0;
1336 * if PCI_REGION_MEM is set we do a two pass search with preference
1337 * on matches that don't have PCI_REGION_SYS_MEMORY set
1339 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1340 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1341 PCI_REGION_SYS_MEMORY, &bus_addr);
1346 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1349 puts("pci_hose_phys_to_bus: invalid physical address\n");
1354 static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
1357 int ea_cnt, i, entry_size;
1358 int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
1362 /* EA capability structure header */
1363 dm_pci_read_config32(dev, ea_off, &ea_entry);
1364 ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
1365 ea_off += PCI_EA_FIRST_ENT;
1367 for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
1369 dm_pci_read_config32(dev, ea_off, &ea_entry);
1370 entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
1372 if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
1375 /* Base address, 1st DW */
1376 dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
1377 addr = ea_entry & PCI_EA_FIELD_MASK;
1378 if (ea_entry & PCI_EA_IS_64) {
1379 /* Base address, 2nd DW, skip over 4B MaxOffset */
1380 dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
1381 addr |= ((u64)ea_entry) << 32;
1384 /* size ignored for now */
1385 return map_physmem(addr, flags, 0);
1391 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1393 pci_addr_t pci_bus_addr;
1398 * if the function supports Enhanced Allocation use that instead of
1401 ea_off = dm_pci_find_capability(dev, PCI_CAP_ID_EA);
1403 return dm_pci_map_ea_bar(dev, bar, flags, ea_off);
1405 /* read BAR address */
1406 dm_pci_read_config32(dev, bar, &bar_response);
1407 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1410 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1411 * isn't actualy used on any platform because u-boot assumes a static
1412 * linear mapping. In the future, this could read the BAR size
1413 * and pass that as the size if needed.
1415 return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1418 static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
1420 int ttl = PCI_FIND_CAP_TTL;
1424 dm_pci_read_config8(dev, pos, &pos);
1427 if (pos < PCI_STD_HEADER_SIZEOF)
1430 dm_pci_read_config16(dev, pos, &ent);
1443 int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap)
1445 return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT,
1449 int dm_pci_find_capability(struct udevice *dev, int cap)
1455 dm_pci_read_config16(dev, PCI_STATUS, &status);
1456 if (!(status & PCI_STATUS_CAP_LIST))
1459 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
1460 if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
1461 pos = PCI_CB_CAPABILITY_LIST;
1463 pos = PCI_CAPABILITY_LIST;
1465 return _dm_pci_find_next_capability(dev, pos, cap);
1468 int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap)
1472 int pos = PCI_CFG_SPACE_SIZE;
1474 /* minimum 8 bytes per capability */
1475 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1480 dm_pci_read_config32(dev, pos, &header);
1482 * If we have no capabilities, this is indicated by cap ID,
1483 * cap version and next pointer all being 0.
1489 if (PCI_EXT_CAP_ID(header) == cap)
1492 pos = PCI_EXT_CAP_NEXT(header);
1493 if (pos < PCI_CFG_SPACE_SIZE)
1496 dm_pci_read_config32(dev, pos, &header);
1502 int dm_pci_find_ext_capability(struct udevice *dev, int cap)
1504 return dm_pci_find_next_ext_capability(dev, 0, cap);
1507 int dm_pci_flr(struct udevice *dev)
1512 /* look for PCI Express Capability */
1513 pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
1517 /* check FLR capability */
1518 dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap);
1519 if (!(cap & PCI_EXP_DEVCAP_FLR))
1522 dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0,
1523 PCI_EXP_DEVCTL_BCR_FLR);
1525 /* wait 100ms, per PCI spec */
1531 UCLASS_DRIVER(pci) = {
1534 .flags = DM_UC_FLAG_SEQ_ALIAS,
1535 .post_bind = dm_scan_fdt_dev,
1536 .pre_probe = pci_uclass_pre_probe,
1537 .post_probe = pci_uclass_post_probe,
1538 .child_post_bind = pci_uclass_child_post_bind,
1539 .per_device_auto_alloc_size = sizeof(struct pci_controller),
1540 .per_child_platdata_auto_alloc_size =
1541 sizeof(struct pci_child_platdata),
1544 static const struct dm_pci_ops pci_bridge_ops = {
1545 .read_config = pci_bridge_read_config,
1546 .write_config = pci_bridge_write_config,
1549 static const struct udevice_id pci_bridge_ids[] = {
1550 { .compatible = "pci-bridge" },
1554 U_BOOT_DRIVER(pci_bridge_drv) = {
1555 .name = "pci_bridge_drv",
1557 .of_match = pci_bridge_ids,
1558 .ops = &pci_bridge_ops,
1561 UCLASS_DRIVER(pci_generic) = {
1562 .id = UCLASS_PCI_GENERIC,
1563 .name = "pci_generic",
1566 static const struct udevice_id pci_generic_ids[] = {
1567 { .compatible = "pci-generic" },
1571 U_BOOT_DRIVER(pci_generic_drv) = {
1572 .name = "pci_generic_drv",
1573 .id = UCLASS_PCI_GENERIC,
1574 .of_match = pci_generic_ids,
1579 struct udevice *bus;
1582 * Enumerate all known controller devices. Enumeration has the side-
1583 * effect of probing them, so PCIe devices will be enumerated too.
1585 for (uclass_first_device_check(UCLASS_PCI, &bus);
1587 uclass_next_device_check(&bus)) {