1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2014 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
15 #include <dm/device-internal.h>
17 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
18 #include <asm/fsp/fsp_support.h>
20 #include <linux/delay.h>
21 #include "pci_internal.h"
23 DECLARE_GLOBAL_DATA_PTR;
25 int pci_get_bus(int busnum, struct udevice **busp)
29 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
31 /* Since buses may not be numbered yet try a little harder with bus 0 */
33 ret = uclass_first_device_err(UCLASS_PCI, busp);
36 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
42 struct udevice *pci_get_controller(struct udevice *dev)
44 while (device_is_on_pci_bus(dev))
50 pci_dev_t dm_pci_get_bdf(const struct udevice *dev)
52 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
53 struct udevice *bus = dev->parent;
56 * This error indicates that @dev is a device on an unprobed PCI bus.
57 * The bus likely has bus=seq == -1, so the PCI_ADD_BUS() macro below
58 * will produce a bad BDF>
60 * A common cause of this problem is that this function is called in the
61 * ofdata_to_platdata() method of @dev. Accessing the PCI bus in that
62 * method is not allowed, since it has not yet been probed. To fix this,
63 * move that access to the probe() method of @dev instead.
65 if (!device_active(bus))
66 log_err("PCI: Device '%s' on unprobed bus '%s'\n", dev->name,
68 return PCI_ADD_BUS(bus->seq, pplat->devfn);
72 * pci_get_bus_max() - returns the bus number of the last active bus
74 * @return last bus number, or -1 if no active buses
76 static int pci_get_bus_max(void)
82 ret = uclass_get(UCLASS_PCI, &uc);
83 uclass_foreach_dev(bus, uc) {
88 debug("%s: ret=%d\n", __func__, ret);
93 int pci_last_busno(void)
95 return pci_get_bus_max();
98 int pci_get_ff(enum pci_size_t size)
110 static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
113 struct fdt_pci_addr addr;
117 dev_for_each_subnode(node, bus) {
118 ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
123 if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
131 int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
132 struct udevice **devp)
136 for (device_find_first_child(bus, &dev);
138 device_find_next_child(&dev)) {
139 struct pci_child_platdata *pplat;
141 pplat = dev_get_parent_platdata(dev);
142 if (pplat && pplat->devfn == find_devfn) {
151 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
156 ret = pci_get_bus(PCI_BUS(bdf), &bus);
159 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
162 static int pci_device_matches_ids(struct udevice *dev,
163 struct pci_device_id *ids)
165 struct pci_child_platdata *pplat;
168 pplat = dev_get_parent_platdata(dev);
171 for (i = 0; ids[i].vendor != 0; i++) {
172 if (pplat->vendor == ids[i].vendor &&
173 pplat->device == ids[i].device)
180 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
181 int *indexp, struct udevice **devp)
185 /* Scan all devices on this bus */
186 for (device_find_first_child(bus, &dev);
188 device_find_next_child(&dev)) {
189 if (pci_device_matches_ids(dev, ids) >= 0) {
190 if ((*indexp)-- <= 0) {
200 int pci_find_device_id(struct pci_device_id *ids, int index,
201 struct udevice **devp)
205 /* Scan all known buses */
206 for (uclass_first_device(UCLASS_PCI, &bus);
208 uclass_next_device(&bus)) {
209 if (!pci_bus_find_devices(bus, ids, &index, devp))
217 static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
218 unsigned int device, int *indexp,
219 struct udevice **devp)
221 struct pci_child_platdata *pplat;
224 for (device_find_first_child(bus, &dev);
226 device_find_next_child(&dev)) {
227 pplat = dev_get_parent_platdata(dev);
228 if (pplat->vendor == vendor && pplat->device == device) {
239 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
240 struct udevice **devp)
244 /* Scan all known buses */
245 for (uclass_first_device(UCLASS_PCI, &bus);
247 uclass_next_device(&bus)) {
248 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
249 return device_probe(*devp);
256 int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
260 /* Scan all known buses */
261 for (pci_find_first_device(&dev);
263 pci_find_next_device(&dev)) {
264 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
266 if (pplat->class == find_class && !index--) {
268 return device_probe(*devp);
276 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
277 unsigned long value, enum pci_size_t size)
279 struct dm_pci_ops *ops;
281 ops = pci_get_ops(bus);
282 if (!ops->write_config)
284 return ops->write_config(bus, bdf, offset, value, size);
287 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
293 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
299 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
302 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
303 enum pci_size_t size)
308 ret = pci_get_bus(PCI_BUS(bdf), &bus);
312 return pci_bus_write_config(bus, bdf, offset, value, size);
315 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
316 enum pci_size_t size)
320 for (bus = dev; device_is_on_pci_bus(bus);)
322 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
326 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
328 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
331 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
333 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
336 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
338 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
341 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
343 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
346 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
348 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
351 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
353 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
356 int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
357 unsigned long *valuep, enum pci_size_t size)
359 struct dm_pci_ops *ops;
361 ops = pci_get_ops(bus);
362 if (!ops->read_config)
364 return ops->read_config(bus, bdf, offset, valuep, size);
367 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
368 enum pci_size_t size)
373 ret = pci_get_bus(PCI_BUS(bdf), &bus);
377 return pci_bus_read_config(bus, bdf, offset, valuep, size);
380 int dm_pci_read_config(const struct udevice *dev, int offset,
381 unsigned long *valuep, enum pci_size_t size)
383 const struct udevice *bus;
385 for (bus = dev; device_is_on_pci_bus(bus);)
387 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
391 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
396 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
404 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
409 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
417 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
422 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
430 int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep)
435 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
443 int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep)
448 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
456 int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep)
461 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
469 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
474 ret = dm_pci_read_config8(dev, offset, &val);
480 return dm_pci_write_config8(dev, offset, val);
483 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
488 ret = dm_pci_read_config16(dev, offset, &val);
494 return dm_pci_write_config16(dev, offset, val);
497 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
502 ret = dm_pci_read_config32(dev, offset, &val);
508 return dm_pci_write_config32(dev, offset, val);
511 static void set_vga_bridge_bits(struct udevice *dev)
513 struct udevice *parent = dev->parent;
516 while (parent->seq != 0) {
517 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
518 bc |= PCI_BRIDGE_CTL_VGA;
519 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
520 parent = parent->parent;
524 int pci_auto_config_devices(struct udevice *bus)
526 struct pci_controller *hose = bus->uclass_priv;
527 struct pci_child_platdata *pplat;
528 unsigned int sub_bus;
533 debug("%s: start\n", __func__);
534 pciauto_config_init(hose);
535 for (ret = device_find_first_child(bus, &dev);
537 ret = device_find_next_child(&dev)) {
538 unsigned int max_bus;
541 debug("%s: device %s\n", __func__, dev->name);
542 if (dev_read_bool(dev, "pci,no-autoconfig"))
544 ret = dm_pciauto_config_device(dev);
548 sub_bus = max(sub_bus, max_bus);
550 pplat = dev_get_parent_platdata(dev);
551 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
552 set_vga_bridge_bits(dev);
554 debug("%s: done\n", __func__);
559 int pci_generic_mmap_write_config(
560 const struct udevice *bus,
561 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
566 enum pci_size_t size)
570 if (addr_f(bus, bdf, offset, &address) < 0)
575 writeb(value, address);
578 writew(value, address);
581 writel(value, address);
588 int pci_generic_mmap_read_config(
589 const struct udevice *bus,
590 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
595 enum pci_size_t size)
599 if (addr_f(bus, bdf, offset, &address) < 0) {
600 *valuep = pci_get_ff(size);
606 *valuep = readb(address);
609 *valuep = readw(address);
612 *valuep = readl(address);
619 int dm_pci_hose_probe_bus(struct udevice *bus)
624 debug("%s\n", __func__);
626 sub_bus = pci_get_bus_max() + 1;
627 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
628 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
630 ret = device_probe(bus);
632 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
636 if (sub_bus != bus->seq) {
637 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
638 __func__, bus->name, bus->seq, sub_bus);
641 sub_bus = pci_get_bus_max();
642 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
648 * pci_match_one_device - Tell if a PCI device structure has a matching
649 * PCI device id structure
650 * @id: single PCI device id structure to match
651 * @find: the PCI device id structure to match against
653 * Returns true if the finding pci_device_id structure matched or false if
656 static bool pci_match_one_id(const struct pci_device_id *id,
657 const struct pci_device_id *find)
659 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
660 (id->device == PCI_ANY_ID || id->device == find->device) &&
661 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
662 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
663 !((id->class ^ find->class) & id->class_mask))
670 * pci_find_and_bind_driver() - Find and bind the right PCI driver
672 * This only looks at certain fields in the descriptor.
674 * @parent: Parent bus
675 * @find_id: Specification of the driver to find
676 * @bdf: Bus/device/function addreess - see PCI_BDF()
677 * @devp: Returns a pointer to the device created
678 * @return 0 if OK, -EPERM if the device is not needed before relocation and
679 * therefore was not created, other -ve value on error
681 static int pci_find_and_bind_driver(struct udevice *parent,
682 struct pci_device_id *find_id,
683 pci_dev_t bdf, struct udevice **devp)
685 struct pci_driver_entry *start, *entry;
686 ofnode node = ofnode_null();
695 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
696 find_id->vendor, find_id->device);
698 /* Determine optional OF node */
699 if (ofnode_valid(dev_ofnode(parent)))
700 pci_dev_find_ofnode(parent, bdf, &node);
702 if (ofnode_valid(node) && !ofnode_is_available(node)) {
703 debug("%s: Ignoring disabled device\n", __func__);
707 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
708 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
709 for (entry = start; entry != start + n_ents; entry++) {
710 const struct pci_device_id *id;
712 const struct driver *drv;
714 for (id = entry->match;
715 id->vendor || id->subvendor || id->class_mask;
717 if (!pci_match_one_id(id, find_id))
723 * In the pre-relocation phase, we only bind devices
724 * whose driver has the DM_FLAG_PRE_RELOC set, to save
725 * precious memory space as on some platforms as that
726 * space is pretty limited (ie: using Cache As RAM).
728 if (!(gd->flags & GD_FLG_RELOC) &&
729 !(drv->flags & DM_FLAG_PRE_RELOC))
733 * We could pass the descriptor to the driver as
734 * platdata (instead of NULL) and allow its bind()
735 * method to return -ENOENT if it doesn't support this
736 * device. That way we could continue the search to
737 * find another driver. For now this doesn't seem
738 * necesssary, so just bind the first match.
740 ret = device_bind_ofnode(parent, drv, drv->name, NULL,
744 debug("%s: Match found: %s\n", __func__, drv->name);
745 dev->driver_data = id->driver_data;
751 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
753 * In the pre-relocation phase, we only bind bridge devices to save
754 * precious memory space as on some platforms as that space is pretty
755 * limited (ie: using Cache As RAM).
757 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
760 /* Bind a generic driver so that the device can be used */
761 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
766 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
768 ret = device_bind_driver_to_node(parent, drv, str, node, devp);
770 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
774 debug("%s: No match found: bound generic driver instead\n", __func__);
779 debug("%s: No match found: error %d\n", __func__, ret);
783 int pci_bind_bus_devices(struct udevice *bus)
785 ulong vendor, device;
792 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
793 PCI_MAX_PCI_FUNCTIONS - 1);
794 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
795 bdf += PCI_BDF(0, 0, 1)) {
796 struct pci_child_platdata *pplat;
802 if (PCI_FUNC(bdf) && !found_multi)
805 /* Check only the first access, we don't expect problems */
806 ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
811 if (vendor == 0xffff || vendor == 0x0000)
814 pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
815 &header_type, PCI_SIZE_8);
818 found_multi = header_type & 0x80;
820 debug("%s: bus %d/%s: found device %x, function %d", __func__,
821 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
822 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
824 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
828 /* Find this device in the device tree */
829 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
830 debug(": find ret=%d\n", ret);
832 /* If nothing in the device tree, bind a device */
833 if (ret == -ENODEV) {
834 struct pci_device_id find_id;
837 memset(&find_id, '\0', sizeof(find_id));
838 find_id.vendor = vendor;
839 find_id.device = device;
840 find_id.class = class;
841 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
842 pci_bus_read_config(bus, bdf,
843 PCI_SUBSYSTEM_VENDOR_ID,
845 find_id.subvendor = val & 0xffff;
846 find_id.subdevice = val >> 16;
848 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
856 /* Update the platform data */
857 pplat = dev_get_parent_platdata(dev);
858 pplat->devfn = PCI_MASK_BUS(bdf);
859 pplat->vendor = vendor;
860 pplat->device = device;
861 pplat->class = class;
866 printf("Cannot read bus configuration: %d\n", ret);
871 static void decode_regions(struct pci_controller *hose, ofnode parent_node,
874 int pci_addr_cells, addr_cells, size_cells;
875 struct bd_info *bd = gd->bd;
876 int cells_per_record;
882 prop = ofnode_get_property(node, "ranges", &len);
884 debug("%s: Cannot decode regions\n", __func__);
888 pci_addr_cells = ofnode_read_simple_addr_cells(node);
889 addr_cells = ofnode_read_simple_addr_cells(parent_node);
890 size_cells = ofnode_read_simple_size_cells(node);
892 /* PCI addresses are always 3-cells */
894 cells_per_record = pci_addr_cells + addr_cells + size_cells;
895 hose->region_count = 0;
896 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
899 /* Dynamically allocate the regions array */
900 max_regions = len / cells_per_record + CONFIG_NR_DRAM_BANKS;
901 hose->regions = (struct pci_region *)
902 calloc(1, max_regions * sizeof(struct pci_region));
904 for (i = 0; i < max_regions; i++, len -= cells_per_record) {
905 u64 pci_addr, addr, size;
911 if (len < cells_per_record)
913 flags = fdt32_to_cpu(prop[0]);
914 space_code = (flags >> 24) & 3;
915 pci_addr = fdtdec_get_number(prop + 1, 2);
916 prop += pci_addr_cells;
917 addr = fdtdec_get_number(prop, addr_cells);
919 size = fdtdec_get_number(prop, size_cells);
921 debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
922 __func__, hose->region_count, pci_addr, addr, size, space_code);
923 if (space_code & 2) {
924 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
926 } else if (space_code & 1) {
927 type = PCI_REGION_IO;
932 if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
933 type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
934 debug(" - beyond the 32-bit boundary, ignoring\n");
939 for (i = 0; i < hose->region_count; i++) {
940 if (hose->regions[i].flags == type)
944 pos = hose->region_count++;
945 debug(" - type=%d, pos=%d\n", type, pos);
946 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
949 /* Add a region for our local memory */
953 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
954 if (bd->bi_dram[i].size) {
955 pci_set_region(hose->regions + hose->region_count++,
956 bd->bi_dram[i].start,
957 bd->bi_dram[i].start,
959 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
966 static int pci_uclass_pre_probe(struct udevice *bus)
968 struct pci_controller *hose;
970 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
972 hose = bus->uclass_priv;
974 /* For bridges, use the top-level PCI controller */
975 if (!device_is_on_pci_bus(bus)) {
977 decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
979 struct pci_controller *parent_hose;
981 parent_hose = dev_get_uclass_priv(bus->parent);
982 hose->ctlr = parent_hose->bus;
985 hose->first_busno = bus->seq;
986 hose->last_busno = bus->seq;
987 hose->skip_auto_config_until_reloc =
988 dev_read_bool(bus, "u-boot,skip-auto-config-until-reloc");
993 static int pci_uclass_post_probe(struct udevice *bus)
995 struct pci_controller *hose = dev_get_uclass_priv(bus);
998 debug("%s: probing bus %d\n", __func__, bus->seq);
999 ret = pci_bind_bus_devices(bus);
1003 if (CONFIG_IS_ENABLED(PCI_PNP) && ll_boot_init() &&
1004 (!hose->skip_auto_config_until_reloc ||
1005 (gd->flags & GD_FLG_RELOC))) {
1006 ret = pci_auto_config_devices(bus);
1008 return log_msg_ret("pci auto-config", ret);
1011 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
1013 * Per Intel FSP specification, we should call FSP notify API to
1014 * inform FSP that PCI enumeration has been done so that FSP will
1015 * do any necessary initialization as required by the chipset's
1016 * BIOS Writer's Guide (BWG).
1018 * Unfortunately we have to put this call here as with driver model,
1019 * the enumeration is all done on a lazy basis as needed, so until
1020 * something is touched on PCI it won't happen.
1022 * Note we only call this 1) after U-Boot is relocated, and 2)
1023 * root bus has finished probing.
1025 if ((gd->flags & GD_FLG_RELOC) && bus->seq == 0 && ll_boot_init()) {
1026 ret = fsp_init_phase_pci();
1035 static int pci_uclass_child_post_bind(struct udevice *dev)
1037 struct pci_child_platdata *pplat;
1039 if (!dev_of_valid(dev))
1042 pplat = dev_get_parent_platdata(dev);
1044 /* Extract vendor id and device id if available */
1045 ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
1047 /* Extract the devfn from fdt_pci_addr */
1048 pplat->devfn = pci_get_devfn(dev);
1053 static int pci_bridge_read_config(const struct udevice *bus, pci_dev_t bdf,
1054 uint offset, ulong *valuep,
1055 enum pci_size_t size)
1057 struct pci_controller *hose = bus->uclass_priv;
1059 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
1062 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
1063 uint offset, ulong value,
1064 enum pci_size_t size)
1066 struct pci_controller *hose = bus->uclass_priv;
1068 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
1071 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
1073 struct udevice *dev;
1077 * Scan through all the PCI controllers. On x86 there will only be one
1078 * but that is not necessarily true on other hardware.
1081 device_find_first_child(bus, &dev);
1086 ret = uclass_next_device(&bus);
1094 int pci_find_next_device(struct udevice **devp)
1096 struct udevice *child = *devp;
1097 struct udevice *bus = child->parent;
1100 /* First try all the siblings */
1103 device_find_next_child(&child);
1110 /* We ran out of siblings. Try the next bus */
1111 ret = uclass_next_device(&bus);
1115 return bus ? skip_to_next_device(bus, devp) : 0;
1118 int pci_find_first_device(struct udevice **devp)
1120 struct udevice *bus;
1124 ret = uclass_first_device(UCLASS_PCI, &bus);
1128 return skip_to_next_device(bus, devp);
1131 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1135 return (value >> ((offset & 3) * 8)) & 0xff;
1137 return (value >> ((offset & 2) * 8)) & 0xffff;
1143 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1144 enum pci_size_t size)
1147 uint val_mask, shift;
1162 shift = (offset & off_mask) * 8;
1163 ldata = (value & val_mask) << shift;
1164 mask = val_mask << shift;
1165 value = (old & ~mask) | ldata;
1170 int pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int index)
1172 int pci_addr_cells, addr_cells, size_cells;
1173 int cells_per_record;
1178 prop = ofnode_get_property(dev_ofnode(dev), "dma-ranges", &len);
1180 log_err("PCI: Device '%s': Cannot decode dma-ranges\n",
1185 pci_addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev));
1186 addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev->parent));
1187 size_cells = ofnode_read_simple_size_cells(dev_ofnode(dev));
1189 /* PCI addresses are always 3-cells */
1191 cells_per_record = pci_addr_cells + addr_cells + size_cells;
1192 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
1196 memp->bus_start = fdtdec_get_number(prop + 1, 2);
1197 prop += pci_addr_cells;
1198 memp->phys_start = fdtdec_get_number(prop, addr_cells);
1200 memp->size = fdtdec_get_number(prop, size_cells);
1206 len -= cells_per_record;
1212 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1213 struct pci_region **memp, struct pci_region **prefp)
1215 struct udevice *bus = pci_get_controller(dev);
1216 struct pci_controller *hose = dev_get_uclass_priv(bus);
1222 for (i = 0; i < hose->region_count; i++) {
1223 switch (hose->regions[i].flags) {
1225 if (!*iop || (*iop)->size < hose->regions[i].size)
1226 *iop = hose->regions + i;
1228 case PCI_REGION_MEM:
1229 if (!*memp || (*memp)->size < hose->regions[i].size)
1230 *memp = hose->regions + i;
1232 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1233 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1234 *prefp = hose->regions + i;
1239 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1242 u32 dm_pci_read_bar32(const struct udevice *dev, int barnum)
1247 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1248 dm_pci_read_config32(dev, bar, &addr);
1251 * If we get an invalid address, return this so that comparisons with
1252 * FDT_ADDR_T_NONE work correctly
1254 if (addr == 0xffffffff)
1256 else if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1257 return addr & PCI_BASE_ADDRESS_IO_MASK;
1259 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1262 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1266 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1267 dm_pci_write_config32(dev, bar, addr);
1270 static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1271 pci_addr_t bus_addr, unsigned long flags,
1272 unsigned long skip_mask, phys_addr_t *pa)
1274 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1275 struct pci_region *res;
1278 if (hose->region_count == 0) {
1283 for (i = 0; i < hose->region_count; i++) {
1284 res = &hose->regions[i];
1286 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1289 if (res->flags & skip_mask)
1292 if (bus_addr >= res->bus_start &&
1293 (bus_addr - res->bus_start) < res->size) {
1294 *pa = (bus_addr - res->bus_start + res->phys_start);
1302 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1303 unsigned long flags)
1305 phys_addr_t phys_addr = 0;
1306 struct udevice *ctlr;
1309 /* The root controller has the region information */
1310 ctlr = pci_get_controller(dev);
1313 * if PCI_REGION_MEM is set we do a two pass search with preference
1314 * on matches that don't have PCI_REGION_SYS_MEMORY set
1316 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1317 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1318 flags, PCI_REGION_SYS_MEMORY,
1324 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1327 puts("pci_hose_bus_to_phys: invalid physical address\n");
1332 int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1333 unsigned long flags, unsigned long skip_mask,
1336 struct pci_region *res;
1337 struct udevice *ctlr;
1338 pci_addr_t bus_addr;
1340 struct pci_controller *hose;
1342 /* The root controller has the region information */
1343 ctlr = pci_get_controller(dev);
1344 hose = dev_get_uclass_priv(ctlr);
1346 if (hose->region_count == 0) {
1351 for (i = 0; i < hose->region_count; i++) {
1352 res = &hose->regions[i];
1354 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1357 if (res->flags & skip_mask)
1360 bus_addr = phys_addr - res->phys_start + res->bus_start;
1362 if (bus_addr >= res->bus_start &&
1363 (bus_addr - res->bus_start) < res->size) {
1372 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1373 unsigned long flags)
1375 pci_addr_t bus_addr = 0;
1379 * if PCI_REGION_MEM is set we do a two pass search with preference
1380 * on matches that don't have PCI_REGION_SYS_MEMORY set
1382 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1383 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1384 PCI_REGION_SYS_MEMORY, &bus_addr);
1389 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1392 puts("pci_hose_phys_to_bus: invalid physical address\n");
1397 static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
1400 int ea_cnt, i, entry_size;
1401 int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
1405 /* EA capability structure header */
1406 dm_pci_read_config32(dev, ea_off, &ea_entry);
1407 ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
1408 ea_off += PCI_EA_FIRST_ENT;
1410 for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
1412 dm_pci_read_config32(dev, ea_off, &ea_entry);
1413 entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
1415 if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
1418 /* Base address, 1st DW */
1419 dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
1420 addr = ea_entry & PCI_EA_FIELD_MASK;
1421 if (ea_entry & PCI_EA_IS_64) {
1422 /* Base address, 2nd DW, skip over 4B MaxOffset */
1423 dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
1424 addr |= ((u64)ea_entry) << 32;
1427 /* size ignored for now */
1428 return map_physmem(addr, 0, flags);
1434 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1436 pci_addr_t pci_bus_addr;
1441 * if the function supports Enhanced Allocation use that instead of
1444 ea_off = dm_pci_find_capability(dev, PCI_CAP_ID_EA);
1446 return dm_pci_map_ea_bar(dev, bar, flags, ea_off);
1448 /* read BAR address */
1449 dm_pci_read_config32(dev, bar, &bar_response);
1450 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1453 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1454 * isn't actually used on any platform because U-Boot assumes a static
1455 * linear mapping. In the future, this could read the BAR size
1456 * and pass that as the size if needed.
1458 return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1461 static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
1463 int ttl = PCI_FIND_CAP_TTL;
1467 dm_pci_read_config8(dev, pos, &pos);
1470 if (pos < PCI_STD_HEADER_SIZEOF)
1473 dm_pci_read_config16(dev, pos, &ent);
1486 int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap)
1488 return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT,
1492 int dm_pci_find_capability(struct udevice *dev, int cap)
1498 dm_pci_read_config16(dev, PCI_STATUS, &status);
1499 if (!(status & PCI_STATUS_CAP_LIST))
1502 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
1503 if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
1504 pos = PCI_CB_CAPABILITY_LIST;
1506 pos = PCI_CAPABILITY_LIST;
1508 return _dm_pci_find_next_capability(dev, pos, cap);
1511 int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap)
1515 int pos = PCI_CFG_SPACE_SIZE;
1517 /* minimum 8 bytes per capability */
1518 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1523 dm_pci_read_config32(dev, pos, &header);
1525 * If we have no capabilities, this is indicated by cap ID,
1526 * cap version and next pointer all being 0.
1532 if (PCI_EXT_CAP_ID(header) == cap)
1535 pos = PCI_EXT_CAP_NEXT(header);
1536 if (pos < PCI_CFG_SPACE_SIZE)
1539 dm_pci_read_config32(dev, pos, &header);
1545 int dm_pci_find_ext_capability(struct udevice *dev, int cap)
1547 return dm_pci_find_next_ext_capability(dev, 0, cap);
1550 int dm_pci_flr(struct udevice *dev)
1555 /* look for PCI Express Capability */
1556 pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
1560 /* check FLR capability */
1561 dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap);
1562 if (!(cap & PCI_EXP_DEVCAP_FLR))
1565 dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0,
1566 PCI_EXP_DEVCTL_BCR_FLR);
1568 /* wait 100ms, per PCI spec */
1574 UCLASS_DRIVER(pci) = {
1577 .flags = DM_UC_FLAG_SEQ_ALIAS,
1578 .post_bind = dm_scan_fdt_dev,
1579 .pre_probe = pci_uclass_pre_probe,
1580 .post_probe = pci_uclass_post_probe,
1581 .child_post_bind = pci_uclass_child_post_bind,
1582 .per_device_auto_alloc_size = sizeof(struct pci_controller),
1583 .per_child_platdata_auto_alloc_size =
1584 sizeof(struct pci_child_platdata),
1587 static const struct dm_pci_ops pci_bridge_ops = {
1588 .read_config = pci_bridge_read_config,
1589 .write_config = pci_bridge_write_config,
1592 static const struct udevice_id pci_bridge_ids[] = {
1593 { .compatible = "pci-bridge" },
1597 U_BOOT_DRIVER(pci_bridge_drv) = {
1598 .name = "pci_bridge_drv",
1600 .of_match = pci_bridge_ids,
1601 .ops = &pci_bridge_ops,
1604 UCLASS_DRIVER(pci_generic) = {
1605 .id = UCLASS_PCI_GENERIC,
1606 .name = "pci_generic",
1609 static const struct udevice_id pci_generic_ids[] = {
1610 { .compatible = "pci-generic" },
1614 U_BOOT_DRIVER(pci_generic_drv) = {
1615 .name = "pci_generic_drv",
1616 .id = UCLASS_PCI_GENERIC,
1617 .of_match = pci_generic_ids,
1622 struct udevice *bus;
1625 * Enumerate all known controller devices. Enumeration has the side-
1626 * effect of probing them, so PCIe devices will be enumerated too.
1628 for (uclass_first_device_check(UCLASS_PCI, &bus);
1630 uclass_next_device_check(&bus)) {