1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2014 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
12 #include <dm/device-internal.h>
14 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
15 #include <asm/fsp/fsp_support.h>
17 #include "pci_internal.h"
19 DECLARE_GLOBAL_DATA_PTR;
21 int pci_get_bus(int busnum, struct udevice **busp)
25 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
27 /* Since buses may not be numbered yet try a little harder with bus 0 */
29 ret = uclass_first_device_err(UCLASS_PCI, busp);
32 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
38 struct udevice *pci_get_controller(struct udevice *dev)
40 while (device_is_on_pci_bus(dev))
46 pci_dev_t dm_pci_get_bdf(struct udevice *dev)
48 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
49 struct udevice *bus = dev->parent;
51 return PCI_ADD_BUS(bus->seq, pplat->devfn);
55 * pci_get_bus_max() - returns the bus number of the last active bus
57 * @return last bus number, or -1 if no active buses
59 static int pci_get_bus_max(void)
65 ret = uclass_get(UCLASS_PCI, &uc);
66 uclass_foreach_dev(bus, uc) {
71 debug("%s: ret=%d\n", __func__, ret);
76 int pci_last_busno(void)
78 return pci_get_bus_max();
81 int pci_get_ff(enum pci_size_t size)
93 static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
96 struct fdt_pci_addr addr;
100 dev_for_each_subnode(node, bus) {
101 ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
106 if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
114 int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
115 struct udevice **devp)
119 for (device_find_first_child(bus, &dev);
121 device_find_next_child(&dev)) {
122 struct pci_child_platdata *pplat;
124 pplat = dev_get_parent_platdata(dev);
125 if (pplat && pplat->devfn == find_devfn) {
134 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
139 ret = pci_get_bus(PCI_BUS(bdf), &bus);
142 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
145 static int pci_device_matches_ids(struct udevice *dev,
146 struct pci_device_id *ids)
148 struct pci_child_platdata *pplat;
151 pplat = dev_get_parent_platdata(dev);
154 for (i = 0; ids[i].vendor != 0; i++) {
155 if (pplat->vendor == ids[i].vendor &&
156 pplat->device == ids[i].device)
163 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
164 int *indexp, struct udevice **devp)
168 /* Scan all devices on this bus */
169 for (device_find_first_child(bus, &dev);
171 device_find_next_child(&dev)) {
172 if (pci_device_matches_ids(dev, ids) >= 0) {
173 if ((*indexp)-- <= 0) {
183 int pci_find_device_id(struct pci_device_id *ids, int index,
184 struct udevice **devp)
188 /* Scan all known buses */
189 for (uclass_first_device(UCLASS_PCI, &bus);
191 uclass_next_device(&bus)) {
192 if (!pci_bus_find_devices(bus, ids, &index, devp))
200 static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
201 unsigned int device, int *indexp,
202 struct udevice **devp)
204 struct pci_child_platdata *pplat;
207 for (device_find_first_child(bus, &dev);
209 device_find_next_child(&dev)) {
210 pplat = dev_get_parent_platdata(dev);
211 if (pplat->vendor == vendor && pplat->device == device) {
222 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
223 struct udevice **devp)
227 /* Scan all known buses */
228 for (uclass_first_device(UCLASS_PCI, &bus);
230 uclass_next_device(&bus)) {
231 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
232 return device_probe(*devp);
239 int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
243 /* Scan all known buses */
244 for (pci_find_first_device(&dev);
246 pci_find_next_device(&dev)) {
247 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
249 if (pplat->class == find_class && !index--) {
251 return device_probe(*devp);
259 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
260 unsigned long value, enum pci_size_t size)
262 struct dm_pci_ops *ops;
264 ops = pci_get_ops(bus);
265 if (!ops->write_config)
267 return ops->write_config(bus, bdf, offset, value, size);
270 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
276 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
282 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
285 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
286 enum pci_size_t size)
291 ret = pci_get_bus(PCI_BUS(bdf), &bus);
295 return pci_bus_write_config(bus, bdf, offset, value, size);
298 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
299 enum pci_size_t size)
303 for (bus = dev; device_is_on_pci_bus(bus);)
305 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
309 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
311 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
314 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
316 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
319 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
321 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
324 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
326 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
329 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
331 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
334 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
336 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
339 int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
340 unsigned long *valuep, enum pci_size_t size)
342 struct dm_pci_ops *ops;
344 ops = pci_get_ops(bus);
345 if (!ops->read_config)
347 return ops->read_config(bus, bdf, offset, valuep, size);
350 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
351 enum pci_size_t size)
356 ret = pci_get_bus(PCI_BUS(bdf), &bus);
360 return pci_bus_read_config(bus, bdf, offset, valuep, size);
363 int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
364 enum pci_size_t size)
368 for (bus = dev; device_is_on_pci_bus(bus);)
370 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
374 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
379 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
387 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
392 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
400 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
405 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
413 int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep)
418 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
426 int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep)
431 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
439 int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep)
444 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
452 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
457 ret = dm_pci_read_config8(dev, offset, &val);
463 return dm_pci_write_config8(dev, offset, val);
466 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
471 ret = dm_pci_read_config16(dev, offset, &val);
477 return dm_pci_write_config16(dev, offset, val);
480 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
485 ret = dm_pci_read_config32(dev, offset, &val);
491 return dm_pci_write_config32(dev, offset, val);
494 static void set_vga_bridge_bits(struct udevice *dev)
496 struct udevice *parent = dev->parent;
499 while (parent->seq != 0) {
500 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
501 bc |= PCI_BRIDGE_CTL_VGA;
502 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
503 parent = parent->parent;
507 int pci_auto_config_devices(struct udevice *bus)
509 struct pci_controller *hose = bus->uclass_priv;
510 struct pci_child_platdata *pplat;
511 unsigned int sub_bus;
516 debug("%s: start\n", __func__);
517 pciauto_config_init(hose);
518 for (ret = device_find_first_child(bus, &dev);
520 ret = device_find_next_child(&dev)) {
521 unsigned int max_bus;
524 debug("%s: device %s\n", __func__, dev->name);
525 ret = dm_pciauto_config_device(dev);
529 sub_bus = max(sub_bus, max_bus);
531 pplat = dev_get_parent_platdata(dev);
532 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
533 set_vga_bridge_bits(dev);
535 debug("%s: done\n", __func__);
540 int pci_generic_mmap_write_config(
542 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
546 enum pci_size_t size)
550 if (addr_f(bus, bdf, offset, &address) < 0)
555 writeb(value, address);
558 writew(value, address);
561 writel(value, address);
568 int pci_generic_mmap_read_config(
570 int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
574 enum pci_size_t size)
578 if (addr_f(bus, bdf, offset, &address) < 0) {
579 *valuep = pci_get_ff(size);
585 *valuep = readb(address);
588 *valuep = readw(address);
591 *valuep = readl(address);
598 int dm_pci_hose_probe_bus(struct udevice *bus)
603 debug("%s\n", __func__);
605 sub_bus = pci_get_bus_max() + 1;
606 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
607 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
609 ret = device_probe(bus);
611 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
615 if (sub_bus != bus->seq) {
616 printf("%s: Internal error, bus '%s' got seq %d, expected %d\n",
617 __func__, bus->name, bus->seq, sub_bus);
620 sub_bus = pci_get_bus_max();
621 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
627 * pci_match_one_device - Tell if a PCI device structure has a matching
628 * PCI device id structure
629 * @id: single PCI device id structure to match
630 * @find: the PCI device id structure to match against
632 * Returns true if the finding pci_device_id structure matched or false if
635 static bool pci_match_one_id(const struct pci_device_id *id,
636 const struct pci_device_id *find)
638 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
639 (id->device == PCI_ANY_ID || id->device == find->device) &&
640 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
641 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
642 !((id->class ^ find->class) & id->class_mask))
649 * pci_find_and_bind_driver() - Find and bind the right PCI driver
651 * This only looks at certain fields in the descriptor.
653 * @parent: Parent bus
654 * @find_id: Specification of the driver to find
655 * @bdf: Bus/device/function addreess - see PCI_BDF()
656 * @devp: Returns a pointer to the device created
657 * @return 0 if OK, -EPERM if the device is not needed before relocation and
658 * therefore was not created, other -ve value on error
660 static int pci_find_and_bind_driver(struct udevice *parent,
661 struct pci_device_id *find_id,
662 pci_dev_t bdf, struct udevice **devp)
664 struct pci_driver_entry *start, *entry;
665 ofnode node = ofnode_null();
674 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
675 find_id->vendor, find_id->device);
677 /* Determine optional OF node */
678 pci_dev_find_ofnode(parent, bdf, &node);
680 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
681 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
682 for (entry = start; entry != start + n_ents; entry++) {
683 const struct pci_device_id *id;
685 const struct driver *drv;
687 for (id = entry->match;
688 id->vendor || id->subvendor || id->class_mask;
690 if (!pci_match_one_id(id, find_id))
696 * In the pre-relocation phase, we only bind devices
697 * whose driver has the DM_FLAG_PRE_RELOC set, to save
698 * precious memory space as on some platforms as that
699 * space is pretty limited (ie: using Cache As RAM).
701 if (!(gd->flags & GD_FLG_RELOC) &&
702 !(drv->flags & DM_FLAG_PRE_RELOC))
706 * We could pass the descriptor to the driver as
707 * platdata (instead of NULL) and allow its bind()
708 * method to return -ENOENT if it doesn't support this
709 * device. That way we could continue the search to
710 * find another driver. For now this doesn't seem
711 * necesssary, so just bind the first match.
713 ret = device_bind_ofnode(parent, drv, drv->name, NULL,
717 debug("%s: Match found: %s\n", __func__, drv->name);
718 dev->driver_data = id->driver_data;
724 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
726 * In the pre-relocation phase, we only bind bridge devices to save
727 * precious memory space as on some platforms as that space is pretty
728 * limited (ie: using Cache As RAM).
730 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
733 /* Bind a generic driver so that the device can be used */
734 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
739 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
741 ret = device_bind_driver_to_node(parent, drv, str, node, devp);
743 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
747 debug("%s: No match found: bound generic driver instead\n", __func__);
752 debug("%s: No match found: error %d\n", __func__, ret);
756 int pci_bind_bus_devices(struct udevice *bus)
758 ulong vendor, device;
765 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
766 PCI_MAX_PCI_FUNCTIONS - 1);
767 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
768 bdf += PCI_BDF(0, 0, 1)) {
769 struct pci_child_platdata *pplat;
775 if (PCI_FUNC(bdf) && !found_multi)
778 /* Check only the first access, we don't expect problems */
779 ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
784 if (vendor == 0xffff || vendor == 0x0000)
787 pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
788 &header_type, PCI_SIZE_8);
791 found_multi = header_type & 0x80;
793 debug("%s: bus %d/%s: found device %x, function %d\n", __func__,
794 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
795 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
797 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
801 /* Find this device in the device tree */
802 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
804 /* If nothing in the device tree, bind a device */
805 if (ret == -ENODEV) {
806 struct pci_device_id find_id;
809 memset(&find_id, '\0', sizeof(find_id));
810 find_id.vendor = vendor;
811 find_id.device = device;
812 find_id.class = class;
813 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
814 pci_bus_read_config(bus, bdf,
815 PCI_SUBSYSTEM_VENDOR_ID,
817 find_id.subvendor = val & 0xffff;
818 find_id.subdevice = val >> 16;
820 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
828 /* Update the platform data */
829 pplat = dev_get_parent_platdata(dev);
830 pplat->devfn = PCI_MASK_BUS(bdf);
831 pplat->vendor = vendor;
832 pplat->device = device;
833 pplat->class = class;
838 printf("Cannot read bus configuration: %d\n", ret);
843 static void decode_regions(struct pci_controller *hose, ofnode parent_node,
846 int pci_addr_cells, addr_cells, size_cells;
847 int cells_per_record;
852 prop = ofnode_get_property(node, "ranges", &len);
854 debug("%s: Cannot decode regions\n", __func__);
858 pci_addr_cells = ofnode_read_simple_addr_cells(node);
859 addr_cells = ofnode_read_simple_addr_cells(parent_node);
860 size_cells = ofnode_read_simple_size_cells(node);
862 /* PCI addresses are always 3-cells */
864 cells_per_record = pci_addr_cells + addr_cells + size_cells;
865 hose->region_count = 0;
866 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
868 for (i = 0; i < MAX_PCI_REGIONS; i++, len -= cells_per_record) {
869 u64 pci_addr, addr, size;
875 if (len < cells_per_record)
877 flags = fdt32_to_cpu(prop[0]);
878 space_code = (flags >> 24) & 3;
879 pci_addr = fdtdec_get_number(prop + 1, 2);
880 prop += pci_addr_cells;
881 addr = fdtdec_get_number(prop, addr_cells);
883 size = fdtdec_get_number(prop, size_cells);
885 debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
886 __func__, hose->region_count, pci_addr, addr, size, space_code);
887 if (space_code & 2) {
888 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
890 } else if (space_code & 1) {
891 type = PCI_REGION_IO;
896 if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
897 type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
898 debug(" - beyond the 32-bit boundary, ignoring\n");
903 for (i = 0; i < hose->region_count; i++) {
904 if (hose->regions[i].flags == type)
908 pos = hose->region_count++;
909 debug(" - type=%d, pos=%d\n", type, pos);
910 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
913 /* Add a region for our local memory */
914 #ifdef CONFIG_NR_DRAM_BANKS
920 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
921 if (hose->region_count == MAX_PCI_REGIONS) {
922 pr_err("maximum number of regions parsed, aborting\n");
926 if (bd->bi_dram[i].size) {
927 pci_set_region(hose->regions + hose->region_count++,
928 bd->bi_dram[i].start,
929 bd->bi_dram[i].start,
931 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
935 phys_addr_t base = 0, size;
938 #ifdef CONFIG_SYS_SDRAM_BASE
939 base = CONFIG_SYS_SDRAM_BASE;
941 if (gd->pci_ram_top && gd->pci_ram_top < base + size)
942 size = gd->pci_ram_top - base;
944 pci_set_region(hose->regions + hose->region_count++, base,
945 base, size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
951 static int pci_uclass_pre_probe(struct udevice *bus)
953 struct pci_controller *hose;
955 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
957 hose = bus->uclass_priv;
959 /* For bridges, use the top-level PCI controller */
960 if (!device_is_on_pci_bus(bus)) {
962 decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
964 struct pci_controller *parent_hose;
966 parent_hose = dev_get_uclass_priv(bus->parent);
967 hose->ctlr = parent_hose->bus;
970 hose->first_busno = bus->seq;
971 hose->last_busno = bus->seq;
976 static int pci_uclass_post_probe(struct udevice *bus)
980 debug("%s: probing bus %d\n", __func__, bus->seq);
981 ret = pci_bind_bus_devices(bus);
985 #ifdef CONFIG_PCI_PNP
986 ret = pci_auto_config_devices(bus);
991 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
993 * Per Intel FSP specification, we should call FSP notify API to
994 * inform FSP that PCI enumeration has been done so that FSP will
995 * do any necessary initialization as required by the chipset's
996 * BIOS Writer's Guide (BWG).
998 * Unfortunately we have to put this call here as with driver model,
999 * the enumeration is all done on a lazy basis as needed, so until
1000 * something is touched on PCI it won't happen.
1002 * Note we only call this 1) after U-Boot is relocated, and 2)
1003 * root bus has finished probing.
1005 if ((gd->flags & GD_FLG_RELOC) && (bus->seq == 0)) {
1006 ret = fsp_init_phase_pci();
1015 int pci_get_devfn(struct udevice *dev)
1017 struct fdt_pci_addr addr;
1020 /* Extract the devfn from fdt_pci_addr */
1021 ret = ofnode_read_pci_addr(dev_ofnode(dev), FDT_PCI_SPACE_CONFIG,
1028 return addr.phys_hi & 0xff00;
1031 static int pci_uclass_child_post_bind(struct udevice *dev)
1033 struct pci_child_platdata *pplat;
1035 if (!dev_of_valid(dev))
1038 pplat = dev_get_parent_platdata(dev);
1040 /* Extract vendor id and device id if available */
1041 ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
1043 /* Extract the devfn from fdt_pci_addr */
1044 pplat->devfn = pci_get_devfn(dev);
1049 static int pci_bridge_read_config(struct udevice *bus, pci_dev_t bdf,
1050 uint offset, ulong *valuep,
1051 enum pci_size_t size)
1053 struct pci_controller *hose = bus->uclass_priv;
1055 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
1058 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
1059 uint offset, ulong value,
1060 enum pci_size_t size)
1062 struct pci_controller *hose = bus->uclass_priv;
1064 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
1067 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
1069 struct udevice *dev;
1073 * Scan through all the PCI controllers. On x86 there will only be one
1074 * but that is not necessarily true on other hardware.
1077 device_find_first_child(bus, &dev);
1082 ret = uclass_next_device(&bus);
1090 int pci_find_next_device(struct udevice **devp)
1092 struct udevice *child = *devp;
1093 struct udevice *bus = child->parent;
1096 /* First try all the siblings */
1099 device_find_next_child(&child);
1106 /* We ran out of siblings. Try the next bus */
1107 ret = uclass_next_device(&bus);
1111 return bus ? skip_to_next_device(bus, devp) : 0;
1114 int pci_find_first_device(struct udevice **devp)
1116 struct udevice *bus;
1120 ret = uclass_first_device(UCLASS_PCI, &bus);
1124 return skip_to_next_device(bus, devp);
1127 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1131 return (value >> ((offset & 3) * 8)) & 0xff;
1133 return (value >> ((offset & 2) * 8)) & 0xffff;
1139 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1140 enum pci_size_t size)
1143 uint val_mask, shift;
1158 shift = (offset & off_mask) * 8;
1159 ldata = (value & val_mask) << shift;
1160 mask = val_mask << shift;
1161 value = (old & ~mask) | ldata;
1166 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1167 struct pci_region **memp, struct pci_region **prefp)
1169 struct udevice *bus = pci_get_controller(dev);
1170 struct pci_controller *hose = dev_get_uclass_priv(bus);
1176 for (i = 0; i < hose->region_count; i++) {
1177 switch (hose->regions[i].flags) {
1179 if (!*iop || (*iop)->size < hose->regions[i].size)
1180 *iop = hose->regions + i;
1182 case PCI_REGION_MEM:
1183 if (!*memp || (*memp)->size < hose->regions[i].size)
1184 *memp = hose->regions + i;
1186 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1187 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1188 *prefp = hose->regions + i;
1193 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1196 u32 dm_pci_read_bar32(struct udevice *dev, int barnum)
1201 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1202 dm_pci_read_config32(dev, bar, &addr);
1203 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1204 return addr & PCI_BASE_ADDRESS_IO_MASK;
1206 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1209 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1213 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1214 dm_pci_write_config32(dev, bar, addr);
1217 static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1218 pci_addr_t bus_addr, unsigned long flags,
1219 unsigned long skip_mask, phys_addr_t *pa)
1221 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1222 struct pci_region *res;
1225 if (hose->region_count == 0) {
1230 for (i = 0; i < hose->region_count; i++) {
1231 res = &hose->regions[i];
1233 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1236 if (res->flags & skip_mask)
1239 if (bus_addr >= res->bus_start &&
1240 (bus_addr - res->bus_start) < res->size) {
1241 *pa = (bus_addr - res->bus_start + res->phys_start);
1249 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1250 unsigned long flags)
1252 phys_addr_t phys_addr = 0;
1253 struct udevice *ctlr;
1256 /* The root controller has the region information */
1257 ctlr = pci_get_controller(dev);
1260 * if PCI_REGION_MEM is set we do a two pass search with preference
1261 * on matches that don't have PCI_REGION_SYS_MEMORY set
1263 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1264 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1265 flags, PCI_REGION_SYS_MEMORY,
1271 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1274 puts("pci_hose_bus_to_phys: invalid physical address\n");
1279 int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1280 unsigned long flags, unsigned long skip_mask,
1283 struct pci_region *res;
1284 struct udevice *ctlr;
1285 pci_addr_t bus_addr;
1287 struct pci_controller *hose;
1289 /* The root controller has the region information */
1290 ctlr = pci_get_controller(dev);
1291 hose = dev_get_uclass_priv(ctlr);
1293 if (hose->region_count == 0) {
1298 for (i = 0; i < hose->region_count; i++) {
1299 res = &hose->regions[i];
1301 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1304 if (res->flags & skip_mask)
1307 bus_addr = phys_addr - res->phys_start + res->bus_start;
1309 if (bus_addr >= res->bus_start &&
1310 (bus_addr - res->bus_start) < res->size) {
1319 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1320 unsigned long flags)
1322 pci_addr_t bus_addr = 0;
1326 * if PCI_REGION_MEM is set we do a two pass search with preference
1327 * on matches that don't have PCI_REGION_SYS_MEMORY set
1329 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1330 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1331 PCI_REGION_SYS_MEMORY, &bus_addr);
1336 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1339 puts("pci_hose_phys_to_bus: invalid physical address\n");
1344 static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
1347 int ea_cnt, i, entry_size;
1348 int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
1352 /* EA capability structure header */
1353 dm_pci_read_config32(dev, ea_off, &ea_entry);
1354 ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
1355 ea_off += PCI_EA_FIRST_ENT;
1357 for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
1359 dm_pci_read_config32(dev, ea_off, &ea_entry);
1360 entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
1362 if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
1365 /* Base address, 1st DW */
1366 dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
1367 addr = ea_entry & PCI_EA_FIELD_MASK;
1368 if (ea_entry & PCI_EA_IS_64) {
1369 /* Base address, 2nd DW, skip over 4B MaxOffset */
1370 dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
1371 addr |= ((u64)ea_entry) << 32;
1374 /* size ignored for now */
1375 return map_physmem(addr, flags, 0);
1381 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1383 pci_addr_t pci_bus_addr;
1388 * if the function supports Enhanced Allocation use that instead of
1391 ea_off = dm_pci_find_capability(dev, PCI_CAP_ID_EA);
1393 return dm_pci_map_ea_bar(dev, bar, flags, ea_off);
1395 /* read BAR address */
1396 dm_pci_read_config32(dev, bar, &bar_response);
1397 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1400 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1401 * isn't actualy used on any platform because u-boot assumes a static
1402 * linear mapping. In the future, this could read the BAR size
1403 * and pass that as the size if needed.
1405 return dm_pci_bus_to_virt(dev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1408 static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
1410 int ttl = PCI_FIND_CAP_TTL;
1414 dm_pci_read_config8(dev, pos, &pos);
1417 if (pos < PCI_STD_HEADER_SIZEOF)
1420 dm_pci_read_config16(dev, pos, &ent);
1433 int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap)
1435 return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT,
1439 int dm_pci_find_capability(struct udevice *dev, int cap)
1445 dm_pci_read_config16(dev, PCI_STATUS, &status);
1446 if (!(status & PCI_STATUS_CAP_LIST))
1449 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
1450 if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
1451 pos = PCI_CB_CAPABILITY_LIST;
1453 pos = PCI_CAPABILITY_LIST;
1455 return _dm_pci_find_next_capability(dev, pos, cap);
1458 int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap)
1462 int pos = PCI_CFG_SPACE_SIZE;
1464 /* minimum 8 bytes per capability */
1465 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1470 dm_pci_read_config32(dev, pos, &header);
1472 * If we have no capabilities, this is indicated by cap ID,
1473 * cap version and next pointer all being 0.
1479 if (PCI_EXT_CAP_ID(header) == cap)
1482 pos = PCI_EXT_CAP_NEXT(header);
1483 if (pos < PCI_CFG_SPACE_SIZE)
1486 dm_pci_read_config32(dev, pos, &header);
1492 int dm_pci_find_ext_capability(struct udevice *dev, int cap)
1494 return dm_pci_find_next_ext_capability(dev, 0, cap);
1497 int dm_pci_flr(struct udevice *dev)
1502 /* look for PCI Express Capability */
1503 pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
1507 /* check FLR capability */
1508 dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap);
1509 if (!(cap & PCI_EXP_DEVCAP_FLR))
1512 dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0,
1513 PCI_EXP_DEVCTL_BCR_FLR);
1515 /* wait 100ms, per PCI spec */
1521 UCLASS_DRIVER(pci) = {
1524 .flags = DM_UC_FLAG_SEQ_ALIAS,
1525 .post_bind = dm_scan_fdt_dev,
1526 .pre_probe = pci_uclass_pre_probe,
1527 .post_probe = pci_uclass_post_probe,
1528 .child_post_bind = pci_uclass_child_post_bind,
1529 .per_device_auto_alloc_size = sizeof(struct pci_controller),
1530 .per_child_platdata_auto_alloc_size =
1531 sizeof(struct pci_child_platdata),
1534 static const struct dm_pci_ops pci_bridge_ops = {
1535 .read_config = pci_bridge_read_config,
1536 .write_config = pci_bridge_write_config,
1539 static const struct udevice_id pci_bridge_ids[] = {
1540 { .compatible = "pci-bridge" },
1544 U_BOOT_DRIVER(pci_bridge_drv) = {
1545 .name = "pci_bridge_drv",
1547 .of_match = pci_bridge_ids,
1548 .ops = &pci_bridge_ops,
1551 UCLASS_DRIVER(pci_generic) = {
1552 .id = UCLASS_PCI_GENERIC,
1553 .name = "pci_generic",
1556 static const struct udevice_id pci_generic_ids[] = {
1557 { .compatible = "pci-generic" },
1561 U_BOOT_DRIVER(pci_generic_drv) = {
1562 .name = "pci_generic_drv",
1563 .id = UCLASS_PCI_GENERIC,
1564 .of_match = pci_generic_ids,
1569 struct udevice *bus;
1572 * Enumerate all known controller devices. Enumeration has the side-
1573 * effect of probing them, so PCIe devices will be enumerated too.
1575 for (uclass_first_device(UCLASS_PCI, &bus);
1577 uclass_next_device(&bus)) {