1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2014 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
7 #define LOG_CATEGORY UCLASS_PCI
17 #include <asm/global_data.h>
19 #include <dm/device-internal.h>
21 #include <dm/uclass-internal.h>
22 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
23 #include <asm/fsp/fsp_support.h>
25 #include <dt-bindings/pci/pci.h>
26 #include <linux/delay.h>
27 #include "pci_internal.h"
29 DECLARE_GLOBAL_DATA_PTR;
31 int pci_get_bus(int busnum, struct udevice **busp)
35 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
37 /* Since buses may not be numbered yet try a little harder with bus 0 */
39 ret = uclass_first_device_err(UCLASS_PCI, busp);
42 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
48 struct udevice *pci_get_controller(struct udevice *dev)
50 while (device_is_on_pci_bus(dev))
56 pci_dev_t dm_pci_get_bdf(const struct udevice *dev)
58 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
59 struct udevice *bus = dev->parent;
62 * This error indicates that @dev is a device on an unprobed PCI bus.
63 * The bus likely has bus=seq == -1, so the PCI_ADD_BUS() macro below
64 * will produce a bad BDF>
66 * A common cause of this problem is that this function is called in the
67 * of_to_plat() method of @dev. Accessing the PCI bus in that
68 * method is not allowed, since it has not yet been probed. To fix this,
69 * move that access to the probe() method of @dev instead.
71 if (!device_active(bus))
72 log_err("PCI: Device '%s' on unprobed bus '%s'\n", dev->name,
74 return PCI_ADD_BUS(dev_seq(bus), pplat->devfn);
78 * pci_get_bus_max() - returns the bus number of the last active bus
80 * Return: last bus number, or -1 if no active buses
82 static int pci_get_bus_max(void)
88 ret = uclass_get(UCLASS_PCI, &uc);
89 uclass_foreach_dev(bus, uc) {
90 if (dev_seq(bus) > ret)
94 debug("%s: ret=%d\n", __func__, ret);
99 int pci_last_busno(void)
101 return pci_get_bus_max();
104 int pci_get_ff(enum pci_size_t size)
116 static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
119 struct fdt_pci_addr addr;
123 dev_for_each_subnode(node, bus) {
124 ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
129 if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
137 int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
138 struct udevice **devp)
142 for (device_find_first_child(bus, &dev);
144 device_find_next_child(&dev)) {
145 struct pci_child_plat *pplat;
147 pplat = dev_get_parent_plat(dev);
148 if (pplat && pplat->devfn == find_devfn) {
157 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
162 ret = pci_get_bus(PCI_BUS(bdf), &bus);
165 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
168 static int pci_device_matches_ids(struct udevice *dev,
169 const struct pci_device_id *ids)
171 struct pci_child_plat *pplat;
174 pplat = dev_get_parent_plat(dev);
177 for (i = 0; ids[i].vendor != 0; i++) {
178 if (pplat->vendor == ids[i].vendor &&
179 pplat->device == ids[i].device)
186 int pci_bus_find_devices(struct udevice *bus, const struct pci_device_id *ids,
187 int *indexp, struct udevice **devp)
191 /* Scan all devices on this bus */
192 for (device_find_first_child(bus, &dev);
194 device_find_next_child(&dev)) {
195 if (pci_device_matches_ids(dev, ids) >= 0) {
196 if ((*indexp)-- <= 0) {
206 int pci_find_device_id(const struct pci_device_id *ids, int index,
207 struct udevice **devp)
211 /* Scan all known buses */
212 for (uclass_first_device(UCLASS_PCI, &bus);
214 uclass_next_device(&bus)) {
215 if (!pci_bus_find_devices(bus, ids, &index, devp))
223 static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
224 unsigned int device, int *indexp,
225 struct udevice **devp)
227 struct pci_child_plat *pplat;
230 for (device_find_first_child(bus, &dev);
232 device_find_next_child(&dev)) {
233 pplat = dev_get_parent_plat(dev);
234 if (pplat->vendor == vendor && pplat->device == device) {
245 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
246 struct udevice **devp)
250 /* Scan all known buses */
251 for (uclass_first_device(UCLASS_PCI, &bus);
253 uclass_next_device(&bus)) {
254 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
255 return device_probe(*devp);
262 int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
266 /* Scan all known buses */
267 for (pci_find_first_device(&dev);
269 pci_find_next_device(&dev)) {
270 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
272 if (pplat->class == find_class && !index--) {
274 return device_probe(*devp);
282 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
283 unsigned long value, enum pci_size_t size)
285 struct dm_pci_ops *ops;
287 ops = pci_get_ops(bus);
288 if (!ops->write_config)
290 if (offset < 0 || offset >= 4096)
292 return ops->write_config(bus, bdf, offset, value, size);
295 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
301 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
307 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
310 static int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
311 enum pci_size_t size)
316 ret = pci_get_bus(PCI_BUS(bdf), &bus);
320 return pci_bus_write_config(bus, bdf, offset, value, size);
323 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
324 enum pci_size_t size)
328 for (bus = dev; device_is_on_pci_bus(bus);)
330 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
334 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
336 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
339 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
341 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
344 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
346 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
349 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
351 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
354 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
356 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
359 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
361 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
364 int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
365 unsigned long *valuep, enum pci_size_t size)
367 struct dm_pci_ops *ops;
369 ops = pci_get_ops(bus);
370 if (!ops->read_config) {
371 *valuep = pci_conv_32_to_size(~0, offset, size);
374 if (offset < 0 || offset >= 4096) {
375 *valuep = pci_conv_32_to_size(0, offset, size);
378 return ops->read_config(bus, bdf, offset, valuep, size);
381 static int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
382 enum pci_size_t size)
387 ret = pci_get_bus(PCI_BUS(bdf), &bus);
391 return pci_bus_read_config(bus, bdf, offset, valuep, size);
394 int dm_pci_read_config(const struct udevice *dev, int offset,
395 unsigned long *valuep, enum pci_size_t size)
397 const struct udevice *bus;
399 for (bus = dev; device_is_on_pci_bus(bus);)
401 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
405 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
410 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
418 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
423 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
431 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
436 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
444 int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep)
449 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
457 int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep)
462 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
470 int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep)
475 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
483 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
488 ret = dm_pci_read_config8(dev, offset, &val);
494 return dm_pci_write_config8(dev, offset, val);
497 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
502 ret = dm_pci_read_config16(dev, offset, &val);
508 return dm_pci_write_config16(dev, offset, val);
511 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
516 ret = dm_pci_read_config32(dev, offset, &val);
522 return dm_pci_write_config32(dev, offset, val);
525 static void set_vga_bridge_bits(struct udevice *dev)
527 struct udevice *parent = dev->parent;
530 while (dev_seq(parent) != 0) {
531 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
532 bc |= PCI_BRIDGE_CTL_VGA;
533 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
534 parent = parent->parent;
538 int pci_auto_config_devices(struct udevice *bus)
540 struct pci_controller *hose = dev_get_uclass_priv(bus);
541 struct pci_child_plat *pplat;
542 unsigned int sub_bus;
546 sub_bus = dev_seq(bus);
547 debug("%s: start\n", __func__);
548 pciauto_config_init(hose);
549 for (ret = device_find_first_child(bus, &dev);
551 ret = device_find_next_child(&dev)) {
552 unsigned int max_bus;
555 debug("%s: device %s\n", __func__, dev->name);
556 if (dev_has_ofnode(dev) &&
557 dev_read_bool(dev, "pci,no-autoconfig"))
559 ret = dm_pciauto_config_device(dev);
561 return log_msg_ret("auto", ret);
563 sub_bus = max(sub_bus, max_bus);
565 if (dev_get_parent(dev) == bus)
568 pplat = dev_get_parent_plat(dev);
569 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
570 set_vga_bridge_bits(dev);
572 if (hose->last_busno < sub_bus)
573 hose->last_busno = sub_bus;
574 debug("%s: done\n", __func__);
576 return log_msg_ret("sub", sub_bus);
579 int pci_generic_mmap_write_config(
580 const struct udevice *bus,
581 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
586 enum pci_size_t size)
590 if (addr_f(bus, bdf, offset, &address) < 0)
595 writeb(value, address);
598 writew(value, address);
601 writel(value, address);
608 int pci_generic_mmap_read_config(
609 const struct udevice *bus,
610 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
615 enum pci_size_t size)
619 if (addr_f(bus, bdf, offset, &address) < 0) {
620 *valuep = pci_get_ff(size);
626 *valuep = readb(address);
629 *valuep = readw(address);
632 *valuep = readl(address);
639 int dm_pci_hose_probe_bus(struct udevice *bus)
647 debug("%s\n", __func__);
649 dm_pci_read_config8(bus, PCI_HEADER_TYPE, &header_type);
651 if (header_type != PCI_HEADER_TYPE_BRIDGE) {
652 debug("%s: Skipping PCI device %d with Non-Bridge Header Type 0x%x\n",
653 __func__, PCI_DEV(dm_pci_get_bdf(bus)), header_type);
654 return log_msg_ret("probe", -EINVAL);
657 if (IS_ENABLED(CONFIG_PCI_ENHANCED_ALLOCATION))
658 ea_pos = dm_pci_find_capability(bus, PCI_CAP_ID_EA);
663 dm_pci_read_config8(bus, ea_pos + sizeof(u32) + sizeof(u8),
667 sub_bus = pci_get_bus_max() + 1;
669 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
670 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
672 ret = device_probe(bus);
674 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
676 return log_msg_ret("probe", ret);
680 sub_bus = pci_get_bus_max();
682 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
688 * pci_match_one_device - Tell if a PCI device structure has a matching
689 * PCI device id structure
690 * @id: single PCI device id structure to match
691 * @find: the PCI device id structure to match against
693 * Returns true if the finding pci_device_id structure matched or false if
696 static bool pci_match_one_id(const struct pci_device_id *id,
697 const struct pci_device_id *find)
699 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
700 (id->device == PCI_ANY_ID || id->device == find->device) &&
701 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
702 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
703 !((id->class ^ find->class) & id->class_mask))
710 * pci_need_device_pre_reloc() - Check if a device should be bound
712 * This checks a list of vendor/device-ID values indicating devices that should
713 * be bound before relocation.
716 * @vendor: Vendor ID to check
717 * @device: Device ID to check
718 * Return: true if the vendor/device is in the list, false if not
720 static bool pci_need_device_pre_reloc(struct udevice *bus, uint vendor,
726 if (spl_phase() == PHASE_SPL && CONFIG_IS_ENABLED(PCI_PNP))
730 !dev_read_u32_index(bus, "u-boot,pci-pre-reloc", index,
733 if (vendev == PCI_VENDEV(vendor, device))
741 * pci_find_and_bind_driver() - Find and bind the right PCI driver
743 * This only looks at certain fields in the descriptor.
745 * @parent: Parent bus
746 * @find_id: Specification of the driver to find
747 * @bdf: Bus/device/function addreess - see PCI_BDF()
748 * @devp: Returns a pointer to the device created
749 * Return: 0 if OK, -EPERM if the device is not needed before relocation and
750 * therefore was not created, other -ve value on error
752 static int pci_find_and_bind_driver(struct udevice *parent,
753 struct pci_device_id *find_id,
754 pci_dev_t bdf, struct udevice **devp)
756 struct pci_driver_entry *start, *entry;
757 ofnode node = ofnode_null();
766 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
767 find_id->vendor, find_id->device);
769 /* Determine optional OF node */
770 if (ofnode_valid(dev_ofnode(parent)))
771 pci_dev_find_ofnode(parent, bdf, &node);
773 if (ofnode_valid(node) && !ofnode_is_enabled(node)) {
774 debug("%s: Ignoring disabled device\n", __func__);
775 return log_msg_ret("dis", -EPERM);
778 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
779 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
780 for (entry = start; entry != start + n_ents; entry++) {
781 const struct pci_device_id *id;
783 const struct driver *drv;
785 for (id = entry->match;
786 id->vendor || id->subvendor || id->class_mask;
788 if (!pci_match_one_id(id, find_id))
794 * In the pre-relocation phase, we only bind devices
795 * whose driver has the DM_FLAG_PRE_RELOC set, to save
796 * precious memory space as on some platforms as that
797 * space is pretty limited (ie: using Cache As RAM).
799 if (!(gd->flags & GD_FLG_RELOC) &&
800 !(drv->flags & DM_FLAG_PRE_RELOC) &&
801 (!CONFIG_IS_ENABLED(PCI_PNP) ||
802 spl_phase() != PHASE_SPL))
803 return log_msg_ret("pre", -EPERM);
806 * We could pass the descriptor to the driver as
807 * plat (instead of NULL) and allow its bind()
808 * method to return -ENOENT if it doesn't support this
809 * device. That way we could continue the search to
810 * find another driver. For now this doesn't seem
811 * necesssary, so just bind the first match.
813 ret = device_bind(parent, drv, drv->name, NULL, node,
817 debug("%s: Match found: %s\n", __func__, drv->name);
818 dev->driver_data = id->driver_data;
824 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
826 * In the pre-relocation phase, we only bind bridge devices to save
827 * precious memory space as on some platforms as that space is pretty
828 * limited (ie: using Cache As RAM).
830 if (!(gd->flags & GD_FLG_RELOC) && !bridge &&
831 !pci_need_device_pre_reloc(parent, find_id->vendor,
833 return log_msg_ret("notbr", -EPERM);
835 /* Bind a generic driver so that the device can be used */
836 sprintf(name, "pci_%x:%x.%x", dev_seq(parent), PCI_DEV(bdf),
841 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
843 ret = device_bind_driver_to_node(parent, drv, str, node, devp);
845 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
849 debug("%s: No match found: bound generic driver instead\n", __func__);
854 debug("%s: No match found: error %d\n", __func__, ret);
858 __weak extern void board_pci_fixup_dev(struct udevice *bus, struct udevice *dev)
862 int pci_bind_bus_devices(struct udevice *bus)
864 ulong vendor, device;
872 end = PCI_BDF(dev_seq(bus), PCI_MAX_PCI_DEVICES - 1,
873 PCI_MAX_PCI_FUNCTIONS - 1);
874 for (bdf = PCI_BDF(dev_seq(bus), 0, 0); bdf <= end;
875 bdf += PCI_BDF(0, 0, 1)) {
876 struct pci_child_plat *pplat;
882 if (PCI_FUNC(bdf) && !found_multi)
885 /* Check only the first access, we don't expect problems */
886 ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
888 if (ret || vendor == 0xffff || vendor == 0x0000)
891 pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
892 &header_type, PCI_SIZE_8);
895 found_multi = header_type & 0x80;
897 debug("%s: bus %d/%s: found device %x, function %d", __func__,
898 dev_seq(bus), bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
899 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
901 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
905 /* Find this device in the device tree */
906 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
907 debug(": find ret=%d\n", ret);
909 /* If nothing in the device tree, bind a device */
910 if (ret == -ENODEV) {
911 struct pci_device_id find_id;
914 memset(&find_id, '\0', sizeof(find_id));
915 find_id.vendor = vendor;
916 find_id.device = device;
917 find_id.class = class;
918 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
919 pci_bus_read_config(bus, bdf,
920 PCI_SUBSYSTEM_VENDOR_ID,
922 find_id.subvendor = val & 0xffff;
923 find_id.subdevice = val >> 16;
925 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
928 debug("device: %s\n", dev->name);
935 /* Update the platform data */
936 pplat = dev_get_parent_plat(dev);
937 pplat->devfn = PCI_MASK_BUS(bdf);
938 pplat->vendor = vendor;
939 pplat->device = device;
940 pplat->class = class;
942 if (IS_ENABLED(CONFIG_PCI_ARID)) {
943 ari_off = dm_pci_find_ext_capability(dev,
949 * Read Next Function number in ARI Cap
952 dm_pci_read_config16(dev, ari_off + 4,
955 * Update next scan on this function number,
956 * subtract 1 in BDF to satisfy loop increment.
958 if (ari_cap & 0xff00) {
959 bdf = PCI_BDF(PCI_BUS(bdf),
967 board_pci_fixup_dev(bus, dev);
973 static int decode_regions(struct pci_controller *hose, ofnode parent_node,
976 int pci_addr_cells, addr_cells, size_cells;
977 int cells_per_record;
984 /* handle booting from coreboot, etc. */
988 prop = ofnode_get_property(node, "ranges", &len);
990 debug("%s: Cannot decode regions\n", __func__);
994 pci_addr_cells = ofnode_read_simple_addr_cells(node);
995 addr_cells = ofnode_read_simple_addr_cells(parent_node);
996 size_cells = ofnode_read_simple_size_cells(node);
998 /* PCI addresses are always 3-cells */
1000 cells_per_record = pci_addr_cells + addr_cells + size_cells;
1001 hose->region_count = 0;
1002 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
1005 /* Dynamically allocate the regions array */
1006 max_regions = len / cells_per_record + CONFIG_NR_DRAM_BANKS;
1007 hose->regions = (struct pci_region *)
1008 calloc(1, max_regions * sizeof(struct pci_region));
1012 for (i = 0; i < max_regions; i++, len -= cells_per_record) {
1013 u64 pci_addr, addr, size;
1019 if (len < cells_per_record)
1021 flags = fdt32_to_cpu(prop[0]);
1022 space_code = (flags >> 24) & 3;
1023 pci_addr = fdtdec_get_number(prop + 1, 2);
1024 prop += pci_addr_cells;
1025 addr = fdtdec_get_number(prop, addr_cells);
1027 size = fdtdec_get_number(prop, size_cells);
1029 debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
1030 __func__, hose->region_count, pci_addr, addr, size, space_code);
1031 if (space_code & 2) {
1032 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
1034 } else if (space_code & 1) {
1035 type = PCI_REGION_IO;
1040 if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
1041 type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
1042 debug(" - pci_addr beyond the 32-bit boundary, ignoring\n");
1046 if (!IS_ENABLED(CONFIG_PHYS_64BIT) && upper_32_bits(addr)) {
1047 debug(" - addr beyond the 32-bit boundary, ignoring\n");
1051 if (~((pci_addr_t)0) - pci_addr < size) {
1052 debug(" - PCI range exceeds max address, ignoring\n");
1056 if (~((phys_addr_t)0) - addr < size) {
1057 debug(" - phys range exceeds max address, ignoring\n");
1062 if (!IS_ENABLED(CONFIG_PCI_REGION_MULTI_ENTRY)) {
1063 for (i = 0; i < hose->region_count; i++) {
1064 if (hose->regions[i].flags == type)
1070 pos = hose->region_count++;
1071 debug(" - type=%d, pos=%d\n", type, pos);
1072 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
1075 /* Add a region for our local memory */
1080 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
1081 if (bd->bi_dram[i].size) {
1082 phys_addr_t start = bd->bi_dram[i].start;
1084 if (IS_ENABLED(CONFIG_PCI_MAP_SYSTEM_MEMORY))
1085 start = virt_to_phys((void *)(uintptr_t)bd->bi_dram[i].start);
1087 pci_set_region(hose->regions + hose->region_count++,
1088 start, start, bd->bi_dram[i].size,
1089 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
1096 static int pci_uclass_pre_probe(struct udevice *bus)
1098 struct pci_controller *hose;
1102 debug("%s, bus=%d/%s, parent=%s\n", __func__, dev_seq(bus), bus->name,
1104 hose = dev_get_uclass_priv(bus);
1107 * Set the sequence number, if device_bind() doesn't. We want control
1108 * of this so that numbers are allocated as devices are probed. That
1109 * ensures that sub-bus numbered is correct (sub-buses must get numbers
1110 * higher than their parents)
1112 if (dev_seq(bus) == -1) {
1113 ret = uclass_get(UCLASS_PCI, &uc);
1116 bus->seq_ = uclass_find_next_free_seq(uc);
1119 /* For bridges, use the top-level PCI controller */
1120 if (!device_is_on_pci_bus(bus)) {
1122 ret = decode_regions(hose, dev_ofnode(bus->parent),
1127 struct pci_controller *parent_hose;
1129 parent_hose = dev_get_uclass_priv(bus->parent);
1130 hose->ctlr = parent_hose->bus;
1134 hose->first_busno = dev_seq(bus);
1135 hose->last_busno = dev_seq(bus);
1136 if (dev_has_ofnode(bus)) {
1137 hose->skip_auto_config_until_reloc =
1139 "u-boot,skip-auto-config-until-reloc");
1145 static int pci_uclass_post_probe(struct udevice *bus)
1147 struct pci_controller *hose = dev_get_uclass_priv(bus);
1150 debug("%s: probing bus %d\n", __func__, dev_seq(bus));
1151 ret = pci_bind_bus_devices(bus);
1153 return log_msg_ret("bind", ret);
1155 if (CONFIG_IS_ENABLED(PCI_PNP) && ll_boot_init() &&
1156 (!hose->skip_auto_config_until_reloc ||
1157 (gd->flags & GD_FLG_RELOC))) {
1158 ret = pci_auto_config_devices(bus);
1160 return log_msg_ret("cfg", ret);
1163 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
1165 * Per Intel FSP specification, we should call FSP notify API to
1166 * inform FSP that PCI enumeration has been done so that FSP will
1167 * do any necessary initialization as required by the chipset's
1168 * BIOS Writer's Guide (BWG).
1170 * Unfortunately we have to put this call here as with driver model,
1171 * the enumeration is all done on a lazy basis as needed, so until
1172 * something is touched on PCI it won't happen.
1174 * Note we only call this 1) after U-Boot is relocated, and 2)
1175 * root bus has finished probing.
1177 if ((gd->flags & GD_FLG_RELOC) && dev_seq(bus) == 0 && ll_boot_init()) {
1178 ret = fsp_init_phase_pci();
1180 return log_msg_ret("fsp", ret);
1187 static int pci_uclass_child_post_bind(struct udevice *dev)
1189 struct pci_child_plat *pplat;
1191 if (!dev_has_ofnode(dev))
1194 pplat = dev_get_parent_plat(dev);
1196 /* Extract vendor id and device id if available */
1197 ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
1199 /* Extract the devfn from fdt_pci_addr */
1200 pplat->devfn = pci_get_devfn(dev);
1205 static int pci_bridge_read_config(const struct udevice *bus, pci_dev_t bdf,
1206 uint offset, ulong *valuep,
1207 enum pci_size_t size)
1209 struct pci_controller *hose = dev_get_uclass_priv(bus);
1211 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
1214 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
1215 uint offset, ulong value,
1216 enum pci_size_t size)
1218 struct pci_controller *hose = dev_get_uclass_priv(bus);
1220 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
1223 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
1225 struct udevice *dev;
1228 * Scan through all the PCI controllers. On x86 there will only be one
1229 * but that is not necessarily true on other hardware.
1232 device_find_first_child(bus, &dev);
1237 uclass_next_device(&bus);
1243 int pci_find_next_device(struct udevice **devp)
1245 struct udevice *child = *devp;
1246 struct udevice *bus = child->parent;
1248 /* First try all the siblings */
1251 device_find_next_child(&child);
1258 /* We ran out of siblings. Try the next bus */
1259 uclass_next_device(&bus);
1261 return bus ? skip_to_next_device(bus, devp) : 0;
1264 int pci_find_first_device(struct udevice **devp)
1266 struct udevice *bus;
1269 uclass_first_device(UCLASS_PCI, &bus);
1271 return skip_to_next_device(bus, devp);
1274 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1278 return (value >> ((offset & 3) * 8)) & 0xff;
1280 return (value >> ((offset & 2) * 8)) & 0xffff;
1286 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1287 enum pci_size_t size)
1290 uint val_mask, shift;
1305 shift = (offset & off_mask) * 8;
1306 ldata = (value & val_mask) << shift;
1307 mask = val_mask << shift;
1308 value = (old & ~mask) | ldata;
1313 int pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int index)
1315 int pci_addr_cells, addr_cells, size_cells;
1316 int cells_per_record;
1321 prop = ofnode_get_property(dev_ofnode(dev), "dma-ranges", &len);
1323 log_err("PCI: Device '%s': Cannot decode dma-ranges\n",
1328 pci_addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev));
1329 addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev->parent));
1330 size_cells = ofnode_read_simple_size_cells(dev_ofnode(dev));
1332 /* PCI addresses are always 3-cells */
1334 cells_per_record = pci_addr_cells + addr_cells + size_cells;
1335 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
1339 memp->bus_start = fdtdec_get_number(prop + 1, 2);
1340 prop += pci_addr_cells;
1341 memp->phys_start = fdtdec_get_number(prop, addr_cells);
1343 memp->size = fdtdec_get_number(prop, size_cells);
1349 len -= cells_per_record;
1355 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1356 struct pci_region **memp, struct pci_region **prefp)
1358 struct udevice *bus = pci_get_controller(dev);
1359 struct pci_controller *hose = dev_get_uclass_priv(bus);
1365 for (i = 0; i < hose->region_count; i++) {
1366 switch (hose->regions[i].flags) {
1368 if (!*iop || (*iop)->size < hose->regions[i].size)
1369 *iop = hose->regions + i;
1371 case PCI_REGION_MEM:
1372 if (!*memp || (*memp)->size < hose->regions[i].size)
1373 *memp = hose->regions + i;
1375 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1376 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1377 *prefp = hose->regions + i;
1382 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1385 u32 dm_pci_read_bar32(const struct udevice *dev, int barnum)
1390 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1391 dm_pci_read_config32(dev, bar, &addr);
1394 * If we get an invalid address, return this so that comparisons with
1395 * FDT_ADDR_T_NONE work correctly
1397 if (addr == 0xffffffff)
1399 else if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1400 return addr & PCI_BASE_ADDRESS_IO_MASK;
1402 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1405 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1409 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1410 dm_pci_write_config32(dev, bar, addr);
1413 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1414 size_t len, unsigned long mask,
1415 unsigned long flags)
1417 struct udevice *ctlr;
1418 struct pci_controller *hose;
1419 struct pci_region *res;
1423 /* The root controller has the region information */
1424 ctlr = pci_get_controller(dev);
1425 hose = dev_get_uclass_priv(ctlr);
1427 if (hose->region_count == 0)
1430 for (i = 0; i < hose->region_count; i++) {
1431 res = &hose->regions[i];
1433 if ((res->flags & mask) != flags)
1436 if (bus_addr < res->bus_start)
1439 offset = bus_addr - res->bus_start;
1440 if (offset >= res->size)
1443 if (len > res->size - offset)
1446 return res->phys_start + offset;
1449 puts("pci_hose_bus_to_phys: invalid physical address\n");
1453 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1454 size_t len, unsigned long mask,
1455 unsigned long flags)
1457 struct udevice *ctlr;
1458 struct pci_controller *hose;
1459 struct pci_region *res;
1463 /* The root controller has the region information */
1464 ctlr = pci_get_controller(dev);
1465 hose = dev_get_uclass_priv(ctlr);
1467 if (hose->region_count == 0)
1470 for (i = 0; i < hose->region_count; i++) {
1471 res = &hose->regions[i];
1473 if ((res->flags & mask) != flags)
1476 if (phys_addr < res->phys_start)
1479 offset = phys_addr - res->phys_start;
1480 if (offset >= res->size)
1483 if (len > res->size - offset)
1486 return res->bus_start + offset;
1489 puts("pci_hose_phys_to_bus: invalid physical address\n");
1493 static phys_addr_t dm_pci_map_ea_virt(struct udevice *dev, int ea_off,
1494 struct pci_child_plat *pdata)
1496 phys_addr_t addr = 0;
1499 * In the case of a Virtual Function device using BAR
1500 * base and size, add offset for VFn BAR(1, 2, 3...n)
1502 if (pdata->is_virtfn) {
1506 /* MaxOffset, 1st DW */
1507 dm_pci_read_config32(dev, ea_off + 8, &ea_entry);
1508 sz = ea_entry & PCI_EA_FIELD_MASK;
1509 /* Fill up lower 2 bits */
1510 sz |= (~PCI_EA_FIELD_MASK);
1512 if (ea_entry & PCI_EA_IS_64) {
1513 /* MaxOffset 2nd DW */
1514 dm_pci_read_config32(dev, ea_off + 16, &ea_entry);
1515 sz |= ((u64)ea_entry) << 32;
1518 addr = (pdata->virtid - 1) * (sz + 1);
1524 static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, size_t offset,
1525 size_t len, int ea_off,
1526 struct pci_child_plat *pdata)
1528 int ea_cnt, i, entry_size;
1529 int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
1533 if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
1535 * In the case of a Virtual Function device, device is
1536 * Physical function, so pdata will point to required VF
1539 if (pdata->is_virtfn)
1540 bar_id += PCI_EA_BEI_VF_BAR0;
1543 /* EA capability structure header */
1544 dm_pci_read_config32(dev, ea_off, &ea_entry);
1545 ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
1546 ea_off += PCI_EA_FIRST_ENT;
1548 for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
1550 dm_pci_read_config32(dev, ea_off, &ea_entry);
1551 entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
1553 if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
1556 /* Base address, 1st DW */
1557 dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
1558 addr = ea_entry & PCI_EA_FIELD_MASK;
1559 if (ea_entry & PCI_EA_IS_64) {
1560 /* Base address, 2nd DW, skip over 4B MaxOffset */
1561 dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
1562 addr |= ((u64)ea_entry) << 32;
1565 if (IS_ENABLED(CONFIG_PCI_SRIOV))
1566 addr += dm_pci_map_ea_virt(dev, ea_off, pdata);
1568 if (~((phys_addr_t)0) - addr < offset)
1571 /* size ignored for now */
1572 return map_physmem(addr + offset, len, MAP_NOCACHE);
1578 void *dm_pci_map_bar(struct udevice *dev, int bar, size_t offset, size_t len,
1579 unsigned long mask, unsigned long flags)
1581 struct pci_child_plat *pdata = dev_get_parent_plat(dev);
1582 struct udevice *udev = dev;
1583 pci_addr_t pci_bus_addr;
1587 if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
1589 * In case of Virtual Function devices, use PF udevice
1590 * as EA capability is defined in Physical Function
1592 if (pdata->is_virtfn)
1593 udev = pdata->pfdev;
1597 * if the function supports Enhanced Allocation use that instead of
1599 * Incase of virtual functions, pdata will help read VF BEI
1600 * and EA entry size.
1602 if (IS_ENABLED(CONFIG_PCI_ENHANCED_ALLOCATION))
1603 ea_off = dm_pci_find_capability(udev, PCI_CAP_ID_EA);
1608 return dm_pci_map_ea_bar(udev, bar, offset, len, ea_off, pdata);
1610 /* read BAR address */
1611 dm_pci_read_config32(udev, bar, &bar_response);
1612 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1614 if (~((pci_addr_t)0) - pci_bus_addr < offset)
1618 * Forward the length argument to dm_pci_bus_to_virt. The length will
1619 * be used to check that the entire address range has been declared as
1620 * a PCI range, but a better check would be to probe for the size of
1621 * the bar and prevent overflow more locally.
1623 return dm_pci_bus_to_virt(udev, pci_bus_addr + offset, len, mask, flags,
1627 static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
1629 int ttl = PCI_FIND_CAP_TTL;
1633 dm_pci_read_config8(dev, pos, &pos);
1636 if (pos < PCI_STD_HEADER_SIZEOF)
1639 dm_pci_read_config16(dev, pos, &ent);
1652 int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap)
1654 return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT,
1658 int dm_pci_find_capability(struct udevice *dev, int cap)
1664 dm_pci_read_config16(dev, PCI_STATUS, &status);
1665 if (!(status & PCI_STATUS_CAP_LIST))
1668 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
1669 if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
1670 pos = PCI_CB_CAPABILITY_LIST;
1672 pos = PCI_CAPABILITY_LIST;
1674 return _dm_pci_find_next_capability(dev, pos, cap);
1677 int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap)
1681 int pos = PCI_CFG_SPACE_SIZE;
1683 /* minimum 8 bytes per capability */
1684 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1689 dm_pci_read_config32(dev, pos, &header);
1691 * If we have no capabilities, this is indicated by cap ID,
1692 * cap version and next pointer all being 0.
1698 if (PCI_EXT_CAP_ID(header) == cap)
1701 pos = PCI_EXT_CAP_NEXT(header);
1702 if (pos < PCI_CFG_SPACE_SIZE)
1705 dm_pci_read_config32(dev, pos, &header);
1711 int dm_pci_find_ext_capability(struct udevice *dev, int cap)
1713 return dm_pci_find_next_ext_capability(dev, 0, cap);
1716 int dm_pci_flr(struct udevice *dev)
1721 /* look for PCI Express Capability */
1722 pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
1726 /* check FLR capability */
1727 dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap);
1728 if (!(cap & PCI_EXP_DEVCAP_FLR))
1731 dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0,
1732 PCI_EXP_DEVCTL_BCR_FLR);
1734 /* wait 100ms, per PCI spec */
1740 #if defined(CONFIG_PCI_SRIOV)
1741 int pci_sriov_init(struct udevice *pdev, int vf_en)
1744 struct udevice *bus;
1745 struct udevice *dev;
1755 pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1757 debug("Error: SRIOV capability not found\n");
1761 dm_pci_read_config16(pdev, pos + PCI_SRIOV_CTRL, &ctrl);
1763 dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
1764 if (vf_en > total_vf)
1766 dm_pci_write_config16(pdev, pos + PCI_SRIOV_NUM_VF, vf_en);
1768 ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
1769 dm_pci_write_config16(pdev, pos + PCI_SRIOV_CTRL, ctrl);
1771 dm_pci_read_config16(pdev, pos + PCI_SRIOV_NUM_VF, &num_vfs);
1772 if (num_vfs > vf_en)
1775 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_OFFSET, &vf_offset);
1776 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_STRIDE, &vf_stride);
1778 dm_pci_read_config16(pdev, PCI_VENDOR_ID, &vendor);
1779 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_DID, &device);
1781 bdf = dm_pci_get_bdf(pdev);
1783 ret = pci_get_bus(PCI_BUS(bdf), &bus);
1787 bdf += PCI_BDF(0, 0, vf_offset);
1789 for (vf = 0; vf < num_vfs; vf++) {
1790 struct pci_child_plat *pplat;
1793 pci_bus_read_config(bus, bdf, PCI_CLASS_DEVICE,
1794 &class, PCI_SIZE_16);
1796 debug("%s: bus %d/%s: found VF %x:%x\n", __func__,
1797 dev_seq(bus), bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
1799 /* Find this device in the device tree */
1800 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
1802 if (ret == -ENODEV) {
1803 struct pci_device_id find_id;
1805 memset(&find_id, '\0', sizeof(find_id));
1806 find_id.vendor = vendor;
1807 find_id.device = device;
1808 find_id.class = class;
1810 ret = pci_find_and_bind_driver(bus, &find_id,
1817 /* Update the platform data */
1818 pplat = dev_get_parent_plat(dev);
1819 pplat->devfn = PCI_MASK_BUS(bdf);
1820 pplat->vendor = vendor;
1821 pplat->device = device;
1822 pplat->class = class;
1823 pplat->is_virtfn = true;
1824 pplat->pfdev = pdev;
1825 pplat->virtid = vf * vf_stride + vf_offset;
1827 debug("%s: bus %d/%s: found VF %x:%x %x:%x class %lx id %x\n",
1828 __func__, dev_seq(dev), dev->name, PCI_DEV(bdf),
1829 PCI_FUNC(bdf), vendor, device, class, pplat->virtid);
1830 bdf += PCI_BDF(0, 0, vf_stride);
1836 int pci_sriov_get_totalvfs(struct udevice *pdev)
1841 pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1843 debug("Error: SRIOV capability not found\n");
1847 dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
1853 UCLASS_DRIVER(pci) = {
1856 .flags = DM_UC_FLAG_SEQ_ALIAS | DM_UC_FLAG_NO_AUTO_SEQ,
1857 .post_bind = dm_scan_fdt_dev,
1858 .pre_probe = pci_uclass_pre_probe,
1859 .post_probe = pci_uclass_post_probe,
1860 .child_post_bind = pci_uclass_child_post_bind,
1861 .per_device_auto = sizeof(struct pci_controller),
1862 .per_child_plat_auto = sizeof(struct pci_child_plat),
1865 static const struct dm_pci_ops pci_bridge_ops = {
1866 .read_config = pci_bridge_read_config,
1867 .write_config = pci_bridge_write_config,
1870 static const struct udevice_id pci_bridge_ids[] = {
1871 { .compatible = "pci-bridge" },
1875 U_BOOT_DRIVER(pci_bridge_drv) = {
1876 .name = "pci_bridge_drv",
1878 .of_match = pci_bridge_ids,
1879 .ops = &pci_bridge_ops,
1882 UCLASS_DRIVER(pci_generic) = {
1883 .id = UCLASS_PCI_GENERIC,
1884 .name = "pci_generic",
1887 static const struct udevice_id pci_generic_ids[] = {
1888 { .compatible = "pci-generic" },
1892 U_BOOT_DRIVER(pci_generic_drv) = {
1893 .name = "pci_generic_drv",
1894 .id = UCLASS_PCI_GENERIC,
1895 .of_match = pci_generic_ids,
1900 struct udevice *bus;
1903 * Enumerate all known controller devices. Enumeration has the side-
1904 * effect of probing them, so PCIe devices will be enumerated too.
1906 for (uclass_first_device_check(UCLASS_PCI, &bus);
1908 uclass_next_device_check(&bus)) {