1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2014 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
15 #include <dm/device-internal.h>
17 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
18 #include <asm/fsp/fsp_support.h>
20 #include <linux/delay.h>
21 #include "pci_internal.h"
23 DECLARE_GLOBAL_DATA_PTR;
25 int pci_get_bus(int busnum, struct udevice **busp)
29 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
31 /* Since buses may not be numbered yet try a little harder with bus 0 */
33 ret = uclass_first_device_err(UCLASS_PCI, busp);
36 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
42 struct udevice *pci_get_controller(struct udevice *dev)
44 while (device_is_on_pci_bus(dev))
50 pci_dev_t dm_pci_get_bdf(const struct udevice *dev)
52 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
53 struct udevice *bus = dev->parent;
56 * This error indicates that @dev is a device on an unprobed PCI bus.
57 * The bus likely has bus=seq == -1, so the PCI_ADD_BUS() macro below
58 * will produce a bad BDF>
60 * A common cause of this problem is that this function is called in the
61 * ofdata_to_platdata() method of @dev. Accessing the PCI bus in that
62 * method is not allowed, since it has not yet been probed. To fix this,
63 * move that access to the probe() method of @dev instead.
65 if (!device_active(bus))
66 log_err("PCI: Device '%s' on unprobed bus '%s'\n", dev->name,
68 return PCI_ADD_BUS(bus->seq, pplat->devfn);
72 * pci_get_bus_max() - returns the bus number of the last active bus
74 * @return last bus number, or -1 if no active buses
76 static int pci_get_bus_max(void)
82 ret = uclass_get(UCLASS_PCI, &uc);
83 uclass_foreach_dev(bus, uc) {
88 debug("%s: ret=%d\n", __func__, ret);
93 int pci_last_busno(void)
95 return pci_get_bus_max();
98 int pci_get_ff(enum pci_size_t size)
110 static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
113 struct fdt_pci_addr addr;
117 dev_for_each_subnode(node, bus) {
118 ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
123 if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
131 int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
132 struct udevice **devp)
136 for (device_find_first_child(bus, &dev);
138 device_find_next_child(&dev)) {
139 struct pci_child_platdata *pplat;
141 pplat = dev_get_parent_platdata(dev);
142 if (pplat && pplat->devfn == find_devfn) {
151 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
156 ret = pci_get_bus(PCI_BUS(bdf), &bus);
159 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
162 static int pci_device_matches_ids(struct udevice *dev,
163 struct pci_device_id *ids)
165 struct pci_child_platdata *pplat;
168 pplat = dev_get_parent_platdata(dev);
171 for (i = 0; ids[i].vendor != 0; i++) {
172 if (pplat->vendor == ids[i].vendor &&
173 pplat->device == ids[i].device)
180 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
181 int *indexp, struct udevice **devp)
185 /* Scan all devices on this bus */
186 for (device_find_first_child(bus, &dev);
188 device_find_next_child(&dev)) {
189 if (pci_device_matches_ids(dev, ids) >= 0) {
190 if ((*indexp)-- <= 0) {
200 int pci_find_device_id(struct pci_device_id *ids, int index,
201 struct udevice **devp)
205 /* Scan all known buses */
206 for (uclass_first_device(UCLASS_PCI, &bus);
208 uclass_next_device(&bus)) {
209 if (!pci_bus_find_devices(bus, ids, &index, devp))
217 static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
218 unsigned int device, int *indexp,
219 struct udevice **devp)
221 struct pci_child_platdata *pplat;
224 for (device_find_first_child(bus, &dev);
226 device_find_next_child(&dev)) {
227 pplat = dev_get_parent_platdata(dev);
228 if (pplat->vendor == vendor && pplat->device == device) {
239 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
240 struct udevice **devp)
244 /* Scan all known buses */
245 for (uclass_first_device(UCLASS_PCI, &bus);
247 uclass_next_device(&bus)) {
248 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
249 return device_probe(*devp);
256 int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
260 /* Scan all known buses */
261 for (pci_find_first_device(&dev);
263 pci_find_next_device(&dev)) {
264 struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
266 if (pplat->class == find_class && !index--) {
268 return device_probe(*devp);
276 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
277 unsigned long value, enum pci_size_t size)
279 struct dm_pci_ops *ops;
281 ops = pci_get_ops(bus);
282 if (!ops->write_config)
284 return ops->write_config(bus, bdf, offset, value, size);
287 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
293 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
299 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
302 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
303 enum pci_size_t size)
308 ret = pci_get_bus(PCI_BUS(bdf), &bus);
312 return pci_bus_write_config(bus, bdf, offset, value, size);
315 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
316 enum pci_size_t size)
320 for (bus = dev; device_is_on_pci_bus(bus);)
322 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
326 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
328 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
331 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
333 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
336 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
338 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
341 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
343 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
346 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
348 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
351 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
353 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
356 int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
357 unsigned long *valuep, enum pci_size_t size)
359 struct dm_pci_ops *ops;
361 ops = pci_get_ops(bus);
362 if (!ops->read_config)
364 return ops->read_config(bus, bdf, offset, valuep, size);
367 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
368 enum pci_size_t size)
373 ret = pci_get_bus(PCI_BUS(bdf), &bus);
377 return pci_bus_read_config(bus, bdf, offset, valuep, size);
380 int dm_pci_read_config(const struct udevice *dev, int offset,
381 unsigned long *valuep, enum pci_size_t size)
383 const struct udevice *bus;
385 for (bus = dev; device_is_on_pci_bus(bus);)
387 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
391 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
396 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
404 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
409 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
417 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
422 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
430 int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep)
435 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
443 int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep)
448 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
456 int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep)
461 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
469 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
474 ret = dm_pci_read_config8(dev, offset, &val);
480 return dm_pci_write_config8(dev, offset, val);
483 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
488 ret = dm_pci_read_config16(dev, offset, &val);
494 return dm_pci_write_config16(dev, offset, val);
497 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
502 ret = dm_pci_read_config32(dev, offset, &val);
508 return dm_pci_write_config32(dev, offset, val);
511 static void set_vga_bridge_bits(struct udevice *dev)
513 struct udevice *parent = dev->parent;
516 while (parent->seq != 0) {
517 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
518 bc |= PCI_BRIDGE_CTL_VGA;
519 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
520 parent = parent->parent;
524 int pci_auto_config_devices(struct udevice *bus)
526 struct pci_controller *hose = bus->uclass_priv;
527 struct pci_child_platdata *pplat;
528 unsigned int sub_bus;
533 debug("%s: start\n", __func__);
534 pciauto_config_init(hose);
535 for (ret = device_find_first_child(bus, &dev);
537 ret = device_find_next_child(&dev)) {
538 unsigned int max_bus;
541 debug("%s: device %s\n", __func__, dev->name);
542 if (dev_read_bool(dev, "pci,no-autoconfig"))
544 ret = dm_pciauto_config_device(dev);
548 sub_bus = max(sub_bus, max_bus);
550 pplat = dev_get_parent_platdata(dev);
551 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
552 set_vga_bridge_bits(dev);
554 debug("%s: done\n", __func__);
559 int pci_generic_mmap_write_config(
560 const struct udevice *bus,
561 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
566 enum pci_size_t size)
570 if (addr_f(bus, bdf, offset, &address) < 0)
575 writeb(value, address);
578 writew(value, address);
581 writel(value, address);
588 int pci_generic_mmap_read_config(
589 const struct udevice *bus,
590 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
595 enum pci_size_t size)
599 if (addr_f(bus, bdf, offset, &address) < 0) {
600 *valuep = pci_get_ff(size);
606 *valuep = readb(address);
609 *valuep = readw(address);
612 *valuep = readl(address);
619 int dm_pci_hose_probe_bus(struct udevice *bus)
626 debug("%s\n", __func__);
628 ea_pos = dm_pci_find_capability(bus, PCI_CAP_ID_EA);
630 dm_pci_read_config8(bus, ea_pos + sizeof(u32) + sizeof(u8),
634 sub_bus = pci_get_bus_max() + 1;
636 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
637 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
639 ret = device_probe(bus);
641 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
647 if (sub_bus != bus->seq) {
648 debug("%s: Internal error, bus '%s' got seq %d, expected %d\n",
649 __func__, bus->name, bus->seq, sub_bus);
652 sub_bus = pci_get_bus_max();
654 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
660 * pci_match_one_device - Tell if a PCI device structure has a matching
661 * PCI device id structure
662 * @id: single PCI device id structure to match
663 * @find: the PCI device id structure to match against
665 * Returns true if the finding pci_device_id structure matched or false if
668 static bool pci_match_one_id(const struct pci_device_id *id,
669 const struct pci_device_id *find)
671 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
672 (id->device == PCI_ANY_ID || id->device == find->device) &&
673 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
674 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
675 !((id->class ^ find->class) & id->class_mask))
682 * pci_find_and_bind_driver() - Find and bind the right PCI driver
684 * This only looks at certain fields in the descriptor.
686 * @parent: Parent bus
687 * @find_id: Specification of the driver to find
688 * @bdf: Bus/device/function addreess - see PCI_BDF()
689 * @devp: Returns a pointer to the device created
690 * @return 0 if OK, -EPERM if the device is not needed before relocation and
691 * therefore was not created, other -ve value on error
693 static int pci_find_and_bind_driver(struct udevice *parent,
694 struct pci_device_id *find_id,
695 pci_dev_t bdf, struct udevice **devp)
697 struct pci_driver_entry *start, *entry;
698 ofnode node = ofnode_null();
707 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
708 find_id->vendor, find_id->device);
710 /* Determine optional OF node */
711 if (ofnode_valid(dev_ofnode(parent)))
712 pci_dev_find_ofnode(parent, bdf, &node);
714 if (ofnode_valid(node) && !ofnode_is_available(node)) {
715 debug("%s: Ignoring disabled device\n", __func__);
719 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
720 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
721 for (entry = start; entry != start + n_ents; entry++) {
722 const struct pci_device_id *id;
724 const struct driver *drv;
726 for (id = entry->match;
727 id->vendor || id->subvendor || id->class_mask;
729 if (!pci_match_one_id(id, find_id))
735 * In the pre-relocation phase, we only bind devices
736 * whose driver has the DM_FLAG_PRE_RELOC set, to save
737 * precious memory space as on some platforms as that
738 * space is pretty limited (ie: using Cache As RAM).
740 if (!(gd->flags & GD_FLG_RELOC) &&
741 !(drv->flags & DM_FLAG_PRE_RELOC))
745 * We could pass the descriptor to the driver as
746 * platdata (instead of NULL) and allow its bind()
747 * method to return -ENOENT if it doesn't support this
748 * device. That way we could continue the search to
749 * find another driver. For now this doesn't seem
750 * necesssary, so just bind the first match.
752 ret = device_bind_ofnode(parent, drv, drv->name, NULL,
756 debug("%s: Match found: %s\n", __func__, drv->name);
757 dev->driver_data = id->driver_data;
763 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
765 * In the pre-relocation phase, we only bind bridge devices to save
766 * precious memory space as on some platforms as that space is pretty
767 * limited (ie: using Cache As RAM).
769 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
772 /* Bind a generic driver so that the device can be used */
773 sprintf(name, "pci_%x:%x.%x", parent->seq, PCI_DEV(bdf),
778 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
780 ret = device_bind_driver_to_node(parent, drv, str, node, devp);
782 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
786 debug("%s: No match found: bound generic driver instead\n", __func__);
791 debug("%s: No match found: error %d\n", __func__, ret);
795 int pci_bind_bus_devices(struct udevice *bus)
797 ulong vendor, device;
804 end = PCI_BDF(bus->seq, PCI_MAX_PCI_DEVICES - 1,
805 PCI_MAX_PCI_FUNCTIONS - 1);
806 for (bdf = PCI_BDF(bus->seq, 0, 0); bdf <= end;
807 bdf += PCI_BDF(0, 0, 1)) {
808 struct pci_child_platdata *pplat;
814 if (PCI_FUNC(bdf) && !found_multi)
817 /* Check only the first access, we don't expect problems */
818 ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
823 if (vendor == 0xffff || vendor == 0x0000)
826 pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
827 &header_type, PCI_SIZE_8);
830 found_multi = header_type & 0x80;
832 debug("%s: bus %d/%s: found device %x, function %d", __func__,
833 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
834 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
836 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
840 /* Find this device in the device tree */
841 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
842 debug(": find ret=%d\n", ret);
844 /* If nothing in the device tree, bind a device */
845 if (ret == -ENODEV) {
846 struct pci_device_id find_id;
849 memset(&find_id, '\0', sizeof(find_id));
850 find_id.vendor = vendor;
851 find_id.device = device;
852 find_id.class = class;
853 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
854 pci_bus_read_config(bus, bdf,
855 PCI_SUBSYSTEM_VENDOR_ID,
857 find_id.subvendor = val & 0xffff;
858 find_id.subdevice = val >> 16;
860 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
868 /* Update the platform data */
869 pplat = dev_get_parent_platdata(dev);
870 pplat->devfn = PCI_MASK_BUS(bdf);
871 pplat->vendor = vendor;
872 pplat->device = device;
873 pplat->class = class;
878 printf("Cannot read bus configuration: %d\n", ret);
883 static void decode_regions(struct pci_controller *hose, ofnode parent_node,
886 int pci_addr_cells, addr_cells, size_cells;
887 struct bd_info *bd = gd->bd;
888 int cells_per_record;
894 prop = ofnode_get_property(node, "ranges", &len);
896 debug("%s: Cannot decode regions\n", __func__);
900 pci_addr_cells = ofnode_read_simple_addr_cells(node);
901 addr_cells = ofnode_read_simple_addr_cells(parent_node);
902 size_cells = ofnode_read_simple_size_cells(node);
904 /* PCI addresses are always 3-cells */
906 cells_per_record = pci_addr_cells + addr_cells + size_cells;
907 hose->region_count = 0;
908 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
911 /* Dynamically allocate the regions array */
912 max_regions = len / cells_per_record + CONFIG_NR_DRAM_BANKS;
913 hose->regions = (struct pci_region *)
914 calloc(1, max_regions * sizeof(struct pci_region));
916 for (i = 0; i < max_regions; i++, len -= cells_per_record) {
917 u64 pci_addr, addr, size;
923 if (len < cells_per_record)
925 flags = fdt32_to_cpu(prop[0]);
926 space_code = (flags >> 24) & 3;
927 pci_addr = fdtdec_get_number(prop + 1, 2);
928 prop += pci_addr_cells;
929 addr = fdtdec_get_number(prop, addr_cells);
931 size = fdtdec_get_number(prop, size_cells);
933 debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
934 __func__, hose->region_count, pci_addr, addr, size, space_code);
935 if (space_code & 2) {
936 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
938 } else if (space_code & 1) {
939 type = PCI_REGION_IO;
944 if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
945 type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
946 debug(" - beyond the 32-bit boundary, ignoring\n");
951 if (!IS_ENABLED(CONFIG_PCI_REGION_MULTI_ENTRY)) {
952 for (i = 0; i < hose->region_count; i++) {
953 if (hose->regions[i].flags == type)
959 pos = hose->region_count++;
960 debug(" - type=%d, pos=%d\n", type, pos);
961 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
964 /* Add a region for our local memory */
968 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
969 if (bd->bi_dram[i].size) {
970 pci_set_region(hose->regions + hose->region_count++,
971 bd->bi_dram[i].start,
972 bd->bi_dram[i].start,
974 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
981 static int pci_uclass_pre_probe(struct udevice *bus)
983 struct pci_controller *hose;
985 debug("%s, bus=%d/%s, parent=%s\n", __func__, bus->seq, bus->name,
987 hose = bus->uclass_priv;
989 /* For bridges, use the top-level PCI controller */
990 if (!device_is_on_pci_bus(bus)) {
992 decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
994 struct pci_controller *parent_hose;
996 parent_hose = dev_get_uclass_priv(bus->parent);
997 hose->ctlr = parent_hose->bus;
1000 hose->first_busno = bus->seq;
1001 hose->last_busno = bus->seq;
1002 hose->skip_auto_config_until_reloc =
1003 dev_read_bool(bus, "u-boot,skip-auto-config-until-reloc");
1008 static int pci_uclass_post_probe(struct udevice *bus)
1010 struct pci_controller *hose = dev_get_uclass_priv(bus);
1013 debug("%s: probing bus %d\n", __func__, bus->seq);
1014 ret = pci_bind_bus_devices(bus);
1018 if (CONFIG_IS_ENABLED(PCI_PNP) && ll_boot_init() &&
1019 (!hose->skip_auto_config_until_reloc ||
1020 (gd->flags & GD_FLG_RELOC))) {
1021 ret = pci_auto_config_devices(bus);
1023 return log_msg_ret("pci auto-config", ret);
1026 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
1028 * Per Intel FSP specification, we should call FSP notify API to
1029 * inform FSP that PCI enumeration has been done so that FSP will
1030 * do any necessary initialization as required by the chipset's
1031 * BIOS Writer's Guide (BWG).
1033 * Unfortunately we have to put this call here as with driver model,
1034 * the enumeration is all done on a lazy basis as needed, so until
1035 * something is touched on PCI it won't happen.
1037 * Note we only call this 1) after U-Boot is relocated, and 2)
1038 * root bus has finished probing.
1040 if ((gd->flags & GD_FLG_RELOC) && bus->seq == 0 && ll_boot_init()) {
1041 ret = fsp_init_phase_pci();
1050 static int pci_uclass_child_post_bind(struct udevice *dev)
1052 struct pci_child_platdata *pplat;
1054 if (!dev_of_valid(dev))
1057 pplat = dev_get_parent_platdata(dev);
1059 /* Extract vendor id and device id if available */
1060 ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
1062 /* Extract the devfn from fdt_pci_addr */
1063 pplat->devfn = pci_get_devfn(dev);
1068 static int pci_bridge_read_config(const struct udevice *bus, pci_dev_t bdf,
1069 uint offset, ulong *valuep,
1070 enum pci_size_t size)
1072 struct pci_controller *hose = bus->uclass_priv;
1074 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
1077 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
1078 uint offset, ulong value,
1079 enum pci_size_t size)
1081 struct pci_controller *hose = bus->uclass_priv;
1083 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
1086 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
1088 struct udevice *dev;
1092 * Scan through all the PCI controllers. On x86 there will only be one
1093 * but that is not necessarily true on other hardware.
1096 device_find_first_child(bus, &dev);
1101 ret = uclass_next_device(&bus);
1109 int pci_find_next_device(struct udevice **devp)
1111 struct udevice *child = *devp;
1112 struct udevice *bus = child->parent;
1115 /* First try all the siblings */
1118 device_find_next_child(&child);
1125 /* We ran out of siblings. Try the next bus */
1126 ret = uclass_next_device(&bus);
1130 return bus ? skip_to_next_device(bus, devp) : 0;
1133 int pci_find_first_device(struct udevice **devp)
1135 struct udevice *bus;
1139 ret = uclass_first_device(UCLASS_PCI, &bus);
1143 return skip_to_next_device(bus, devp);
1146 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1150 return (value >> ((offset & 3) * 8)) & 0xff;
1152 return (value >> ((offset & 2) * 8)) & 0xffff;
1158 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1159 enum pci_size_t size)
1162 uint val_mask, shift;
1177 shift = (offset & off_mask) * 8;
1178 ldata = (value & val_mask) << shift;
1179 mask = val_mask << shift;
1180 value = (old & ~mask) | ldata;
1185 int pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int index)
1187 int pci_addr_cells, addr_cells, size_cells;
1188 int cells_per_record;
1193 prop = ofnode_get_property(dev_ofnode(dev), "dma-ranges", &len);
1195 log_err("PCI: Device '%s': Cannot decode dma-ranges\n",
1200 pci_addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev));
1201 addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev->parent));
1202 size_cells = ofnode_read_simple_size_cells(dev_ofnode(dev));
1204 /* PCI addresses are always 3-cells */
1206 cells_per_record = pci_addr_cells + addr_cells + size_cells;
1207 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
1211 memp->bus_start = fdtdec_get_number(prop + 1, 2);
1212 prop += pci_addr_cells;
1213 memp->phys_start = fdtdec_get_number(prop, addr_cells);
1215 memp->size = fdtdec_get_number(prop, size_cells);
1221 len -= cells_per_record;
1227 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1228 struct pci_region **memp, struct pci_region **prefp)
1230 struct udevice *bus = pci_get_controller(dev);
1231 struct pci_controller *hose = dev_get_uclass_priv(bus);
1237 for (i = 0; i < hose->region_count; i++) {
1238 switch (hose->regions[i].flags) {
1240 if (!*iop || (*iop)->size < hose->regions[i].size)
1241 *iop = hose->regions + i;
1243 case PCI_REGION_MEM:
1244 if (!*memp || (*memp)->size < hose->regions[i].size)
1245 *memp = hose->regions + i;
1247 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1248 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1249 *prefp = hose->regions + i;
1254 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1257 u32 dm_pci_read_bar32(const struct udevice *dev, int barnum)
1262 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1263 dm_pci_read_config32(dev, bar, &addr);
1266 * If we get an invalid address, return this so that comparisons with
1267 * FDT_ADDR_T_NONE work correctly
1269 if (addr == 0xffffffff)
1271 else if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1272 return addr & PCI_BASE_ADDRESS_IO_MASK;
1274 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1277 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1281 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1282 dm_pci_write_config32(dev, bar, addr);
1285 static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1286 pci_addr_t bus_addr, unsigned long flags,
1287 unsigned long skip_mask, phys_addr_t *pa)
1289 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1290 struct pci_region *res;
1293 if (hose->region_count == 0) {
1298 for (i = 0; i < hose->region_count; i++) {
1299 res = &hose->regions[i];
1301 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1304 if (res->flags & skip_mask)
1307 if (bus_addr >= res->bus_start &&
1308 (bus_addr - res->bus_start) < res->size) {
1309 *pa = (bus_addr - res->bus_start + res->phys_start);
1317 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1318 unsigned long flags)
1320 phys_addr_t phys_addr = 0;
1321 struct udevice *ctlr;
1324 /* The root controller has the region information */
1325 ctlr = pci_get_controller(dev);
1328 * if PCI_REGION_MEM is set we do a two pass search with preference
1329 * on matches that don't have PCI_REGION_SYS_MEMORY set
1331 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1332 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1333 flags, PCI_REGION_SYS_MEMORY,
1339 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1342 puts("pci_hose_bus_to_phys: invalid physical address\n");
1347 int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1348 unsigned long flags, unsigned long skip_mask,
1351 struct pci_region *res;
1352 struct udevice *ctlr;
1353 pci_addr_t bus_addr;
1355 struct pci_controller *hose;
1357 /* The root controller has the region information */
1358 ctlr = pci_get_controller(dev);
1359 hose = dev_get_uclass_priv(ctlr);
1361 if (hose->region_count == 0) {
1366 for (i = 0; i < hose->region_count; i++) {
1367 res = &hose->regions[i];
1369 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1372 if (res->flags & skip_mask)
1375 bus_addr = phys_addr - res->phys_start + res->bus_start;
1377 if (bus_addr >= res->bus_start &&
1378 (bus_addr - res->bus_start) < res->size) {
1387 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1388 unsigned long flags)
1390 pci_addr_t bus_addr = 0;
1394 * if PCI_REGION_MEM is set we do a two pass search with preference
1395 * on matches that don't have PCI_REGION_SYS_MEMORY set
1397 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1398 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1399 PCI_REGION_SYS_MEMORY, &bus_addr);
1404 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1407 puts("pci_hose_phys_to_bus: invalid physical address\n");
1412 static phys_addr_t dm_pci_map_ea_virt(struct udevice *dev, int ea_off,
1413 struct pci_child_platdata *pdata)
1415 phys_addr_t addr = 0;
1418 * In the case of a Virtual Function device using BAR
1419 * base and size, add offset for VFn BAR(1, 2, 3...n)
1421 if (pdata->is_virtfn) {
1425 /* MaxOffset, 1st DW */
1426 dm_pci_read_config32(dev, ea_off + 8, &ea_entry);
1427 sz = ea_entry & PCI_EA_FIELD_MASK;
1428 /* Fill up lower 2 bits */
1429 sz |= (~PCI_EA_FIELD_MASK);
1431 if (ea_entry & PCI_EA_IS_64) {
1432 /* MaxOffset 2nd DW */
1433 dm_pci_read_config32(dev, ea_off + 16, &ea_entry);
1434 sz |= ((u64)ea_entry) << 32;
1437 addr = (pdata->virtid - 1) * (sz + 1);
1443 static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
1444 int ea_off, struct pci_child_platdata *pdata)
1446 int ea_cnt, i, entry_size;
1447 int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
1451 if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
1453 * In the case of a Virtual Function device, device is
1454 * Physical function, so pdata will point to required VF
1457 if (pdata->is_virtfn)
1458 bar_id += PCI_EA_BEI_VF_BAR0;
1461 /* EA capability structure header */
1462 dm_pci_read_config32(dev, ea_off, &ea_entry);
1463 ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
1464 ea_off += PCI_EA_FIRST_ENT;
1466 for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
1468 dm_pci_read_config32(dev, ea_off, &ea_entry);
1469 entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
1471 if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
1474 /* Base address, 1st DW */
1475 dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
1476 addr = ea_entry & PCI_EA_FIELD_MASK;
1477 if (ea_entry & PCI_EA_IS_64) {
1478 /* Base address, 2nd DW, skip over 4B MaxOffset */
1479 dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
1480 addr |= ((u64)ea_entry) << 32;
1483 if (IS_ENABLED(CONFIG_PCI_SRIOV))
1484 addr += dm_pci_map_ea_virt(dev, ea_off, pdata);
1486 /* size ignored for now */
1487 return map_physmem(addr, 0, flags);
1493 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1495 struct pci_child_platdata *pdata = dev_get_parent_platdata(dev);
1496 struct udevice *udev = dev;
1497 pci_addr_t pci_bus_addr;
1501 if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
1503 * In case of Virtual Function devices, use PF udevice
1504 * as EA capability is defined in Physical Function
1506 if (pdata->is_virtfn)
1507 udev = pdata->pfdev;
1511 * if the function supports Enhanced Allocation use that instead of
1513 * Incase of virtual functions, pdata will help read VF BEI
1514 * and EA entry size.
1516 ea_off = dm_pci_find_capability(udev, PCI_CAP_ID_EA);
1518 return dm_pci_map_ea_bar(udev, bar, flags, ea_off, pdata);
1520 /* read BAR address */
1521 dm_pci_read_config32(udev, bar, &bar_response);
1522 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1525 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1526 * isn't actually used on any platform because U-Boot assumes a static
1527 * linear mapping. In the future, this could read the BAR size
1528 * and pass that as the size if needed.
1530 return dm_pci_bus_to_virt(udev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1533 static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
1535 int ttl = PCI_FIND_CAP_TTL;
1539 dm_pci_read_config8(dev, pos, &pos);
1542 if (pos < PCI_STD_HEADER_SIZEOF)
1545 dm_pci_read_config16(dev, pos, &ent);
1558 int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap)
1560 return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT,
1564 int dm_pci_find_capability(struct udevice *dev, int cap)
1570 dm_pci_read_config16(dev, PCI_STATUS, &status);
1571 if (!(status & PCI_STATUS_CAP_LIST))
1574 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
1575 if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
1576 pos = PCI_CB_CAPABILITY_LIST;
1578 pos = PCI_CAPABILITY_LIST;
1580 return _dm_pci_find_next_capability(dev, pos, cap);
1583 int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap)
1587 int pos = PCI_CFG_SPACE_SIZE;
1589 /* minimum 8 bytes per capability */
1590 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1595 dm_pci_read_config32(dev, pos, &header);
1597 * If we have no capabilities, this is indicated by cap ID,
1598 * cap version and next pointer all being 0.
1604 if (PCI_EXT_CAP_ID(header) == cap)
1607 pos = PCI_EXT_CAP_NEXT(header);
1608 if (pos < PCI_CFG_SPACE_SIZE)
1611 dm_pci_read_config32(dev, pos, &header);
1617 int dm_pci_find_ext_capability(struct udevice *dev, int cap)
1619 return dm_pci_find_next_ext_capability(dev, 0, cap);
1622 int dm_pci_flr(struct udevice *dev)
1627 /* look for PCI Express Capability */
1628 pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
1632 /* check FLR capability */
1633 dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap);
1634 if (!(cap & PCI_EXP_DEVCAP_FLR))
1637 dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0,
1638 PCI_EXP_DEVCTL_BCR_FLR);
1640 /* wait 100ms, per PCI spec */
1646 #if defined(CONFIG_PCI_SRIOV)
1647 int pci_sriov_init(struct udevice *pdev, int vf_en)
1650 struct udevice *bus;
1651 struct udevice *dev;
1661 pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1663 debug("Error: SRIOV capability not found\n");
1667 dm_pci_read_config16(pdev, pos + PCI_SRIOV_CTRL, &ctrl);
1669 dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
1670 if (vf_en > total_vf)
1672 dm_pci_write_config16(pdev, pos + PCI_SRIOV_NUM_VF, vf_en);
1674 ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
1675 dm_pci_write_config16(pdev, pos + PCI_SRIOV_CTRL, ctrl);
1677 dm_pci_read_config16(pdev, pos + PCI_SRIOV_NUM_VF, &num_vfs);
1678 if (num_vfs > vf_en)
1681 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_OFFSET, &vf_offset);
1682 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_STRIDE, &vf_stride);
1684 dm_pci_read_config16(pdev, PCI_VENDOR_ID, &vendor);
1685 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_DID, &device);
1687 bdf = dm_pci_get_bdf(pdev);
1689 pci_get_bus(PCI_BUS(bdf), &bus);
1694 bdf += PCI_BDF(0, 0, vf_offset);
1696 for (vf = 0; vf < num_vfs; vf++) {
1697 struct pci_child_platdata *pplat;
1700 pci_bus_read_config(bus, bdf, PCI_CLASS_DEVICE,
1701 &class, PCI_SIZE_16);
1703 debug("%s: bus %d/%s: found VF %x:%x\n", __func__,
1704 bus->seq, bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
1706 /* Find this device in the device tree */
1707 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
1709 if (ret == -ENODEV) {
1710 struct pci_device_id find_id;
1712 memset(&find_id, '\0', sizeof(find_id));
1713 find_id.vendor = vendor;
1714 find_id.device = device;
1715 find_id.class = class;
1717 ret = pci_find_and_bind_driver(bus, &find_id,
1724 /* Update the platform data */
1725 pplat = dev_get_parent_platdata(dev);
1726 pplat->devfn = PCI_MASK_BUS(bdf);
1727 pplat->vendor = vendor;
1728 pplat->device = device;
1729 pplat->class = class;
1730 pplat->is_virtfn = true;
1731 pplat->pfdev = pdev;
1732 pplat->virtid = vf * vf_stride + vf_offset;
1734 debug("%s: bus %d/%s: found VF %x:%x %x:%x class %lx id %x\n",
1735 __func__, dev->seq, dev->name, PCI_DEV(bdf),
1736 PCI_FUNC(bdf), vendor, device, class, pplat->virtid);
1737 bdf += PCI_BDF(0, 0, vf_stride);
1743 int pci_sriov_get_totalvfs(struct udevice *pdev)
1748 pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1750 debug("Error: SRIOV capability not found\n");
1754 dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
1760 UCLASS_DRIVER(pci) = {
1763 .flags = DM_UC_FLAG_SEQ_ALIAS,
1764 .post_bind = dm_scan_fdt_dev,
1765 .pre_probe = pci_uclass_pre_probe,
1766 .post_probe = pci_uclass_post_probe,
1767 .child_post_bind = pci_uclass_child_post_bind,
1768 .per_device_auto_alloc_size = sizeof(struct pci_controller),
1769 .per_child_platdata_auto_alloc_size =
1770 sizeof(struct pci_child_platdata),
1773 static const struct dm_pci_ops pci_bridge_ops = {
1774 .read_config = pci_bridge_read_config,
1775 .write_config = pci_bridge_write_config,
1778 static const struct udevice_id pci_bridge_ids[] = {
1779 { .compatible = "pci-bridge" },
1783 U_BOOT_DRIVER(pci_bridge_drv) = {
1784 .name = "pci_bridge_drv",
1786 .of_match = pci_bridge_ids,
1787 .ops = &pci_bridge_ops,
1790 UCLASS_DRIVER(pci_generic) = {
1791 .id = UCLASS_PCI_GENERIC,
1792 .name = "pci_generic",
1795 static const struct udevice_id pci_generic_ids[] = {
1796 { .compatible = "pci-generic" },
1800 U_BOOT_DRIVER(pci_generic_drv) = {
1801 .name = "pci_generic_drv",
1802 .id = UCLASS_PCI_GENERIC,
1803 .of_match = pci_generic_ids,
1808 struct udevice *bus;
1811 * Enumerate all known controller devices. Enumeration has the side-
1812 * effect of probing them, so PCIe devices will be enumerated too.
1814 for (uclass_first_device_check(UCLASS_PCI, &bus);
1816 uclass_next_device_check(&bus)) {