1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2014 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
7 #define LOG_CATEGORY UCLASS_PCI
16 #include <asm/global_data.h>
18 #include <dm/device-internal.h>
20 #include <dm/uclass-internal.h>
21 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
22 #include <asm/fsp/fsp_support.h>
24 #include <dt-bindings/pci/pci.h>
25 #include <linux/delay.h>
26 #include "pci_internal.h"
28 DECLARE_GLOBAL_DATA_PTR;
30 int pci_get_bus(int busnum, struct udevice **busp)
34 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
36 /* Since buses may not be numbered yet try a little harder with bus 0 */
38 ret = uclass_first_device_err(UCLASS_PCI, busp);
41 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
47 struct udevice *pci_get_controller(struct udevice *dev)
49 while (device_is_on_pci_bus(dev))
55 pci_dev_t dm_pci_get_bdf(const struct udevice *dev)
57 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
58 struct udevice *bus = dev->parent;
61 * This error indicates that @dev is a device on an unprobed PCI bus.
62 * The bus likely has bus=seq == -1, so the PCI_ADD_BUS() macro below
63 * will produce a bad BDF>
65 * A common cause of this problem is that this function is called in the
66 * of_to_plat() method of @dev. Accessing the PCI bus in that
67 * method is not allowed, since it has not yet been probed. To fix this,
68 * move that access to the probe() method of @dev instead.
70 if (!device_active(bus))
71 log_err("PCI: Device '%s' on unprobed bus '%s'\n", dev->name,
73 return PCI_ADD_BUS(dev_seq(bus), pplat->devfn);
77 * pci_get_bus_max() - returns the bus number of the last active bus
79 * Return: last bus number, or -1 if no active buses
81 static int pci_get_bus_max(void)
87 ret = uclass_get(UCLASS_PCI, &uc);
88 uclass_foreach_dev(bus, uc) {
89 if (dev_seq(bus) > ret)
93 debug("%s: ret=%d\n", __func__, ret);
98 int pci_last_busno(void)
100 return pci_get_bus_max();
103 int pci_get_ff(enum pci_size_t size)
115 static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
118 struct fdt_pci_addr addr;
122 dev_for_each_subnode(node, bus) {
123 ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
128 if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
136 int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
137 struct udevice **devp)
141 for (device_find_first_child(bus, &dev);
143 device_find_next_child(&dev)) {
144 struct pci_child_plat *pplat;
146 pplat = dev_get_parent_plat(dev);
147 if (pplat && pplat->devfn == find_devfn) {
156 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
161 ret = pci_get_bus(PCI_BUS(bdf), &bus);
164 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
167 static int pci_device_matches_ids(struct udevice *dev,
168 const struct pci_device_id *ids)
170 struct pci_child_plat *pplat;
173 pplat = dev_get_parent_plat(dev);
176 for (i = 0; ids[i].vendor != 0; i++) {
177 if (pplat->vendor == ids[i].vendor &&
178 pplat->device == ids[i].device)
185 int pci_bus_find_devices(struct udevice *bus, const struct pci_device_id *ids,
186 int *indexp, struct udevice **devp)
190 /* Scan all devices on this bus */
191 for (device_find_first_child(bus, &dev);
193 device_find_next_child(&dev)) {
194 if (pci_device_matches_ids(dev, ids) >= 0) {
195 if ((*indexp)-- <= 0) {
205 int pci_find_device_id(const struct pci_device_id *ids, int index,
206 struct udevice **devp)
210 /* Scan all known buses */
211 for (uclass_first_device(UCLASS_PCI, &bus);
213 uclass_next_device(&bus)) {
214 if (!pci_bus_find_devices(bus, ids, &index, devp))
222 static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
223 unsigned int device, int *indexp,
224 struct udevice **devp)
226 struct pci_child_plat *pplat;
229 for (device_find_first_child(bus, &dev);
231 device_find_next_child(&dev)) {
232 pplat = dev_get_parent_plat(dev);
233 if (pplat->vendor == vendor && pplat->device == device) {
244 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
245 struct udevice **devp)
249 /* Scan all known buses */
250 for (uclass_first_device(UCLASS_PCI, &bus);
252 uclass_next_device(&bus)) {
253 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
254 return device_probe(*devp);
261 int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
265 /* Scan all known buses */
266 for (pci_find_first_device(&dev);
268 pci_find_next_device(&dev)) {
269 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
271 if (pplat->class == find_class && !index--) {
273 return device_probe(*devp);
281 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
282 unsigned long value, enum pci_size_t size)
284 struct dm_pci_ops *ops;
286 ops = pci_get_ops(bus);
287 if (!ops->write_config)
289 return ops->write_config(bus, bdf, offset, value, size);
292 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
298 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
304 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
307 static int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
308 enum pci_size_t size)
313 ret = pci_get_bus(PCI_BUS(bdf), &bus);
317 return pci_bus_write_config(bus, bdf, offset, value, size);
320 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
321 enum pci_size_t size)
325 for (bus = dev; device_is_on_pci_bus(bus);)
327 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
331 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
333 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
336 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
338 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
341 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
343 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
346 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
348 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
351 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
353 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
356 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
358 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
361 int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
362 unsigned long *valuep, enum pci_size_t size)
364 struct dm_pci_ops *ops;
366 ops = pci_get_ops(bus);
367 if (!ops->read_config)
369 return ops->read_config(bus, bdf, offset, valuep, size);
372 static int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
373 enum pci_size_t size)
378 ret = pci_get_bus(PCI_BUS(bdf), &bus);
382 return pci_bus_read_config(bus, bdf, offset, valuep, size);
385 int dm_pci_read_config(const struct udevice *dev, int offset,
386 unsigned long *valuep, enum pci_size_t size)
388 const struct udevice *bus;
390 for (bus = dev; device_is_on_pci_bus(bus);)
392 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
396 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
401 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
409 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
414 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
422 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
427 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
435 int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep)
440 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
448 int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep)
453 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
461 int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep)
466 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
474 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
479 ret = dm_pci_read_config8(dev, offset, &val);
485 return dm_pci_write_config8(dev, offset, val);
488 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
493 ret = dm_pci_read_config16(dev, offset, &val);
499 return dm_pci_write_config16(dev, offset, val);
502 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
507 ret = dm_pci_read_config32(dev, offset, &val);
513 return dm_pci_write_config32(dev, offset, val);
516 static void set_vga_bridge_bits(struct udevice *dev)
518 struct udevice *parent = dev->parent;
521 while (dev_seq(parent) != 0) {
522 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
523 bc |= PCI_BRIDGE_CTL_VGA;
524 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
525 parent = parent->parent;
529 int pci_auto_config_devices(struct udevice *bus)
531 struct pci_controller *hose = dev_get_uclass_priv(bus);
532 struct pci_child_plat *pplat;
533 unsigned int sub_bus;
537 sub_bus = dev_seq(bus);
538 debug("%s: start\n", __func__);
539 pciauto_config_init(hose);
540 for (ret = device_find_first_child(bus, &dev);
542 ret = device_find_next_child(&dev)) {
543 unsigned int max_bus;
546 debug("%s: device %s\n", __func__, dev->name);
547 if (dev_has_ofnode(dev) &&
548 dev_read_bool(dev, "pci,no-autoconfig"))
550 ret = dm_pciauto_config_device(dev);
552 return log_msg_ret("auto", ret);
554 sub_bus = max(sub_bus, max_bus);
556 if (dev_get_parent(dev) == bus)
559 pplat = dev_get_parent_plat(dev);
560 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
561 set_vga_bridge_bits(dev);
563 if (hose->last_busno < sub_bus)
564 hose->last_busno = sub_bus;
565 debug("%s: done\n", __func__);
567 return log_msg_ret("sub", sub_bus);
570 int pci_generic_mmap_write_config(
571 const struct udevice *bus,
572 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
577 enum pci_size_t size)
581 if (addr_f(bus, bdf, offset, &address) < 0)
586 writeb(value, address);
589 writew(value, address);
592 writel(value, address);
599 int pci_generic_mmap_read_config(
600 const struct udevice *bus,
601 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
606 enum pci_size_t size)
610 if (addr_f(bus, bdf, offset, &address) < 0) {
611 *valuep = pci_get_ff(size);
617 *valuep = readb(address);
620 *valuep = readw(address);
623 *valuep = readl(address);
630 int dm_pci_hose_probe_bus(struct udevice *bus)
638 debug("%s\n", __func__);
640 dm_pci_read_config8(bus, PCI_HEADER_TYPE, &header_type);
642 if (header_type != PCI_HEADER_TYPE_BRIDGE) {
643 debug("%s: Skipping PCI device %d with Non-Bridge Header Type 0x%x\n",
644 __func__, PCI_DEV(dm_pci_get_bdf(bus)), header_type);
645 return log_msg_ret("probe", -EINVAL);
648 if (IS_ENABLED(CONFIG_PCI_ENHANCED_ALLOCATION))
649 ea_pos = dm_pci_find_capability(bus, PCI_CAP_ID_EA);
654 dm_pci_read_config8(bus, ea_pos + sizeof(u32) + sizeof(u8),
658 sub_bus = pci_get_bus_max() + 1;
660 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
661 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
663 ret = device_probe(bus);
665 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
667 return log_msg_ret("probe", ret);
671 sub_bus = pci_get_bus_max();
673 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
679 * pci_match_one_device - Tell if a PCI device structure has a matching
680 * PCI device id structure
681 * @id: single PCI device id structure to match
682 * @find: the PCI device id structure to match against
684 * Returns true if the finding pci_device_id structure matched or false if
687 static bool pci_match_one_id(const struct pci_device_id *id,
688 const struct pci_device_id *find)
690 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
691 (id->device == PCI_ANY_ID || id->device == find->device) &&
692 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
693 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
694 !((id->class ^ find->class) & id->class_mask))
701 * pci_need_device_pre_reloc() - Check if a device should be bound
703 * This checks a list of vendor/device-ID values indicating devices that should
704 * be bound before relocation.
707 * @vendor: Vendor ID to check
708 * @device: Device ID to check
709 * Return: true if the vendor/device is in the list, false if not
711 static bool pci_need_device_pre_reloc(struct udevice *bus, uint vendor,
718 !dev_read_u32_index(bus, "u-boot,pci-pre-reloc", index,
721 if (vendev == PCI_VENDEV(vendor, device))
729 * pci_find_and_bind_driver() - Find and bind the right PCI driver
731 * This only looks at certain fields in the descriptor.
733 * @parent: Parent bus
734 * @find_id: Specification of the driver to find
735 * @bdf: Bus/device/function addreess - see PCI_BDF()
736 * @devp: Returns a pointer to the device created
737 * Return: 0 if OK, -EPERM if the device is not needed before relocation and
738 * therefore was not created, other -ve value on error
740 static int pci_find_and_bind_driver(struct udevice *parent,
741 struct pci_device_id *find_id,
742 pci_dev_t bdf, struct udevice **devp)
744 struct pci_driver_entry *start, *entry;
745 ofnode node = ofnode_null();
754 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
755 find_id->vendor, find_id->device);
757 /* Determine optional OF node */
758 if (ofnode_valid(dev_ofnode(parent)))
759 pci_dev_find_ofnode(parent, bdf, &node);
761 if (ofnode_valid(node) && !ofnode_is_available(node)) {
762 debug("%s: Ignoring disabled device\n", __func__);
763 return log_msg_ret("dis", -EPERM);
766 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
767 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
768 for (entry = start; entry != start + n_ents; entry++) {
769 const struct pci_device_id *id;
771 const struct driver *drv;
773 for (id = entry->match;
774 id->vendor || id->subvendor || id->class_mask;
776 if (!pci_match_one_id(id, find_id))
782 * In the pre-relocation phase, we only bind devices
783 * whose driver has the DM_FLAG_PRE_RELOC set, to save
784 * precious memory space as on some platforms as that
785 * space is pretty limited (ie: using Cache As RAM).
787 if (!(gd->flags & GD_FLG_RELOC) &&
788 !(drv->flags & DM_FLAG_PRE_RELOC))
789 return log_msg_ret("pre", -EPERM);
792 * We could pass the descriptor to the driver as
793 * plat (instead of NULL) and allow its bind()
794 * method to return -ENOENT if it doesn't support this
795 * device. That way we could continue the search to
796 * find another driver. For now this doesn't seem
797 * necesssary, so just bind the first match.
799 ret = device_bind(parent, drv, drv->name, NULL, node,
803 debug("%s: Match found: %s\n", __func__, drv->name);
804 dev->driver_data = id->driver_data;
810 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
812 * In the pre-relocation phase, we only bind bridge devices to save
813 * precious memory space as on some platforms as that space is pretty
814 * limited (ie: using Cache As RAM).
816 if (!(gd->flags & GD_FLG_RELOC) && !bridge &&
817 !pci_need_device_pre_reloc(parent, find_id->vendor,
819 return log_msg_ret("notbr", -EPERM);
821 /* Bind a generic driver so that the device can be used */
822 sprintf(name, "pci_%x:%x.%x", dev_seq(parent), PCI_DEV(bdf),
827 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
829 ret = device_bind_driver_to_node(parent, drv, str, node, devp);
831 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
835 debug("%s: No match found: bound generic driver instead\n", __func__);
840 debug("%s: No match found: error %d\n", __func__, ret);
844 __weak extern void board_pci_fixup_dev(struct udevice *bus, struct udevice *dev)
848 int pci_bind_bus_devices(struct udevice *bus)
850 ulong vendor, device;
858 end = PCI_BDF(dev_seq(bus), PCI_MAX_PCI_DEVICES - 1,
859 PCI_MAX_PCI_FUNCTIONS - 1);
860 for (bdf = PCI_BDF(dev_seq(bus), 0, 0); bdf <= end;
861 bdf += PCI_BDF(0, 0, 1)) {
862 struct pci_child_plat *pplat;
868 if (PCI_FUNC(bdf) && !found_multi)
871 /* Check only the first access, we don't expect problems */
872 ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
874 if (ret || vendor == 0xffff || vendor == 0x0000)
877 pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
878 &header_type, PCI_SIZE_8);
881 found_multi = header_type & 0x80;
883 debug("%s: bus %d/%s: found device %x, function %d", __func__,
884 dev_seq(bus), bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
885 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
887 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
891 /* Find this device in the device tree */
892 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
893 debug(": find ret=%d\n", ret);
895 /* If nothing in the device tree, bind a device */
896 if (ret == -ENODEV) {
897 struct pci_device_id find_id;
900 memset(&find_id, '\0', sizeof(find_id));
901 find_id.vendor = vendor;
902 find_id.device = device;
903 find_id.class = class;
904 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
905 pci_bus_read_config(bus, bdf,
906 PCI_SUBSYSTEM_VENDOR_ID,
908 find_id.subvendor = val & 0xffff;
909 find_id.subdevice = val >> 16;
911 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
919 /* Update the platform data */
920 pplat = dev_get_parent_plat(dev);
921 pplat->devfn = PCI_MASK_BUS(bdf);
922 pplat->vendor = vendor;
923 pplat->device = device;
924 pplat->class = class;
926 if (IS_ENABLED(CONFIG_PCI_ARID)) {
927 ari_off = dm_pci_find_ext_capability(dev,
933 * Read Next Function number in ARI Cap
936 dm_pci_read_config16(dev, ari_off + 4,
939 * Update next scan on this function number,
940 * subtract 1 in BDF to satisfy loop increment.
942 if (ari_cap & 0xff00) {
943 bdf = PCI_BDF(PCI_BUS(bdf),
951 board_pci_fixup_dev(bus, dev);
957 static int decode_regions(struct pci_controller *hose, ofnode parent_node,
960 int pci_addr_cells, addr_cells, size_cells;
961 int cells_per_record;
968 prop = ofnode_get_property(node, "ranges", &len);
970 debug("%s: Cannot decode regions\n", __func__);
974 pci_addr_cells = ofnode_read_simple_addr_cells(node);
975 addr_cells = ofnode_read_simple_addr_cells(parent_node);
976 size_cells = ofnode_read_simple_size_cells(node);
978 /* PCI addresses are always 3-cells */
980 cells_per_record = pci_addr_cells + addr_cells + size_cells;
981 hose->region_count = 0;
982 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
985 /* Dynamically allocate the regions array */
986 max_regions = len / cells_per_record + CONFIG_NR_DRAM_BANKS;
987 hose->regions = (struct pci_region *)
988 calloc(1, max_regions * sizeof(struct pci_region));
992 for (i = 0; i < max_regions; i++, len -= cells_per_record) {
993 u64 pci_addr, addr, size;
999 if (len < cells_per_record)
1001 flags = fdt32_to_cpu(prop[0]);
1002 space_code = (flags >> 24) & 3;
1003 pci_addr = fdtdec_get_number(prop + 1, 2);
1004 prop += pci_addr_cells;
1005 addr = fdtdec_get_number(prop, addr_cells);
1007 size = fdtdec_get_number(prop, size_cells);
1009 debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
1010 __func__, hose->region_count, pci_addr, addr, size, space_code);
1011 if (space_code & 2) {
1012 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
1014 } else if (space_code & 1) {
1015 type = PCI_REGION_IO;
1020 if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
1021 type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
1022 debug(" - pci_addr beyond the 32-bit boundary, ignoring\n");
1026 if (!IS_ENABLED(CONFIG_PHYS_64BIT) && upper_32_bits(addr)) {
1027 debug(" - addr beyond the 32-bit boundary, ignoring\n");
1031 if (~((pci_addr_t)0) - pci_addr < size) {
1032 debug(" - PCI range exceeds max address, ignoring\n");
1036 if (~((phys_addr_t)0) - addr < size) {
1037 debug(" - phys range exceeds max address, ignoring\n");
1042 if (!IS_ENABLED(CONFIG_PCI_REGION_MULTI_ENTRY)) {
1043 for (i = 0; i < hose->region_count; i++) {
1044 if (hose->regions[i].flags == type)
1050 pos = hose->region_count++;
1051 debug(" - type=%d, pos=%d\n", type, pos);
1052 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
1055 /* Add a region for our local memory */
1060 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
1061 if (bd->bi_dram[i].size) {
1062 phys_addr_t start = bd->bi_dram[i].start;
1064 if (IS_ENABLED(CONFIG_PCI_MAP_SYSTEM_MEMORY))
1065 start = virt_to_phys((void *)(uintptr_t)bd->bi_dram[i].start);
1067 pci_set_region(hose->regions + hose->region_count++,
1068 start, start, bd->bi_dram[i].size,
1069 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
1076 static int pci_uclass_pre_probe(struct udevice *bus)
1078 struct pci_controller *hose;
1082 debug("%s, bus=%d/%s, parent=%s\n", __func__, dev_seq(bus), bus->name,
1084 hose = dev_get_uclass_priv(bus);
1087 * Set the sequence number, if device_bind() doesn't. We want control
1088 * of this so that numbers are allocated as devices are probed. That
1089 * ensures that sub-bus numbered is correct (sub-buses must get numbers
1090 * higher than their parents)
1092 if (dev_seq(bus) == -1) {
1093 ret = uclass_get(UCLASS_PCI, &uc);
1096 bus->seq_ = uclass_find_next_free_seq(uc);
1099 /* For bridges, use the top-level PCI controller */
1100 if (!device_is_on_pci_bus(bus)) {
1102 ret = decode_regions(hose, dev_ofnode(bus->parent),
1107 struct pci_controller *parent_hose;
1109 parent_hose = dev_get_uclass_priv(bus->parent);
1110 hose->ctlr = parent_hose->bus;
1114 hose->first_busno = dev_seq(bus);
1115 hose->last_busno = dev_seq(bus);
1116 if (dev_has_ofnode(bus)) {
1117 hose->skip_auto_config_until_reloc =
1119 "u-boot,skip-auto-config-until-reloc");
1125 static int pci_uclass_post_probe(struct udevice *bus)
1127 struct pci_controller *hose = dev_get_uclass_priv(bus);
1130 debug("%s: probing bus %d\n", __func__, dev_seq(bus));
1131 ret = pci_bind_bus_devices(bus);
1133 return log_msg_ret("bind", ret);
1135 if (CONFIG_IS_ENABLED(PCI_PNP) && ll_boot_init() &&
1136 (!hose->skip_auto_config_until_reloc ||
1137 (gd->flags & GD_FLG_RELOC))) {
1138 ret = pci_auto_config_devices(bus);
1140 return log_msg_ret("cfg", ret);
1143 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
1145 * Per Intel FSP specification, we should call FSP notify API to
1146 * inform FSP that PCI enumeration has been done so that FSP will
1147 * do any necessary initialization as required by the chipset's
1148 * BIOS Writer's Guide (BWG).
1150 * Unfortunately we have to put this call here as with driver model,
1151 * the enumeration is all done on a lazy basis as needed, so until
1152 * something is touched on PCI it won't happen.
1154 * Note we only call this 1) after U-Boot is relocated, and 2)
1155 * root bus has finished probing.
1157 if ((gd->flags & GD_FLG_RELOC) && dev_seq(bus) == 0 && ll_boot_init()) {
1158 ret = fsp_init_phase_pci();
1160 return log_msg_ret("fsp", ret);
1167 static int pci_uclass_child_post_bind(struct udevice *dev)
1169 struct pci_child_plat *pplat;
1171 if (!dev_has_ofnode(dev))
1174 pplat = dev_get_parent_plat(dev);
1176 /* Extract vendor id and device id if available */
1177 ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
1179 /* Extract the devfn from fdt_pci_addr */
1180 pplat->devfn = pci_get_devfn(dev);
1185 static int pci_bridge_read_config(const struct udevice *bus, pci_dev_t bdf,
1186 uint offset, ulong *valuep,
1187 enum pci_size_t size)
1189 struct pci_controller *hose = dev_get_uclass_priv(bus);
1191 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
1194 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
1195 uint offset, ulong value,
1196 enum pci_size_t size)
1198 struct pci_controller *hose = dev_get_uclass_priv(bus);
1200 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
1203 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
1205 struct udevice *dev;
1209 * Scan through all the PCI controllers. On x86 there will only be one
1210 * but that is not necessarily true on other hardware.
1213 device_find_first_child(bus, &dev);
1218 ret = uclass_next_device(&bus);
1226 int pci_find_next_device(struct udevice **devp)
1228 struct udevice *child = *devp;
1229 struct udevice *bus = child->parent;
1232 /* First try all the siblings */
1235 device_find_next_child(&child);
1242 /* We ran out of siblings. Try the next bus */
1243 ret = uclass_next_device(&bus);
1247 return bus ? skip_to_next_device(bus, devp) : 0;
1250 int pci_find_first_device(struct udevice **devp)
1252 struct udevice *bus;
1256 ret = uclass_first_device(UCLASS_PCI, &bus);
1260 return skip_to_next_device(bus, devp);
1263 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1267 return (value >> ((offset & 3) * 8)) & 0xff;
1269 return (value >> ((offset & 2) * 8)) & 0xffff;
1275 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1276 enum pci_size_t size)
1279 uint val_mask, shift;
1294 shift = (offset & off_mask) * 8;
1295 ldata = (value & val_mask) << shift;
1296 mask = val_mask << shift;
1297 value = (old & ~mask) | ldata;
1302 int pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int index)
1304 int pci_addr_cells, addr_cells, size_cells;
1305 int cells_per_record;
1310 prop = ofnode_get_property(dev_ofnode(dev), "dma-ranges", &len);
1312 log_err("PCI: Device '%s': Cannot decode dma-ranges\n",
1317 pci_addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev));
1318 addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev->parent));
1319 size_cells = ofnode_read_simple_size_cells(dev_ofnode(dev));
1321 /* PCI addresses are always 3-cells */
1323 cells_per_record = pci_addr_cells + addr_cells + size_cells;
1324 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
1328 memp->bus_start = fdtdec_get_number(prop + 1, 2);
1329 prop += pci_addr_cells;
1330 memp->phys_start = fdtdec_get_number(prop, addr_cells);
1332 memp->size = fdtdec_get_number(prop, size_cells);
1338 len -= cells_per_record;
1344 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1345 struct pci_region **memp, struct pci_region **prefp)
1347 struct udevice *bus = pci_get_controller(dev);
1348 struct pci_controller *hose = dev_get_uclass_priv(bus);
1354 for (i = 0; i < hose->region_count; i++) {
1355 switch (hose->regions[i].flags) {
1357 if (!*iop || (*iop)->size < hose->regions[i].size)
1358 *iop = hose->regions + i;
1360 case PCI_REGION_MEM:
1361 if (!*memp || (*memp)->size < hose->regions[i].size)
1362 *memp = hose->regions + i;
1364 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1365 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1366 *prefp = hose->regions + i;
1371 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1374 u32 dm_pci_read_bar32(const struct udevice *dev, int barnum)
1379 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1380 dm_pci_read_config32(dev, bar, &addr);
1383 * If we get an invalid address, return this so that comparisons with
1384 * FDT_ADDR_T_NONE work correctly
1386 if (addr == 0xffffffff)
1388 else if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1389 return addr & PCI_BASE_ADDRESS_IO_MASK;
1391 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1394 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1398 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1399 dm_pci_write_config32(dev, bar, addr);
1402 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1403 size_t len, unsigned long mask,
1404 unsigned long flags)
1406 struct udevice *ctlr;
1407 struct pci_controller *hose;
1408 struct pci_region *res;
1412 /* The root controller has the region information */
1413 ctlr = pci_get_controller(dev);
1414 hose = dev_get_uclass_priv(ctlr);
1416 if (hose->region_count == 0)
1419 for (i = 0; i < hose->region_count; i++) {
1420 res = &hose->regions[i];
1422 if ((res->flags & mask) != flags)
1425 if (bus_addr < res->bus_start)
1428 offset = bus_addr - res->bus_start;
1429 if (offset >= res->size)
1432 if (len > res->size - offset)
1435 return res->phys_start + offset;
1438 puts("pci_hose_bus_to_phys: invalid physical address\n");
1442 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1443 size_t len, unsigned long mask,
1444 unsigned long flags)
1446 struct udevice *ctlr;
1447 struct pci_controller *hose;
1448 struct pci_region *res;
1452 /* The root controller has the region information */
1453 ctlr = pci_get_controller(dev);
1454 hose = dev_get_uclass_priv(ctlr);
1456 if (hose->region_count == 0)
1459 for (i = 0; i < hose->region_count; i++) {
1460 res = &hose->regions[i];
1462 if ((res->flags & mask) != flags)
1465 if (phys_addr < res->phys_start)
1468 offset = phys_addr - res->phys_start;
1469 if (offset >= res->size)
1472 if (len > res->size - offset)
1475 return res->bus_start + offset;
1478 puts("pci_hose_phys_to_bus: invalid physical address\n");
1482 static phys_addr_t dm_pci_map_ea_virt(struct udevice *dev, int ea_off,
1483 struct pci_child_plat *pdata)
1485 phys_addr_t addr = 0;
1488 * In the case of a Virtual Function device using BAR
1489 * base and size, add offset for VFn BAR(1, 2, 3...n)
1491 if (pdata->is_virtfn) {
1495 /* MaxOffset, 1st DW */
1496 dm_pci_read_config32(dev, ea_off + 8, &ea_entry);
1497 sz = ea_entry & PCI_EA_FIELD_MASK;
1498 /* Fill up lower 2 bits */
1499 sz |= (~PCI_EA_FIELD_MASK);
1501 if (ea_entry & PCI_EA_IS_64) {
1502 /* MaxOffset 2nd DW */
1503 dm_pci_read_config32(dev, ea_off + 16, &ea_entry);
1504 sz |= ((u64)ea_entry) << 32;
1507 addr = (pdata->virtid - 1) * (sz + 1);
1513 static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, size_t offset,
1514 size_t len, int ea_off,
1515 struct pci_child_plat *pdata)
1517 int ea_cnt, i, entry_size;
1518 int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
1522 if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
1524 * In the case of a Virtual Function device, device is
1525 * Physical function, so pdata will point to required VF
1528 if (pdata->is_virtfn)
1529 bar_id += PCI_EA_BEI_VF_BAR0;
1532 /* EA capability structure header */
1533 dm_pci_read_config32(dev, ea_off, &ea_entry);
1534 ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
1535 ea_off += PCI_EA_FIRST_ENT;
1537 for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
1539 dm_pci_read_config32(dev, ea_off, &ea_entry);
1540 entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
1542 if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
1545 /* Base address, 1st DW */
1546 dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
1547 addr = ea_entry & PCI_EA_FIELD_MASK;
1548 if (ea_entry & PCI_EA_IS_64) {
1549 /* Base address, 2nd DW, skip over 4B MaxOffset */
1550 dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
1551 addr |= ((u64)ea_entry) << 32;
1554 if (IS_ENABLED(CONFIG_PCI_SRIOV))
1555 addr += dm_pci_map_ea_virt(dev, ea_off, pdata);
1557 if (~((phys_addr_t)0) - addr < offset)
1560 /* size ignored for now */
1561 return map_physmem(addr + offset, len, MAP_NOCACHE);
1567 void *dm_pci_map_bar(struct udevice *dev, int bar, size_t offset, size_t len,
1568 unsigned long mask, unsigned long flags)
1570 struct pci_child_plat *pdata = dev_get_parent_plat(dev);
1571 struct udevice *udev = dev;
1572 pci_addr_t pci_bus_addr;
1576 if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
1578 * In case of Virtual Function devices, use PF udevice
1579 * as EA capability is defined in Physical Function
1581 if (pdata->is_virtfn)
1582 udev = pdata->pfdev;
1586 * if the function supports Enhanced Allocation use that instead of
1588 * Incase of virtual functions, pdata will help read VF BEI
1589 * and EA entry size.
1591 if (IS_ENABLED(CONFIG_PCI_ENHANCED_ALLOCATION))
1592 ea_off = dm_pci_find_capability(udev, PCI_CAP_ID_EA);
1597 return dm_pci_map_ea_bar(udev, bar, offset, len, ea_off, pdata);
1599 /* read BAR address */
1600 dm_pci_read_config32(udev, bar, &bar_response);
1601 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1603 if (~((pci_addr_t)0) - pci_bus_addr < offset)
1607 * Forward the length argument to dm_pci_bus_to_virt. The length will
1608 * be used to check that the entire address range has been declared as
1609 * a PCI range, but a better check would be to probe for the size of
1610 * the bar and prevent overflow more locally.
1612 return dm_pci_bus_to_virt(udev, pci_bus_addr + offset, len, mask, flags,
1616 static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
1618 int ttl = PCI_FIND_CAP_TTL;
1622 dm_pci_read_config8(dev, pos, &pos);
1625 if (pos < PCI_STD_HEADER_SIZEOF)
1628 dm_pci_read_config16(dev, pos, &ent);
1641 int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap)
1643 return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT,
1647 int dm_pci_find_capability(struct udevice *dev, int cap)
1653 dm_pci_read_config16(dev, PCI_STATUS, &status);
1654 if (!(status & PCI_STATUS_CAP_LIST))
1657 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
1658 if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
1659 pos = PCI_CB_CAPABILITY_LIST;
1661 pos = PCI_CAPABILITY_LIST;
1663 return _dm_pci_find_next_capability(dev, pos, cap);
1666 int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap)
1670 int pos = PCI_CFG_SPACE_SIZE;
1672 /* minimum 8 bytes per capability */
1673 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1678 dm_pci_read_config32(dev, pos, &header);
1680 * If we have no capabilities, this is indicated by cap ID,
1681 * cap version and next pointer all being 0.
1687 if (PCI_EXT_CAP_ID(header) == cap)
1690 pos = PCI_EXT_CAP_NEXT(header);
1691 if (pos < PCI_CFG_SPACE_SIZE)
1694 dm_pci_read_config32(dev, pos, &header);
1700 int dm_pci_find_ext_capability(struct udevice *dev, int cap)
1702 return dm_pci_find_next_ext_capability(dev, 0, cap);
1705 int dm_pci_flr(struct udevice *dev)
1710 /* look for PCI Express Capability */
1711 pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
1715 /* check FLR capability */
1716 dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap);
1717 if (!(cap & PCI_EXP_DEVCAP_FLR))
1720 dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0,
1721 PCI_EXP_DEVCTL_BCR_FLR);
1723 /* wait 100ms, per PCI spec */
1729 #if defined(CONFIG_PCI_SRIOV)
1730 int pci_sriov_init(struct udevice *pdev, int vf_en)
1733 struct udevice *bus;
1734 struct udevice *dev;
1744 pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1746 debug("Error: SRIOV capability not found\n");
1750 dm_pci_read_config16(pdev, pos + PCI_SRIOV_CTRL, &ctrl);
1752 dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
1753 if (vf_en > total_vf)
1755 dm_pci_write_config16(pdev, pos + PCI_SRIOV_NUM_VF, vf_en);
1757 ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
1758 dm_pci_write_config16(pdev, pos + PCI_SRIOV_CTRL, ctrl);
1760 dm_pci_read_config16(pdev, pos + PCI_SRIOV_NUM_VF, &num_vfs);
1761 if (num_vfs > vf_en)
1764 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_OFFSET, &vf_offset);
1765 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_STRIDE, &vf_stride);
1767 dm_pci_read_config16(pdev, PCI_VENDOR_ID, &vendor);
1768 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_DID, &device);
1770 bdf = dm_pci_get_bdf(pdev);
1772 pci_get_bus(PCI_BUS(bdf), &bus);
1777 bdf += PCI_BDF(0, 0, vf_offset);
1779 for (vf = 0; vf < num_vfs; vf++) {
1780 struct pci_child_plat *pplat;
1783 pci_bus_read_config(bus, bdf, PCI_CLASS_DEVICE,
1784 &class, PCI_SIZE_16);
1786 debug("%s: bus %d/%s: found VF %x:%x\n", __func__,
1787 dev_seq(bus), bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
1789 /* Find this device in the device tree */
1790 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
1792 if (ret == -ENODEV) {
1793 struct pci_device_id find_id;
1795 memset(&find_id, '\0', sizeof(find_id));
1796 find_id.vendor = vendor;
1797 find_id.device = device;
1798 find_id.class = class;
1800 ret = pci_find_and_bind_driver(bus, &find_id,
1807 /* Update the platform data */
1808 pplat = dev_get_parent_plat(dev);
1809 pplat->devfn = PCI_MASK_BUS(bdf);
1810 pplat->vendor = vendor;
1811 pplat->device = device;
1812 pplat->class = class;
1813 pplat->is_virtfn = true;
1814 pplat->pfdev = pdev;
1815 pplat->virtid = vf * vf_stride + vf_offset;
1817 debug("%s: bus %d/%s: found VF %x:%x %x:%x class %lx id %x\n",
1818 __func__, dev_seq(dev), dev->name, PCI_DEV(bdf),
1819 PCI_FUNC(bdf), vendor, device, class, pplat->virtid);
1820 bdf += PCI_BDF(0, 0, vf_stride);
1826 int pci_sriov_get_totalvfs(struct udevice *pdev)
1831 pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1833 debug("Error: SRIOV capability not found\n");
1837 dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
1843 UCLASS_DRIVER(pci) = {
1846 .flags = DM_UC_FLAG_SEQ_ALIAS | DM_UC_FLAG_NO_AUTO_SEQ,
1847 .post_bind = dm_scan_fdt_dev,
1848 .pre_probe = pci_uclass_pre_probe,
1849 .post_probe = pci_uclass_post_probe,
1850 .child_post_bind = pci_uclass_child_post_bind,
1851 .per_device_auto = sizeof(struct pci_controller),
1852 .per_child_plat_auto = sizeof(struct pci_child_plat),
1855 static const struct dm_pci_ops pci_bridge_ops = {
1856 .read_config = pci_bridge_read_config,
1857 .write_config = pci_bridge_write_config,
1860 static const struct udevice_id pci_bridge_ids[] = {
1861 { .compatible = "pci-bridge" },
1865 U_BOOT_DRIVER(pci_bridge_drv) = {
1866 .name = "pci_bridge_drv",
1868 .of_match = pci_bridge_ids,
1869 .ops = &pci_bridge_ops,
1872 UCLASS_DRIVER(pci_generic) = {
1873 .id = UCLASS_PCI_GENERIC,
1874 .name = "pci_generic",
1877 static const struct udevice_id pci_generic_ids[] = {
1878 { .compatible = "pci-generic" },
1882 U_BOOT_DRIVER(pci_generic_drv) = {
1883 .name = "pci_generic_drv",
1884 .id = UCLASS_PCI_GENERIC,
1885 .of_match = pci_generic_ids,
1890 struct udevice *bus;
1893 * Enumerate all known controller devices. Enumeration has the side-
1894 * effect of probing them, so PCIe devices will be enumerated too.
1896 for (uclass_first_device_check(UCLASS_PCI, &bus);
1898 uclass_next_device_check(&bus)) {