1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2014 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
15 #include <dm/device-internal.h>
17 #include <dm/uclass-internal.h>
18 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
19 #include <asm/fsp/fsp_support.h>
21 #include <linux/delay.h>
22 #include "pci_internal.h"
24 DECLARE_GLOBAL_DATA_PTR;
26 int pci_get_bus(int busnum, struct udevice **busp)
30 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
32 /* Since buses may not be numbered yet try a little harder with bus 0 */
34 ret = uclass_first_device_err(UCLASS_PCI, busp);
37 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
43 struct udevice *pci_get_controller(struct udevice *dev)
45 while (device_is_on_pci_bus(dev))
51 pci_dev_t dm_pci_get_bdf(const struct udevice *dev)
53 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
54 struct udevice *bus = dev->parent;
57 * This error indicates that @dev is a device on an unprobed PCI bus.
58 * The bus likely has bus=seq == -1, so the PCI_ADD_BUS() macro below
59 * will produce a bad BDF>
61 * A common cause of this problem is that this function is called in the
62 * of_to_plat() method of @dev. Accessing the PCI bus in that
63 * method is not allowed, since it has not yet been probed. To fix this,
64 * move that access to the probe() method of @dev instead.
66 if (!device_active(bus))
67 log_err("PCI: Device '%s' on unprobed bus '%s'\n", dev->name,
69 return PCI_ADD_BUS(dev_seq(bus), pplat->devfn);
73 * pci_get_bus_max() - returns the bus number of the last active bus
75 * @return last bus number, or -1 if no active buses
77 static int pci_get_bus_max(void)
83 ret = uclass_get(UCLASS_PCI, &uc);
84 uclass_foreach_dev(bus, uc) {
85 if (dev_seq(bus) > ret)
89 debug("%s: ret=%d\n", __func__, ret);
94 int pci_last_busno(void)
96 return pci_get_bus_max();
99 int pci_get_ff(enum pci_size_t size)
111 static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
114 struct fdt_pci_addr addr;
118 dev_for_each_subnode(node, bus) {
119 ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
124 if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
132 int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
133 struct udevice **devp)
137 for (device_find_first_child(bus, &dev);
139 device_find_next_child(&dev)) {
140 struct pci_child_plat *pplat;
142 pplat = dev_get_parent_plat(dev);
143 if (pplat && pplat->devfn == find_devfn) {
152 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
157 ret = pci_get_bus(PCI_BUS(bdf), &bus);
160 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
163 static int pci_device_matches_ids(struct udevice *dev,
164 struct pci_device_id *ids)
166 struct pci_child_plat *pplat;
169 pplat = dev_get_parent_plat(dev);
172 for (i = 0; ids[i].vendor != 0; i++) {
173 if (pplat->vendor == ids[i].vendor &&
174 pplat->device == ids[i].device)
181 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
182 int *indexp, struct udevice **devp)
186 /* Scan all devices on this bus */
187 for (device_find_first_child(bus, &dev);
189 device_find_next_child(&dev)) {
190 if (pci_device_matches_ids(dev, ids) >= 0) {
191 if ((*indexp)-- <= 0) {
201 int pci_find_device_id(struct pci_device_id *ids, int index,
202 struct udevice **devp)
206 /* Scan all known buses */
207 for (uclass_first_device(UCLASS_PCI, &bus);
209 uclass_next_device(&bus)) {
210 if (!pci_bus_find_devices(bus, ids, &index, devp))
218 static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
219 unsigned int device, int *indexp,
220 struct udevice **devp)
222 struct pci_child_plat *pplat;
225 for (device_find_first_child(bus, &dev);
227 device_find_next_child(&dev)) {
228 pplat = dev_get_parent_plat(dev);
229 if (pplat->vendor == vendor && pplat->device == device) {
240 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
241 struct udevice **devp)
245 /* Scan all known buses */
246 for (uclass_first_device(UCLASS_PCI, &bus);
248 uclass_next_device(&bus)) {
249 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
250 return device_probe(*devp);
257 int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
261 /* Scan all known buses */
262 for (pci_find_first_device(&dev);
264 pci_find_next_device(&dev)) {
265 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
267 if (pplat->class == find_class && !index--) {
269 return device_probe(*devp);
277 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
278 unsigned long value, enum pci_size_t size)
280 struct dm_pci_ops *ops;
282 ops = pci_get_ops(bus);
283 if (!ops->write_config)
285 return ops->write_config(bus, bdf, offset, value, size);
288 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
294 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
300 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
303 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
304 enum pci_size_t size)
309 ret = pci_get_bus(PCI_BUS(bdf), &bus);
313 return pci_bus_write_config(bus, bdf, offset, value, size);
316 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
317 enum pci_size_t size)
321 for (bus = dev; device_is_on_pci_bus(bus);)
323 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
327 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
329 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
332 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
334 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
337 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
339 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
342 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
344 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
347 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
349 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
352 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
354 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
357 int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
358 unsigned long *valuep, enum pci_size_t size)
360 struct dm_pci_ops *ops;
362 ops = pci_get_ops(bus);
363 if (!ops->read_config)
365 return ops->read_config(bus, bdf, offset, valuep, size);
368 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
369 enum pci_size_t size)
374 ret = pci_get_bus(PCI_BUS(bdf), &bus);
378 return pci_bus_read_config(bus, bdf, offset, valuep, size);
381 int dm_pci_read_config(const struct udevice *dev, int offset,
382 unsigned long *valuep, enum pci_size_t size)
384 const struct udevice *bus;
386 for (bus = dev; device_is_on_pci_bus(bus);)
388 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
392 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
397 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
405 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
410 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
418 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
423 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
431 int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep)
436 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
444 int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep)
449 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
457 int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep)
462 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
470 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
475 ret = dm_pci_read_config8(dev, offset, &val);
481 return dm_pci_write_config8(dev, offset, val);
484 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
489 ret = dm_pci_read_config16(dev, offset, &val);
495 return dm_pci_write_config16(dev, offset, val);
498 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
503 ret = dm_pci_read_config32(dev, offset, &val);
509 return dm_pci_write_config32(dev, offset, val);
512 static void set_vga_bridge_bits(struct udevice *dev)
514 struct udevice *parent = dev->parent;
517 while (dev_seq(parent) != 0) {
518 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
519 bc |= PCI_BRIDGE_CTL_VGA;
520 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
521 parent = parent->parent;
525 int pci_auto_config_devices(struct udevice *bus)
527 struct pci_controller *hose = bus->uclass_priv;
528 struct pci_child_plat *pplat;
529 unsigned int sub_bus;
533 sub_bus = dev_seq(bus);
534 debug("%s: start\n", __func__);
535 pciauto_config_init(hose);
536 for (ret = device_find_first_child(bus, &dev);
538 ret = device_find_next_child(&dev)) {
539 unsigned int max_bus;
542 debug("%s: device %s\n", __func__, dev->name);
543 if (dev_of_valid(dev) &&
544 dev_read_bool(dev, "pci,no-autoconfig"))
546 ret = dm_pciauto_config_device(dev);
548 return log_msg_ret("auto", ret);
550 sub_bus = max(sub_bus, max_bus);
552 pplat = dev_get_parent_plat(dev);
553 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
554 set_vga_bridge_bits(dev);
556 debug("%s: done\n", __func__);
558 return log_msg_ret("sub", sub_bus);
561 int pci_generic_mmap_write_config(
562 const struct udevice *bus,
563 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
568 enum pci_size_t size)
572 if (addr_f(bus, bdf, offset, &address) < 0)
577 writeb(value, address);
580 writew(value, address);
583 writel(value, address);
590 int pci_generic_mmap_read_config(
591 const struct udevice *bus,
592 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
597 enum pci_size_t size)
601 if (addr_f(bus, bdf, offset, &address) < 0) {
602 *valuep = pci_get_ff(size);
608 *valuep = readb(address);
611 *valuep = readw(address);
614 *valuep = readl(address);
621 int dm_pci_hose_probe_bus(struct udevice *bus)
628 debug("%s\n", __func__);
630 ea_pos = dm_pci_find_capability(bus, PCI_CAP_ID_EA);
632 dm_pci_read_config8(bus, ea_pos + sizeof(u32) + sizeof(u8),
636 sub_bus = pci_get_bus_max() + 1;
638 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
639 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
641 ret = device_probe(bus);
643 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
645 return log_msg_ret("probe", ret);
648 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
654 * pci_match_one_device - Tell if a PCI device structure has a matching
655 * PCI device id structure
656 * @id: single PCI device id structure to match
657 * @find: the PCI device id structure to match against
659 * Returns true if the finding pci_device_id structure matched or false if
662 static bool pci_match_one_id(const struct pci_device_id *id,
663 const struct pci_device_id *find)
665 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
666 (id->device == PCI_ANY_ID || id->device == find->device) &&
667 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
668 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
669 !((id->class ^ find->class) & id->class_mask))
676 * pci_find_and_bind_driver() - Find and bind the right PCI driver
678 * This only looks at certain fields in the descriptor.
680 * @parent: Parent bus
681 * @find_id: Specification of the driver to find
682 * @bdf: Bus/device/function addreess - see PCI_BDF()
683 * @devp: Returns a pointer to the device created
684 * @return 0 if OK, -EPERM if the device is not needed before relocation and
685 * therefore was not created, other -ve value on error
687 static int pci_find_and_bind_driver(struct udevice *parent,
688 struct pci_device_id *find_id,
689 pci_dev_t bdf, struct udevice **devp)
691 struct pci_driver_entry *start, *entry;
692 ofnode node = ofnode_null();
701 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
702 find_id->vendor, find_id->device);
704 /* Determine optional OF node */
705 if (ofnode_valid(dev_ofnode(parent)))
706 pci_dev_find_ofnode(parent, bdf, &node);
708 if (ofnode_valid(node) && !ofnode_is_available(node)) {
709 debug("%s: Ignoring disabled device\n", __func__);
710 return log_msg_ret("dis", -EPERM);
713 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
714 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
715 for (entry = start; entry != start + n_ents; entry++) {
716 const struct pci_device_id *id;
718 const struct driver *drv;
720 for (id = entry->match;
721 id->vendor || id->subvendor || id->class_mask;
723 if (!pci_match_one_id(id, find_id))
729 * In the pre-relocation phase, we only bind devices
730 * whose driver has the DM_FLAG_PRE_RELOC set, to save
731 * precious memory space as on some platforms as that
732 * space is pretty limited (ie: using Cache As RAM).
734 if (!(gd->flags & GD_FLG_RELOC) &&
735 !(drv->flags & DM_FLAG_PRE_RELOC))
736 return log_msg_ret("pre", -EPERM);
739 * We could pass the descriptor to the driver as
740 * plat (instead of NULL) and allow its bind()
741 * method to return -ENOENT if it doesn't support this
742 * device. That way we could continue the search to
743 * find another driver. For now this doesn't seem
744 * necesssary, so just bind the first match.
746 ret = device_bind(parent, drv, drv->name, NULL, node,
750 debug("%s: Match found: %s\n", __func__, drv->name);
751 dev->driver_data = id->driver_data;
757 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
759 * In the pre-relocation phase, we only bind bridge devices to save
760 * precious memory space as on some platforms as that space is pretty
761 * limited (ie: using Cache As RAM).
763 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
764 return log_msg_ret("notbr", -EPERM);
766 /* Bind a generic driver so that the device can be used */
767 sprintf(name, "pci_%x:%x.%x", dev_seq(parent), PCI_DEV(bdf),
772 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
774 ret = device_bind_driver_to_node(parent, drv, str, node, devp);
776 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
780 debug("%s: No match found: bound generic driver instead\n", __func__);
785 debug("%s: No match found: error %d\n", __func__, ret);
789 int pci_bind_bus_devices(struct udevice *bus)
791 ulong vendor, device;
799 end = PCI_BDF(dev_seq(bus), PCI_MAX_PCI_DEVICES - 1,
800 PCI_MAX_PCI_FUNCTIONS - 1);
801 for (bdf = PCI_BDF(dev_seq(bus), 0, 0); bdf <= end;
802 bdf += PCI_BDF(0, 0, 1)) {
803 struct pci_child_plat *pplat;
809 if (PCI_FUNC(bdf) && !found_multi)
812 /* Check only the first access, we don't expect problems */
813 ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
818 if (vendor == 0xffff || vendor == 0x0000)
821 pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
822 &header_type, PCI_SIZE_8);
825 found_multi = header_type & 0x80;
827 debug("%s: bus %d/%s: found device %x, function %d", __func__,
828 dev_seq(bus), bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
829 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
831 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
835 /* Find this device in the device tree */
836 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
837 debug(": find ret=%d\n", ret);
839 /* If nothing in the device tree, bind a device */
840 if (ret == -ENODEV) {
841 struct pci_device_id find_id;
844 memset(&find_id, '\0', sizeof(find_id));
845 find_id.vendor = vendor;
846 find_id.device = device;
847 find_id.class = class;
848 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
849 pci_bus_read_config(bus, bdf,
850 PCI_SUBSYSTEM_VENDOR_ID,
852 find_id.subvendor = val & 0xffff;
853 find_id.subdevice = val >> 16;
855 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
863 /* Update the platform data */
864 pplat = dev_get_parent_plat(dev);
865 pplat->devfn = PCI_MASK_BUS(bdf);
866 pplat->vendor = vendor;
867 pplat->device = device;
868 pplat->class = class;
870 if (IS_ENABLED(CONFIG_PCI_ARID)) {
871 ari_off = dm_pci_find_ext_capability(dev,
877 * Read Next Function number in ARI Cap
880 dm_pci_read_config16(dev, ari_off + 4,
883 * Update next scan on this function number,
884 * subtract 1 in BDF to satisfy loop increment.
886 if (ari_cap & 0xff00) {
887 bdf = PCI_BDF(PCI_BUS(bdf),
898 printf("Cannot read bus configuration: %d\n", ret);
903 static void decode_regions(struct pci_controller *hose, ofnode parent_node,
906 int pci_addr_cells, addr_cells, size_cells;
907 int cells_per_record;
914 prop = ofnode_get_property(node, "ranges", &len);
916 debug("%s: Cannot decode regions\n", __func__);
920 pci_addr_cells = ofnode_read_simple_addr_cells(node);
921 addr_cells = ofnode_read_simple_addr_cells(parent_node);
922 size_cells = ofnode_read_simple_size_cells(node);
924 /* PCI addresses are always 3-cells */
926 cells_per_record = pci_addr_cells + addr_cells + size_cells;
927 hose->region_count = 0;
928 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
931 /* Dynamically allocate the regions array */
932 max_regions = len / cells_per_record + CONFIG_NR_DRAM_BANKS;
933 hose->regions = (struct pci_region *)
934 calloc(1, max_regions * sizeof(struct pci_region));
936 for (i = 0; i < max_regions; i++, len -= cells_per_record) {
937 u64 pci_addr, addr, size;
943 if (len < cells_per_record)
945 flags = fdt32_to_cpu(prop[0]);
946 space_code = (flags >> 24) & 3;
947 pci_addr = fdtdec_get_number(prop + 1, 2);
948 prop += pci_addr_cells;
949 addr = fdtdec_get_number(prop, addr_cells);
951 size = fdtdec_get_number(prop, size_cells);
953 debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
954 __func__, hose->region_count, pci_addr, addr, size, space_code);
955 if (space_code & 2) {
956 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
958 } else if (space_code & 1) {
959 type = PCI_REGION_IO;
964 if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
965 type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
966 debug(" - beyond the 32-bit boundary, ignoring\n");
971 if (!IS_ENABLED(CONFIG_PCI_REGION_MULTI_ENTRY)) {
972 for (i = 0; i < hose->region_count; i++) {
973 if (hose->regions[i].flags == type)
979 pos = hose->region_count++;
980 debug(" - type=%d, pos=%d\n", type, pos);
981 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
984 /* Add a region for our local memory */
989 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
990 if (bd->bi_dram[i].size) {
991 pci_set_region(hose->regions + hose->region_count++,
992 bd->bi_dram[i].start,
993 bd->bi_dram[i].start,
995 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
1002 static int pci_uclass_pre_probe(struct udevice *bus)
1004 struct pci_controller *hose;
1008 debug("%s, bus=%d/%s, parent=%s\n", __func__, dev_seq(bus), bus->name,
1010 hose = bus->uclass_priv;
1013 * Set the sequence number, if device_bind() doesn't. We want control
1014 * of this so that numbers are allocated as devices are probed. That
1015 * ensures that sub-bus numbered is correct (sub-buses must get numbers
1016 * higher than their parents)
1018 if (dev_seq(bus) == -1) {
1019 ret = uclass_get(UCLASS_PCI, &uc);
1022 bus->sqq = uclass_find_next_free_seq(uc);
1025 /* For bridges, use the top-level PCI controller */
1026 if (!device_is_on_pci_bus(bus)) {
1028 decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
1030 struct pci_controller *parent_hose;
1032 parent_hose = dev_get_uclass_priv(bus->parent);
1033 hose->ctlr = parent_hose->bus;
1037 hose->first_busno = dev_seq(bus);
1038 hose->last_busno = dev_seq(bus);
1039 if (dev_of_valid(bus)) {
1040 hose->skip_auto_config_until_reloc =
1042 "u-boot,skip-auto-config-until-reloc");
1048 static int pci_uclass_post_probe(struct udevice *bus)
1050 struct pci_controller *hose = dev_get_uclass_priv(bus);
1053 debug("%s: probing bus %d\n", __func__, dev_seq(bus));
1054 ret = pci_bind_bus_devices(bus);
1056 return log_msg_ret("bind", ret);
1058 if (CONFIG_IS_ENABLED(PCI_PNP) && ll_boot_init() &&
1059 (!hose->skip_auto_config_until_reloc ||
1060 (gd->flags & GD_FLG_RELOC))) {
1061 ret = pci_auto_config_devices(bus);
1063 return log_msg_ret("cfg", ret);
1066 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
1068 * Per Intel FSP specification, we should call FSP notify API to
1069 * inform FSP that PCI enumeration has been done so that FSP will
1070 * do any necessary initialization as required by the chipset's
1071 * BIOS Writer's Guide (BWG).
1073 * Unfortunately we have to put this call here as with driver model,
1074 * the enumeration is all done on a lazy basis as needed, so until
1075 * something is touched on PCI it won't happen.
1077 * Note we only call this 1) after U-Boot is relocated, and 2)
1078 * root bus has finished probing.
1080 if ((gd->flags & GD_FLG_RELOC) && dev_seq(bus) == 0 && ll_boot_init()) {
1081 ret = fsp_init_phase_pci();
1083 return log_msg_ret("fsp", ret);
1090 static int pci_uclass_child_post_bind(struct udevice *dev)
1092 struct pci_child_plat *pplat;
1094 if (!dev_of_valid(dev))
1097 pplat = dev_get_parent_plat(dev);
1099 /* Extract vendor id and device id if available */
1100 ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
1102 /* Extract the devfn from fdt_pci_addr */
1103 pplat->devfn = pci_get_devfn(dev);
1108 static int pci_bridge_read_config(const struct udevice *bus, pci_dev_t bdf,
1109 uint offset, ulong *valuep,
1110 enum pci_size_t size)
1112 struct pci_controller *hose = bus->uclass_priv;
1114 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
1117 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
1118 uint offset, ulong value,
1119 enum pci_size_t size)
1121 struct pci_controller *hose = bus->uclass_priv;
1123 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
1126 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
1128 struct udevice *dev;
1132 * Scan through all the PCI controllers. On x86 there will only be one
1133 * but that is not necessarily true on other hardware.
1136 device_find_first_child(bus, &dev);
1141 ret = uclass_next_device(&bus);
1149 int pci_find_next_device(struct udevice **devp)
1151 struct udevice *child = *devp;
1152 struct udevice *bus = child->parent;
1155 /* First try all the siblings */
1158 device_find_next_child(&child);
1165 /* We ran out of siblings. Try the next bus */
1166 ret = uclass_next_device(&bus);
1170 return bus ? skip_to_next_device(bus, devp) : 0;
1173 int pci_find_first_device(struct udevice **devp)
1175 struct udevice *bus;
1179 ret = uclass_first_device(UCLASS_PCI, &bus);
1183 return skip_to_next_device(bus, devp);
1186 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1190 return (value >> ((offset & 3) * 8)) & 0xff;
1192 return (value >> ((offset & 2) * 8)) & 0xffff;
1198 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1199 enum pci_size_t size)
1202 uint val_mask, shift;
1217 shift = (offset & off_mask) * 8;
1218 ldata = (value & val_mask) << shift;
1219 mask = val_mask << shift;
1220 value = (old & ~mask) | ldata;
1225 int pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int index)
1227 int pci_addr_cells, addr_cells, size_cells;
1228 int cells_per_record;
1233 prop = ofnode_get_property(dev_ofnode(dev), "dma-ranges", &len);
1235 log_err("PCI: Device '%s': Cannot decode dma-ranges\n",
1240 pci_addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev));
1241 addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev->parent));
1242 size_cells = ofnode_read_simple_size_cells(dev_ofnode(dev));
1244 /* PCI addresses are always 3-cells */
1246 cells_per_record = pci_addr_cells + addr_cells + size_cells;
1247 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
1251 memp->bus_start = fdtdec_get_number(prop + 1, 2);
1252 prop += pci_addr_cells;
1253 memp->phys_start = fdtdec_get_number(prop, addr_cells);
1255 memp->size = fdtdec_get_number(prop, size_cells);
1261 len -= cells_per_record;
1267 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1268 struct pci_region **memp, struct pci_region **prefp)
1270 struct udevice *bus = pci_get_controller(dev);
1271 struct pci_controller *hose = dev_get_uclass_priv(bus);
1277 for (i = 0; i < hose->region_count; i++) {
1278 switch (hose->regions[i].flags) {
1280 if (!*iop || (*iop)->size < hose->regions[i].size)
1281 *iop = hose->regions + i;
1283 case PCI_REGION_MEM:
1284 if (!*memp || (*memp)->size < hose->regions[i].size)
1285 *memp = hose->regions + i;
1287 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1288 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1289 *prefp = hose->regions + i;
1294 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1297 u32 dm_pci_read_bar32(const struct udevice *dev, int barnum)
1302 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1303 dm_pci_read_config32(dev, bar, &addr);
1306 * If we get an invalid address, return this so that comparisons with
1307 * FDT_ADDR_T_NONE work correctly
1309 if (addr == 0xffffffff)
1311 else if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1312 return addr & PCI_BASE_ADDRESS_IO_MASK;
1314 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1317 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1321 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1322 dm_pci_write_config32(dev, bar, addr);
1325 static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1326 pci_addr_t bus_addr, unsigned long flags,
1327 unsigned long skip_mask, phys_addr_t *pa)
1329 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1330 struct pci_region *res;
1333 if (hose->region_count == 0) {
1338 for (i = 0; i < hose->region_count; i++) {
1339 res = &hose->regions[i];
1341 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1344 if (res->flags & skip_mask)
1347 if (bus_addr >= res->bus_start &&
1348 (bus_addr - res->bus_start) < res->size) {
1349 *pa = (bus_addr - res->bus_start + res->phys_start);
1357 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1358 unsigned long flags)
1360 phys_addr_t phys_addr = 0;
1361 struct udevice *ctlr;
1364 /* The root controller has the region information */
1365 ctlr = pci_get_controller(dev);
1368 * if PCI_REGION_MEM is set we do a two pass search with preference
1369 * on matches that don't have PCI_REGION_SYS_MEMORY set
1371 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1372 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1373 flags, PCI_REGION_SYS_MEMORY,
1379 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1382 puts("pci_hose_bus_to_phys: invalid physical address\n");
1387 int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1388 unsigned long flags, unsigned long skip_mask,
1391 struct pci_region *res;
1392 struct udevice *ctlr;
1393 pci_addr_t bus_addr;
1395 struct pci_controller *hose;
1397 /* The root controller has the region information */
1398 ctlr = pci_get_controller(dev);
1399 hose = dev_get_uclass_priv(ctlr);
1401 if (hose->region_count == 0) {
1406 for (i = 0; i < hose->region_count; i++) {
1407 res = &hose->regions[i];
1409 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1412 if (res->flags & skip_mask)
1415 bus_addr = phys_addr - res->phys_start + res->bus_start;
1417 if (bus_addr >= res->bus_start &&
1418 (bus_addr - res->bus_start) < res->size) {
1427 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1428 unsigned long flags)
1430 pci_addr_t bus_addr = 0;
1434 * if PCI_REGION_MEM is set we do a two pass search with preference
1435 * on matches that don't have PCI_REGION_SYS_MEMORY set
1437 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1438 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1439 PCI_REGION_SYS_MEMORY, &bus_addr);
1444 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1447 puts("pci_hose_phys_to_bus: invalid physical address\n");
1452 static phys_addr_t dm_pci_map_ea_virt(struct udevice *dev, int ea_off,
1453 struct pci_child_plat *pdata)
1455 phys_addr_t addr = 0;
1458 * In the case of a Virtual Function device using BAR
1459 * base and size, add offset for VFn BAR(1, 2, 3...n)
1461 if (pdata->is_virtfn) {
1465 /* MaxOffset, 1st DW */
1466 dm_pci_read_config32(dev, ea_off + 8, &ea_entry);
1467 sz = ea_entry & PCI_EA_FIELD_MASK;
1468 /* Fill up lower 2 bits */
1469 sz |= (~PCI_EA_FIELD_MASK);
1471 if (ea_entry & PCI_EA_IS_64) {
1472 /* MaxOffset 2nd DW */
1473 dm_pci_read_config32(dev, ea_off + 16, &ea_entry);
1474 sz |= ((u64)ea_entry) << 32;
1477 addr = (pdata->virtid - 1) * (sz + 1);
1483 static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
1484 int ea_off, struct pci_child_plat *pdata)
1486 int ea_cnt, i, entry_size;
1487 int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
1491 if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
1493 * In the case of a Virtual Function device, device is
1494 * Physical function, so pdata will point to required VF
1497 if (pdata->is_virtfn)
1498 bar_id += PCI_EA_BEI_VF_BAR0;
1501 /* EA capability structure header */
1502 dm_pci_read_config32(dev, ea_off, &ea_entry);
1503 ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
1504 ea_off += PCI_EA_FIRST_ENT;
1506 for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
1508 dm_pci_read_config32(dev, ea_off, &ea_entry);
1509 entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
1511 if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
1514 /* Base address, 1st DW */
1515 dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
1516 addr = ea_entry & PCI_EA_FIELD_MASK;
1517 if (ea_entry & PCI_EA_IS_64) {
1518 /* Base address, 2nd DW, skip over 4B MaxOffset */
1519 dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
1520 addr |= ((u64)ea_entry) << 32;
1523 if (IS_ENABLED(CONFIG_PCI_SRIOV))
1524 addr += dm_pci_map_ea_virt(dev, ea_off, pdata);
1526 /* size ignored for now */
1527 return map_physmem(addr, 0, flags);
1533 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1535 struct pci_child_plat *pdata = dev_get_parent_plat(dev);
1536 struct udevice *udev = dev;
1537 pci_addr_t pci_bus_addr;
1541 if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
1543 * In case of Virtual Function devices, use PF udevice
1544 * as EA capability is defined in Physical Function
1546 if (pdata->is_virtfn)
1547 udev = pdata->pfdev;
1551 * if the function supports Enhanced Allocation use that instead of
1553 * Incase of virtual functions, pdata will help read VF BEI
1554 * and EA entry size.
1556 ea_off = dm_pci_find_capability(udev, PCI_CAP_ID_EA);
1558 return dm_pci_map_ea_bar(udev, bar, flags, ea_off, pdata);
1560 /* read BAR address */
1561 dm_pci_read_config32(udev, bar, &bar_response);
1562 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1565 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1566 * isn't actually used on any platform because U-Boot assumes a static
1567 * linear mapping. In the future, this could read the BAR size
1568 * and pass that as the size if needed.
1570 return dm_pci_bus_to_virt(udev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1573 static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
1575 int ttl = PCI_FIND_CAP_TTL;
1579 dm_pci_read_config8(dev, pos, &pos);
1582 if (pos < PCI_STD_HEADER_SIZEOF)
1585 dm_pci_read_config16(dev, pos, &ent);
1598 int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap)
1600 return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT,
1604 int dm_pci_find_capability(struct udevice *dev, int cap)
1610 dm_pci_read_config16(dev, PCI_STATUS, &status);
1611 if (!(status & PCI_STATUS_CAP_LIST))
1614 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
1615 if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
1616 pos = PCI_CB_CAPABILITY_LIST;
1618 pos = PCI_CAPABILITY_LIST;
1620 return _dm_pci_find_next_capability(dev, pos, cap);
1623 int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap)
1627 int pos = PCI_CFG_SPACE_SIZE;
1629 /* minimum 8 bytes per capability */
1630 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1635 dm_pci_read_config32(dev, pos, &header);
1637 * If we have no capabilities, this is indicated by cap ID,
1638 * cap version and next pointer all being 0.
1644 if (PCI_EXT_CAP_ID(header) == cap)
1647 pos = PCI_EXT_CAP_NEXT(header);
1648 if (pos < PCI_CFG_SPACE_SIZE)
1651 dm_pci_read_config32(dev, pos, &header);
1657 int dm_pci_find_ext_capability(struct udevice *dev, int cap)
1659 return dm_pci_find_next_ext_capability(dev, 0, cap);
1662 int dm_pci_flr(struct udevice *dev)
1667 /* look for PCI Express Capability */
1668 pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
1672 /* check FLR capability */
1673 dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap);
1674 if (!(cap & PCI_EXP_DEVCAP_FLR))
1677 dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0,
1678 PCI_EXP_DEVCTL_BCR_FLR);
1680 /* wait 100ms, per PCI spec */
1686 #if defined(CONFIG_PCI_SRIOV)
1687 int pci_sriov_init(struct udevice *pdev, int vf_en)
1690 struct udevice *bus;
1691 struct udevice *dev;
1701 pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1703 debug("Error: SRIOV capability not found\n");
1707 dm_pci_read_config16(pdev, pos + PCI_SRIOV_CTRL, &ctrl);
1709 dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
1710 if (vf_en > total_vf)
1712 dm_pci_write_config16(pdev, pos + PCI_SRIOV_NUM_VF, vf_en);
1714 ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
1715 dm_pci_write_config16(pdev, pos + PCI_SRIOV_CTRL, ctrl);
1717 dm_pci_read_config16(pdev, pos + PCI_SRIOV_NUM_VF, &num_vfs);
1718 if (num_vfs > vf_en)
1721 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_OFFSET, &vf_offset);
1722 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_STRIDE, &vf_stride);
1724 dm_pci_read_config16(pdev, PCI_VENDOR_ID, &vendor);
1725 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_DID, &device);
1727 bdf = dm_pci_get_bdf(pdev);
1729 pci_get_bus(PCI_BUS(bdf), &bus);
1734 bdf += PCI_BDF(0, 0, vf_offset);
1736 for (vf = 0; vf < num_vfs; vf++) {
1737 struct pci_child_plat *pplat;
1740 pci_bus_read_config(bus, bdf, PCI_CLASS_DEVICE,
1741 &class, PCI_SIZE_16);
1743 debug("%s: bus %d/%s: found VF %x:%x\n", __func__,
1744 dev_seq(bus), bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
1746 /* Find this device in the device tree */
1747 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
1749 if (ret == -ENODEV) {
1750 struct pci_device_id find_id;
1752 memset(&find_id, '\0', sizeof(find_id));
1753 find_id.vendor = vendor;
1754 find_id.device = device;
1755 find_id.class = class;
1757 ret = pci_find_and_bind_driver(bus, &find_id,
1764 /* Update the platform data */
1765 pplat = dev_get_parent_plat(dev);
1766 pplat->devfn = PCI_MASK_BUS(bdf);
1767 pplat->vendor = vendor;
1768 pplat->device = device;
1769 pplat->class = class;
1770 pplat->is_virtfn = true;
1771 pplat->pfdev = pdev;
1772 pplat->virtid = vf * vf_stride + vf_offset;
1774 debug("%s: bus %d/%s: found VF %x:%x %x:%x class %lx id %x\n",
1775 __func__, dev_seq(dev), dev->name, PCI_DEV(bdf),
1776 PCI_FUNC(bdf), vendor, device, class, pplat->virtid);
1777 bdf += PCI_BDF(0, 0, vf_stride);
1783 int pci_sriov_get_totalvfs(struct udevice *pdev)
1788 pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1790 debug("Error: SRIOV capability not found\n");
1794 dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
1800 UCLASS_DRIVER(pci) = {
1803 .flags = DM_UC_FLAG_SEQ_ALIAS | DM_UC_FLAG_NO_AUTO_SEQ,
1804 .post_bind = dm_scan_fdt_dev,
1805 .pre_probe = pci_uclass_pre_probe,
1806 .post_probe = pci_uclass_post_probe,
1807 .child_post_bind = pci_uclass_child_post_bind,
1808 .per_device_auto = sizeof(struct pci_controller),
1809 .per_child_plat_auto = sizeof(struct pci_child_plat),
1812 static const struct dm_pci_ops pci_bridge_ops = {
1813 .read_config = pci_bridge_read_config,
1814 .write_config = pci_bridge_write_config,
1817 static const struct udevice_id pci_bridge_ids[] = {
1818 { .compatible = "pci-bridge" },
1822 U_BOOT_DRIVER(pci_bridge_drv) = {
1823 .name = "pci_bridge_drv",
1825 .of_match = pci_bridge_ids,
1826 .ops = &pci_bridge_ops,
1829 UCLASS_DRIVER(pci_generic) = {
1830 .id = UCLASS_PCI_GENERIC,
1831 .name = "pci_generic",
1834 static const struct udevice_id pci_generic_ids[] = {
1835 { .compatible = "pci-generic" },
1839 U_BOOT_DRIVER(pci_generic_drv) = {
1840 .name = "pci_generic_drv",
1841 .id = UCLASS_PCI_GENERIC,
1842 .of_match = pci_generic_ids,
1847 struct udevice *bus;
1850 * Enumerate all known controller devices. Enumeration has the side-
1851 * effect of probing them, so PCIe devices will be enumerated too.
1853 for (uclass_first_device_check(UCLASS_PCI, &bus);
1855 uclass_next_device_check(&bus)) {