1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2014 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
7 #define LOG_CATEGORY UCLASS_PCI
16 #include <asm/global_data.h>
18 #include <dm/device-internal.h>
20 #include <dm/uclass-internal.h>
21 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
22 #include <asm/fsp/fsp_support.h>
24 #include <dt-bindings/pci/pci.h>
25 #include <linux/delay.h>
26 #include "pci_internal.h"
28 DECLARE_GLOBAL_DATA_PTR;
30 int pci_get_bus(int busnum, struct udevice **busp)
34 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
36 /* Since buses may not be numbered yet try a little harder with bus 0 */
38 ret = uclass_first_device_err(UCLASS_PCI, busp);
41 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
47 struct udevice *pci_get_controller(struct udevice *dev)
49 while (device_is_on_pci_bus(dev))
55 pci_dev_t dm_pci_get_bdf(const struct udevice *dev)
57 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
58 struct udevice *bus = dev->parent;
61 * This error indicates that @dev is a device on an unprobed PCI bus.
62 * The bus likely has bus=seq == -1, so the PCI_ADD_BUS() macro below
63 * will produce a bad BDF>
65 * A common cause of this problem is that this function is called in the
66 * of_to_plat() method of @dev. Accessing the PCI bus in that
67 * method is not allowed, since it has not yet been probed. To fix this,
68 * move that access to the probe() method of @dev instead.
70 if (!device_active(bus))
71 log_err("PCI: Device '%s' on unprobed bus '%s'\n", dev->name,
73 return PCI_ADD_BUS(dev_seq(bus), pplat->devfn);
77 * pci_get_bus_max() - returns the bus number of the last active bus
79 * @return last bus number, or -1 if no active buses
81 static int pci_get_bus_max(void)
87 ret = uclass_get(UCLASS_PCI, &uc);
88 uclass_foreach_dev(bus, uc) {
89 if (dev_seq(bus) > ret)
93 debug("%s: ret=%d\n", __func__, ret);
98 int pci_last_busno(void)
100 return pci_get_bus_max();
103 int pci_get_ff(enum pci_size_t size)
115 static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
118 struct fdt_pci_addr addr;
122 dev_for_each_subnode(node, bus) {
123 ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
128 if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
136 int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
137 struct udevice **devp)
141 for (device_find_first_child(bus, &dev);
143 device_find_next_child(&dev)) {
144 struct pci_child_plat *pplat;
146 pplat = dev_get_parent_plat(dev);
147 if (pplat && pplat->devfn == find_devfn) {
156 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
161 ret = pci_get_bus(PCI_BUS(bdf), &bus);
164 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
167 static int pci_device_matches_ids(struct udevice *dev,
168 const struct pci_device_id *ids)
170 struct pci_child_plat *pplat;
173 pplat = dev_get_parent_plat(dev);
176 for (i = 0; ids[i].vendor != 0; i++) {
177 if (pplat->vendor == ids[i].vendor &&
178 pplat->device == ids[i].device)
185 int pci_bus_find_devices(struct udevice *bus, const struct pci_device_id *ids,
186 int *indexp, struct udevice **devp)
190 /* Scan all devices on this bus */
191 for (device_find_first_child(bus, &dev);
193 device_find_next_child(&dev)) {
194 if (pci_device_matches_ids(dev, ids) >= 0) {
195 if ((*indexp)-- <= 0) {
205 int pci_find_device_id(const struct pci_device_id *ids, int index,
206 struct udevice **devp)
210 /* Scan all known buses */
211 for (uclass_first_device(UCLASS_PCI, &bus);
213 uclass_next_device(&bus)) {
214 if (!pci_bus_find_devices(bus, ids, &index, devp))
222 static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
223 unsigned int device, int *indexp,
224 struct udevice **devp)
226 struct pci_child_plat *pplat;
229 for (device_find_first_child(bus, &dev);
231 device_find_next_child(&dev)) {
232 pplat = dev_get_parent_plat(dev);
233 if (pplat->vendor == vendor && pplat->device == device) {
244 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
245 struct udevice **devp)
249 /* Scan all known buses */
250 for (uclass_first_device(UCLASS_PCI, &bus);
252 uclass_next_device(&bus)) {
253 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
254 return device_probe(*devp);
261 int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
265 /* Scan all known buses */
266 for (pci_find_first_device(&dev);
268 pci_find_next_device(&dev)) {
269 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
271 if (pplat->class == find_class && !index--) {
273 return device_probe(*devp);
281 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
282 unsigned long value, enum pci_size_t size)
284 struct dm_pci_ops *ops;
286 ops = pci_get_ops(bus);
287 if (!ops->write_config)
289 return ops->write_config(bus, bdf, offset, value, size);
292 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
298 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
304 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
307 static int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
308 enum pci_size_t size)
313 ret = pci_get_bus(PCI_BUS(bdf), &bus);
317 return pci_bus_write_config(bus, bdf, offset, value, size);
320 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
321 enum pci_size_t size)
325 for (bus = dev; device_is_on_pci_bus(bus);)
327 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
331 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
333 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
336 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
338 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
341 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
343 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
346 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
348 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
351 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
353 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
356 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
358 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
361 int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
362 unsigned long *valuep, enum pci_size_t size)
364 struct dm_pci_ops *ops;
366 ops = pci_get_ops(bus);
367 if (!ops->read_config)
369 return ops->read_config(bus, bdf, offset, valuep, size);
372 static int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
373 enum pci_size_t size)
378 ret = pci_get_bus(PCI_BUS(bdf), &bus);
382 return pci_bus_read_config(bus, bdf, offset, valuep, size);
385 int dm_pci_read_config(const struct udevice *dev, int offset,
386 unsigned long *valuep, enum pci_size_t size)
388 const struct udevice *bus;
390 for (bus = dev; device_is_on_pci_bus(bus);)
392 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
396 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
401 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
409 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
414 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
422 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
427 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
435 int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep)
440 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
448 int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep)
453 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
461 int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep)
466 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
474 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
479 ret = dm_pci_read_config8(dev, offset, &val);
485 return dm_pci_write_config8(dev, offset, val);
488 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
493 ret = dm_pci_read_config16(dev, offset, &val);
499 return dm_pci_write_config16(dev, offset, val);
502 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
507 ret = dm_pci_read_config32(dev, offset, &val);
513 return dm_pci_write_config32(dev, offset, val);
516 static void set_vga_bridge_bits(struct udevice *dev)
518 struct udevice *parent = dev->parent;
521 while (dev_seq(parent) != 0) {
522 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
523 bc |= PCI_BRIDGE_CTL_VGA;
524 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
525 parent = parent->parent;
529 int pci_auto_config_devices(struct udevice *bus)
531 struct pci_controller *hose = dev_get_uclass_priv(bus);
532 struct pci_child_plat *pplat;
533 unsigned int sub_bus;
537 sub_bus = dev_seq(bus);
538 debug("%s: start\n", __func__);
539 pciauto_config_init(hose);
540 for (ret = device_find_first_child(bus, &dev);
542 ret = device_find_next_child(&dev)) {
543 unsigned int max_bus;
546 debug("%s: device %s\n", __func__, dev->name);
547 if (dev_has_ofnode(dev) &&
548 dev_read_bool(dev, "pci,no-autoconfig"))
550 ret = dm_pciauto_config_device(dev);
552 return log_msg_ret("auto", ret);
554 sub_bus = max(sub_bus, max_bus);
556 if (dev_get_parent(dev) == bus)
559 pplat = dev_get_parent_plat(dev);
560 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
561 set_vga_bridge_bits(dev);
563 debug("%s: done\n", __func__);
565 return log_msg_ret("sub", sub_bus);
568 int pci_generic_mmap_write_config(
569 const struct udevice *bus,
570 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
575 enum pci_size_t size)
579 if (addr_f(bus, bdf, offset, &address) < 0)
584 writeb(value, address);
587 writew(value, address);
590 writel(value, address);
597 int pci_generic_mmap_read_config(
598 const struct udevice *bus,
599 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
604 enum pci_size_t size)
608 if (addr_f(bus, bdf, offset, &address) < 0) {
609 *valuep = pci_get_ff(size);
615 *valuep = readb(address);
618 *valuep = readw(address);
621 *valuep = readl(address);
628 int dm_pci_hose_probe_bus(struct udevice *bus)
636 debug("%s\n", __func__);
638 dm_pci_read_config8(bus, PCI_HEADER_TYPE, &header_type);
640 if (header_type != PCI_HEADER_TYPE_BRIDGE) {
641 debug("%s: Skipping PCI device %d with Non-Bridge Header Type 0x%x\n",
642 __func__, PCI_DEV(dm_pci_get_bdf(bus)), header_type);
643 return log_msg_ret("probe", -EINVAL);
646 ea_pos = dm_pci_find_capability(bus, PCI_CAP_ID_EA);
648 dm_pci_read_config8(bus, ea_pos + sizeof(u32) + sizeof(u8),
652 sub_bus = pci_get_bus_max() + 1;
654 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
655 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
657 ret = device_probe(bus);
659 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
661 return log_msg_ret("probe", ret);
665 sub_bus = pci_get_bus_max();
667 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
673 * pci_match_one_device - Tell if a PCI device structure has a matching
674 * PCI device id structure
675 * @id: single PCI device id structure to match
676 * @find: the PCI device id structure to match against
678 * Returns true if the finding pci_device_id structure matched or false if
681 static bool pci_match_one_id(const struct pci_device_id *id,
682 const struct pci_device_id *find)
684 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
685 (id->device == PCI_ANY_ID || id->device == find->device) &&
686 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
687 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
688 !((id->class ^ find->class) & id->class_mask))
695 * pci_need_device_pre_reloc() - Check if a device should be bound
697 * This checks a list of vendor/device-ID values indicating devices that should
698 * be bound before relocation.
701 * @vendor: Vendor ID to check
702 * @device: Device ID to check
703 * @return true if the vendor/device is in the list, false if not
705 static bool pci_need_device_pre_reloc(struct udevice *bus, uint vendor,
712 !dev_read_u32_index(bus, "u-boot,pci-pre-reloc", index,
715 if (vendev == PCI_VENDEV(vendor, device))
723 * pci_find_and_bind_driver() - Find and bind the right PCI driver
725 * This only looks at certain fields in the descriptor.
727 * @parent: Parent bus
728 * @find_id: Specification of the driver to find
729 * @bdf: Bus/device/function addreess - see PCI_BDF()
730 * @devp: Returns a pointer to the device created
731 * @return 0 if OK, -EPERM if the device is not needed before relocation and
732 * therefore was not created, other -ve value on error
734 static int pci_find_and_bind_driver(struct udevice *parent,
735 struct pci_device_id *find_id,
736 pci_dev_t bdf, struct udevice **devp)
738 struct pci_driver_entry *start, *entry;
739 ofnode node = ofnode_null();
748 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
749 find_id->vendor, find_id->device);
751 /* Determine optional OF node */
752 if (ofnode_valid(dev_ofnode(parent)))
753 pci_dev_find_ofnode(parent, bdf, &node);
755 if (ofnode_valid(node) && !ofnode_is_available(node)) {
756 debug("%s: Ignoring disabled device\n", __func__);
757 return log_msg_ret("dis", -EPERM);
760 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
761 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
762 for (entry = start; entry != start + n_ents; entry++) {
763 const struct pci_device_id *id;
765 const struct driver *drv;
767 for (id = entry->match;
768 id->vendor || id->subvendor || id->class_mask;
770 if (!pci_match_one_id(id, find_id))
776 * In the pre-relocation phase, we only bind devices
777 * whose driver has the DM_FLAG_PRE_RELOC set, to save
778 * precious memory space as on some platforms as that
779 * space is pretty limited (ie: using Cache As RAM).
781 if (!(gd->flags & GD_FLG_RELOC) &&
782 !(drv->flags & DM_FLAG_PRE_RELOC))
783 return log_msg_ret("pre", -EPERM);
786 * We could pass the descriptor to the driver as
787 * plat (instead of NULL) and allow its bind()
788 * method to return -ENOENT if it doesn't support this
789 * device. That way we could continue the search to
790 * find another driver. For now this doesn't seem
791 * necesssary, so just bind the first match.
793 ret = device_bind(parent, drv, drv->name, NULL, node,
797 debug("%s: Match found: %s\n", __func__, drv->name);
798 dev->driver_data = id->driver_data;
804 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
806 * In the pre-relocation phase, we only bind bridge devices to save
807 * precious memory space as on some platforms as that space is pretty
808 * limited (ie: using Cache As RAM).
810 if (!(gd->flags & GD_FLG_RELOC) && !bridge &&
811 !pci_need_device_pre_reloc(parent, find_id->vendor,
813 return log_msg_ret("notbr", -EPERM);
815 /* Bind a generic driver so that the device can be used */
816 sprintf(name, "pci_%x:%x.%x", dev_seq(parent), PCI_DEV(bdf),
821 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
823 ret = device_bind_driver_to_node(parent, drv, str, node, devp);
825 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
829 debug("%s: No match found: bound generic driver instead\n", __func__);
834 debug("%s: No match found: error %d\n", __func__, ret);
838 __weak extern void board_pci_fixup_dev(struct udevice *bus, struct udevice *dev)
842 int pci_bind_bus_devices(struct udevice *bus)
844 ulong vendor, device;
852 end = PCI_BDF(dev_seq(bus), PCI_MAX_PCI_DEVICES - 1,
853 PCI_MAX_PCI_FUNCTIONS - 1);
854 for (bdf = PCI_BDF(dev_seq(bus), 0, 0); bdf <= end;
855 bdf += PCI_BDF(0, 0, 1)) {
856 struct pci_child_plat *pplat;
862 if (PCI_FUNC(bdf) && !found_multi)
865 /* Check only the first access, we don't expect problems */
866 ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
868 if (ret || vendor == 0xffff || vendor == 0x0000)
871 pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
872 &header_type, PCI_SIZE_8);
875 found_multi = header_type & 0x80;
877 debug("%s: bus %d/%s: found device %x, function %d", __func__,
878 dev_seq(bus), bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
879 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
881 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
885 /* Find this device in the device tree */
886 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
887 debug(": find ret=%d\n", ret);
889 /* If nothing in the device tree, bind a device */
890 if (ret == -ENODEV) {
891 struct pci_device_id find_id;
894 memset(&find_id, '\0', sizeof(find_id));
895 find_id.vendor = vendor;
896 find_id.device = device;
897 find_id.class = class;
898 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
899 pci_bus_read_config(bus, bdf,
900 PCI_SUBSYSTEM_VENDOR_ID,
902 find_id.subvendor = val & 0xffff;
903 find_id.subdevice = val >> 16;
905 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
913 /* Update the platform data */
914 pplat = dev_get_parent_plat(dev);
915 pplat->devfn = PCI_MASK_BUS(bdf);
916 pplat->vendor = vendor;
917 pplat->device = device;
918 pplat->class = class;
920 if (IS_ENABLED(CONFIG_PCI_ARID)) {
921 ari_off = dm_pci_find_ext_capability(dev,
927 * Read Next Function number in ARI Cap
930 dm_pci_read_config16(dev, ari_off + 4,
933 * Update next scan on this function number,
934 * subtract 1 in BDF to satisfy loop increment.
936 if (ari_cap & 0xff00) {
937 bdf = PCI_BDF(PCI_BUS(bdf),
945 board_pci_fixup_dev(bus, dev);
951 static void decode_regions(struct pci_controller *hose, ofnode parent_node,
954 int pci_addr_cells, addr_cells, size_cells;
955 int cells_per_record;
962 prop = ofnode_get_property(node, "ranges", &len);
964 debug("%s: Cannot decode regions\n", __func__);
968 pci_addr_cells = ofnode_read_simple_addr_cells(node);
969 addr_cells = ofnode_read_simple_addr_cells(parent_node);
970 size_cells = ofnode_read_simple_size_cells(node);
972 /* PCI addresses are always 3-cells */
974 cells_per_record = pci_addr_cells + addr_cells + size_cells;
975 hose->region_count = 0;
976 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
979 /* Dynamically allocate the regions array */
980 max_regions = len / cells_per_record + CONFIG_NR_DRAM_BANKS;
981 hose->regions = (struct pci_region *)
982 calloc(1, max_regions * sizeof(struct pci_region));
984 for (i = 0; i < max_regions; i++, len -= cells_per_record) {
985 u64 pci_addr, addr, size;
991 if (len < cells_per_record)
993 flags = fdt32_to_cpu(prop[0]);
994 space_code = (flags >> 24) & 3;
995 pci_addr = fdtdec_get_number(prop + 1, 2);
996 prop += pci_addr_cells;
997 addr = fdtdec_get_number(prop, addr_cells);
999 size = fdtdec_get_number(prop, size_cells);
1001 debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
1002 __func__, hose->region_count, pci_addr, addr, size, space_code);
1003 if (space_code & 2) {
1004 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
1006 } else if (space_code & 1) {
1007 type = PCI_REGION_IO;
1012 if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
1013 type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
1014 debug(" - beyond the 32-bit boundary, ignoring\n");
1019 if (!IS_ENABLED(CONFIG_PCI_REGION_MULTI_ENTRY)) {
1020 for (i = 0; i < hose->region_count; i++) {
1021 if (hose->regions[i].flags == type)
1027 pos = hose->region_count++;
1028 debug(" - type=%d, pos=%d\n", type, pos);
1029 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
1032 /* Add a region for our local memory */
1037 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
1038 if (bd->bi_dram[i].size) {
1039 phys_addr_t start = bd->bi_dram[i].start;
1041 if (IS_ENABLED(CONFIG_PCI_MAP_SYSTEM_MEMORY))
1042 start = virt_to_phys((void *)(uintptr_t)bd->bi_dram[i].start);
1044 pci_set_region(hose->regions + hose->region_count++,
1045 start, start, bd->bi_dram[i].size,
1046 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
1053 static int pci_uclass_pre_probe(struct udevice *bus)
1055 struct pci_controller *hose;
1059 debug("%s, bus=%d/%s, parent=%s\n", __func__, dev_seq(bus), bus->name,
1061 hose = dev_get_uclass_priv(bus);
1064 * Set the sequence number, if device_bind() doesn't. We want control
1065 * of this so that numbers are allocated as devices are probed. That
1066 * ensures that sub-bus numbered is correct (sub-buses must get numbers
1067 * higher than their parents)
1069 if (dev_seq(bus) == -1) {
1070 ret = uclass_get(UCLASS_PCI, &uc);
1073 bus->seq_ = uclass_find_next_free_seq(uc);
1076 /* For bridges, use the top-level PCI controller */
1077 if (!device_is_on_pci_bus(bus)) {
1079 decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
1081 struct pci_controller *parent_hose;
1083 parent_hose = dev_get_uclass_priv(bus->parent);
1084 hose->ctlr = parent_hose->bus;
1088 hose->first_busno = dev_seq(bus);
1089 hose->last_busno = dev_seq(bus);
1090 if (dev_has_ofnode(bus)) {
1091 hose->skip_auto_config_until_reloc =
1093 "u-boot,skip-auto-config-until-reloc");
1099 static int pci_uclass_post_probe(struct udevice *bus)
1101 struct pci_controller *hose = dev_get_uclass_priv(bus);
1104 debug("%s: probing bus %d\n", __func__, dev_seq(bus));
1105 ret = pci_bind_bus_devices(bus);
1107 return log_msg_ret("bind", ret);
1109 if (CONFIG_IS_ENABLED(PCI_PNP) && ll_boot_init() &&
1110 (!hose->skip_auto_config_until_reloc ||
1111 (gd->flags & GD_FLG_RELOC))) {
1112 ret = pci_auto_config_devices(bus);
1114 return log_msg_ret("cfg", ret);
1117 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
1119 * Per Intel FSP specification, we should call FSP notify API to
1120 * inform FSP that PCI enumeration has been done so that FSP will
1121 * do any necessary initialization as required by the chipset's
1122 * BIOS Writer's Guide (BWG).
1124 * Unfortunately we have to put this call here as with driver model,
1125 * the enumeration is all done on a lazy basis as needed, so until
1126 * something is touched on PCI it won't happen.
1128 * Note we only call this 1) after U-Boot is relocated, and 2)
1129 * root bus has finished probing.
1131 if ((gd->flags & GD_FLG_RELOC) && dev_seq(bus) == 0 && ll_boot_init()) {
1132 ret = fsp_init_phase_pci();
1134 return log_msg_ret("fsp", ret);
1141 static int pci_uclass_child_post_bind(struct udevice *dev)
1143 struct pci_child_plat *pplat;
1145 if (!dev_has_ofnode(dev))
1148 pplat = dev_get_parent_plat(dev);
1150 /* Extract vendor id and device id if available */
1151 ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
1153 /* Extract the devfn from fdt_pci_addr */
1154 pplat->devfn = pci_get_devfn(dev);
1159 static int pci_bridge_read_config(const struct udevice *bus, pci_dev_t bdf,
1160 uint offset, ulong *valuep,
1161 enum pci_size_t size)
1163 struct pci_controller *hose = dev_get_uclass_priv(bus);
1165 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
1168 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
1169 uint offset, ulong value,
1170 enum pci_size_t size)
1172 struct pci_controller *hose = dev_get_uclass_priv(bus);
1174 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
1177 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
1179 struct udevice *dev;
1183 * Scan through all the PCI controllers. On x86 there will only be one
1184 * but that is not necessarily true on other hardware.
1187 device_find_first_child(bus, &dev);
1192 ret = uclass_next_device(&bus);
1200 int pci_find_next_device(struct udevice **devp)
1202 struct udevice *child = *devp;
1203 struct udevice *bus = child->parent;
1206 /* First try all the siblings */
1209 device_find_next_child(&child);
1216 /* We ran out of siblings. Try the next bus */
1217 ret = uclass_next_device(&bus);
1221 return bus ? skip_to_next_device(bus, devp) : 0;
1224 int pci_find_first_device(struct udevice **devp)
1226 struct udevice *bus;
1230 ret = uclass_first_device(UCLASS_PCI, &bus);
1234 return skip_to_next_device(bus, devp);
1237 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1241 return (value >> ((offset & 3) * 8)) & 0xff;
1243 return (value >> ((offset & 2) * 8)) & 0xffff;
1249 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1250 enum pci_size_t size)
1253 uint val_mask, shift;
1268 shift = (offset & off_mask) * 8;
1269 ldata = (value & val_mask) << shift;
1270 mask = val_mask << shift;
1271 value = (old & ~mask) | ldata;
1276 int pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int index)
1278 int pci_addr_cells, addr_cells, size_cells;
1279 int cells_per_record;
1284 prop = ofnode_get_property(dev_ofnode(dev), "dma-ranges", &len);
1286 log_err("PCI: Device '%s': Cannot decode dma-ranges\n",
1291 pci_addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev));
1292 addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev->parent));
1293 size_cells = ofnode_read_simple_size_cells(dev_ofnode(dev));
1295 /* PCI addresses are always 3-cells */
1297 cells_per_record = pci_addr_cells + addr_cells + size_cells;
1298 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
1302 memp->bus_start = fdtdec_get_number(prop + 1, 2);
1303 prop += pci_addr_cells;
1304 memp->phys_start = fdtdec_get_number(prop, addr_cells);
1306 memp->size = fdtdec_get_number(prop, size_cells);
1312 len -= cells_per_record;
1318 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1319 struct pci_region **memp, struct pci_region **prefp)
1321 struct udevice *bus = pci_get_controller(dev);
1322 struct pci_controller *hose = dev_get_uclass_priv(bus);
1328 for (i = 0; i < hose->region_count; i++) {
1329 switch (hose->regions[i].flags) {
1331 if (!*iop || (*iop)->size < hose->regions[i].size)
1332 *iop = hose->regions + i;
1334 case PCI_REGION_MEM:
1335 if (!*memp || (*memp)->size < hose->regions[i].size)
1336 *memp = hose->regions + i;
1338 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1339 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1340 *prefp = hose->regions + i;
1345 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1348 u32 dm_pci_read_bar32(const struct udevice *dev, int barnum)
1353 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1354 dm_pci_read_config32(dev, bar, &addr);
1357 * If we get an invalid address, return this so that comparisons with
1358 * FDT_ADDR_T_NONE work correctly
1360 if (addr == 0xffffffff)
1362 else if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1363 return addr & PCI_BASE_ADDRESS_IO_MASK;
1365 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1368 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1372 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1373 dm_pci_write_config32(dev, bar, addr);
1376 static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1377 pci_addr_t bus_addr, unsigned long flags,
1378 unsigned long skip_mask, phys_addr_t *pa)
1380 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1381 struct pci_region *res;
1384 if (hose->region_count == 0) {
1389 for (i = 0; i < hose->region_count; i++) {
1390 res = &hose->regions[i];
1392 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1395 if (res->flags & skip_mask)
1398 if (bus_addr >= res->bus_start &&
1399 (bus_addr - res->bus_start) < res->size) {
1400 *pa = (bus_addr - res->bus_start + res->phys_start);
1408 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1409 unsigned long flags)
1411 phys_addr_t phys_addr = 0;
1412 struct udevice *ctlr;
1415 /* The root controller has the region information */
1416 ctlr = pci_get_controller(dev);
1419 * if PCI_REGION_MEM is set we do a two pass search with preference
1420 * on matches that don't have PCI_REGION_SYS_MEMORY set
1422 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1423 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1424 flags, PCI_REGION_SYS_MEMORY,
1430 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1433 puts("pci_hose_bus_to_phys: invalid physical address\n");
1438 static int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1439 unsigned long flags, unsigned long skip_mask,
1442 struct pci_region *res;
1443 struct udevice *ctlr;
1444 pci_addr_t bus_addr;
1446 struct pci_controller *hose;
1448 /* The root controller has the region information */
1449 ctlr = pci_get_controller(dev);
1450 hose = dev_get_uclass_priv(ctlr);
1452 if (hose->region_count == 0) {
1457 for (i = 0; i < hose->region_count; i++) {
1458 res = &hose->regions[i];
1460 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1463 if (res->flags & skip_mask)
1466 bus_addr = phys_addr - res->phys_start + res->bus_start;
1468 if (bus_addr >= res->bus_start &&
1469 (bus_addr - res->bus_start) < res->size) {
1478 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1479 unsigned long flags)
1481 pci_addr_t bus_addr = 0;
1485 * if PCI_REGION_MEM is set we do a two pass search with preference
1486 * on matches that don't have PCI_REGION_SYS_MEMORY set
1488 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1489 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1490 PCI_REGION_SYS_MEMORY, &bus_addr);
1495 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1498 puts("pci_hose_phys_to_bus: invalid physical address\n");
1503 static phys_addr_t dm_pci_map_ea_virt(struct udevice *dev, int ea_off,
1504 struct pci_child_plat *pdata)
1506 phys_addr_t addr = 0;
1509 * In the case of a Virtual Function device using BAR
1510 * base and size, add offset for VFn BAR(1, 2, 3...n)
1512 if (pdata->is_virtfn) {
1516 /* MaxOffset, 1st DW */
1517 dm_pci_read_config32(dev, ea_off + 8, &ea_entry);
1518 sz = ea_entry & PCI_EA_FIELD_MASK;
1519 /* Fill up lower 2 bits */
1520 sz |= (~PCI_EA_FIELD_MASK);
1522 if (ea_entry & PCI_EA_IS_64) {
1523 /* MaxOffset 2nd DW */
1524 dm_pci_read_config32(dev, ea_off + 16, &ea_entry);
1525 sz |= ((u64)ea_entry) << 32;
1528 addr = (pdata->virtid - 1) * (sz + 1);
1534 static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
1535 int ea_off, struct pci_child_plat *pdata)
1537 int ea_cnt, i, entry_size;
1538 int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
1542 if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
1544 * In the case of a Virtual Function device, device is
1545 * Physical function, so pdata will point to required VF
1548 if (pdata->is_virtfn)
1549 bar_id += PCI_EA_BEI_VF_BAR0;
1552 /* EA capability structure header */
1553 dm_pci_read_config32(dev, ea_off, &ea_entry);
1554 ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
1555 ea_off += PCI_EA_FIRST_ENT;
1557 for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
1559 dm_pci_read_config32(dev, ea_off, &ea_entry);
1560 entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
1562 if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
1565 /* Base address, 1st DW */
1566 dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
1567 addr = ea_entry & PCI_EA_FIELD_MASK;
1568 if (ea_entry & PCI_EA_IS_64) {
1569 /* Base address, 2nd DW, skip over 4B MaxOffset */
1570 dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
1571 addr |= ((u64)ea_entry) << 32;
1574 if (IS_ENABLED(CONFIG_PCI_SRIOV))
1575 addr += dm_pci_map_ea_virt(dev, ea_off, pdata);
1577 /* size ignored for now */
1578 return map_physmem(addr, 0, flags);
1584 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1586 struct pci_child_plat *pdata = dev_get_parent_plat(dev);
1587 struct udevice *udev = dev;
1588 pci_addr_t pci_bus_addr;
1592 if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
1594 * In case of Virtual Function devices, use PF udevice
1595 * as EA capability is defined in Physical Function
1597 if (pdata->is_virtfn)
1598 udev = pdata->pfdev;
1602 * if the function supports Enhanced Allocation use that instead of
1604 * Incase of virtual functions, pdata will help read VF BEI
1605 * and EA entry size.
1607 ea_off = dm_pci_find_capability(udev, PCI_CAP_ID_EA);
1609 return dm_pci_map_ea_bar(udev, bar, flags, ea_off, pdata);
1611 /* read BAR address */
1612 dm_pci_read_config32(udev, bar, &bar_response);
1613 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1616 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1617 * isn't actually used on any platform because U-Boot assumes a static
1618 * linear mapping. In the future, this could read the BAR size
1619 * and pass that as the size if needed.
1621 return dm_pci_bus_to_virt(udev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1624 static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
1626 int ttl = PCI_FIND_CAP_TTL;
1630 dm_pci_read_config8(dev, pos, &pos);
1633 if (pos < PCI_STD_HEADER_SIZEOF)
1636 dm_pci_read_config16(dev, pos, &ent);
1649 int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap)
1651 return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT,
1655 int dm_pci_find_capability(struct udevice *dev, int cap)
1661 dm_pci_read_config16(dev, PCI_STATUS, &status);
1662 if (!(status & PCI_STATUS_CAP_LIST))
1665 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
1666 if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
1667 pos = PCI_CB_CAPABILITY_LIST;
1669 pos = PCI_CAPABILITY_LIST;
1671 return _dm_pci_find_next_capability(dev, pos, cap);
1674 int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap)
1678 int pos = PCI_CFG_SPACE_SIZE;
1680 /* minimum 8 bytes per capability */
1681 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1686 dm_pci_read_config32(dev, pos, &header);
1688 * If we have no capabilities, this is indicated by cap ID,
1689 * cap version and next pointer all being 0.
1695 if (PCI_EXT_CAP_ID(header) == cap)
1698 pos = PCI_EXT_CAP_NEXT(header);
1699 if (pos < PCI_CFG_SPACE_SIZE)
1702 dm_pci_read_config32(dev, pos, &header);
1708 int dm_pci_find_ext_capability(struct udevice *dev, int cap)
1710 return dm_pci_find_next_ext_capability(dev, 0, cap);
1713 int dm_pci_flr(struct udevice *dev)
1718 /* look for PCI Express Capability */
1719 pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
1723 /* check FLR capability */
1724 dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap);
1725 if (!(cap & PCI_EXP_DEVCAP_FLR))
1728 dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0,
1729 PCI_EXP_DEVCTL_BCR_FLR);
1731 /* wait 100ms, per PCI spec */
1737 #if defined(CONFIG_PCI_SRIOV)
1738 int pci_sriov_init(struct udevice *pdev, int vf_en)
1741 struct udevice *bus;
1742 struct udevice *dev;
1752 pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1754 debug("Error: SRIOV capability not found\n");
1758 dm_pci_read_config16(pdev, pos + PCI_SRIOV_CTRL, &ctrl);
1760 dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
1761 if (vf_en > total_vf)
1763 dm_pci_write_config16(pdev, pos + PCI_SRIOV_NUM_VF, vf_en);
1765 ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
1766 dm_pci_write_config16(pdev, pos + PCI_SRIOV_CTRL, ctrl);
1768 dm_pci_read_config16(pdev, pos + PCI_SRIOV_NUM_VF, &num_vfs);
1769 if (num_vfs > vf_en)
1772 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_OFFSET, &vf_offset);
1773 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_STRIDE, &vf_stride);
1775 dm_pci_read_config16(pdev, PCI_VENDOR_ID, &vendor);
1776 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_DID, &device);
1778 bdf = dm_pci_get_bdf(pdev);
1780 pci_get_bus(PCI_BUS(bdf), &bus);
1785 bdf += PCI_BDF(0, 0, vf_offset);
1787 for (vf = 0; vf < num_vfs; vf++) {
1788 struct pci_child_plat *pplat;
1791 pci_bus_read_config(bus, bdf, PCI_CLASS_DEVICE,
1792 &class, PCI_SIZE_16);
1794 debug("%s: bus %d/%s: found VF %x:%x\n", __func__,
1795 dev_seq(bus), bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
1797 /* Find this device in the device tree */
1798 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
1800 if (ret == -ENODEV) {
1801 struct pci_device_id find_id;
1803 memset(&find_id, '\0', sizeof(find_id));
1804 find_id.vendor = vendor;
1805 find_id.device = device;
1806 find_id.class = class;
1808 ret = pci_find_and_bind_driver(bus, &find_id,
1815 /* Update the platform data */
1816 pplat = dev_get_parent_plat(dev);
1817 pplat->devfn = PCI_MASK_BUS(bdf);
1818 pplat->vendor = vendor;
1819 pplat->device = device;
1820 pplat->class = class;
1821 pplat->is_virtfn = true;
1822 pplat->pfdev = pdev;
1823 pplat->virtid = vf * vf_stride + vf_offset;
1825 debug("%s: bus %d/%s: found VF %x:%x %x:%x class %lx id %x\n",
1826 __func__, dev_seq(dev), dev->name, PCI_DEV(bdf),
1827 PCI_FUNC(bdf), vendor, device, class, pplat->virtid);
1828 bdf += PCI_BDF(0, 0, vf_stride);
1834 int pci_sriov_get_totalvfs(struct udevice *pdev)
1839 pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1841 debug("Error: SRIOV capability not found\n");
1845 dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
1851 UCLASS_DRIVER(pci) = {
1854 .flags = DM_UC_FLAG_SEQ_ALIAS | DM_UC_FLAG_NO_AUTO_SEQ,
1855 .post_bind = dm_scan_fdt_dev,
1856 .pre_probe = pci_uclass_pre_probe,
1857 .post_probe = pci_uclass_post_probe,
1858 .child_post_bind = pci_uclass_child_post_bind,
1859 .per_device_auto = sizeof(struct pci_controller),
1860 .per_child_plat_auto = sizeof(struct pci_child_plat),
1863 static const struct dm_pci_ops pci_bridge_ops = {
1864 .read_config = pci_bridge_read_config,
1865 .write_config = pci_bridge_write_config,
1868 static const struct udevice_id pci_bridge_ids[] = {
1869 { .compatible = "pci-bridge" },
1873 U_BOOT_DRIVER(pci_bridge_drv) = {
1874 .name = "pci_bridge_drv",
1876 .of_match = pci_bridge_ids,
1877 .ops = &pci_bridge_ops,
1880 UCLASS_DRIVER(pci_generic) = {
1881 .id = UCLASS_PCI_GENERIC,
1882 .name = "pci_generic",
1885 static const struct udevice_id pci_generic_ids[] = {
1886 { .compatible = "pci-generic" },
1890 U_BOOT_DRIVER(pci_generic_drv) = {
1891 .name = "pci_generic_drv",
1892 .id = UCLASS_PCI_GENERIC,
1893 .of_match = pci_generic_ids,
1898 struct udevice *bus;
1901 * Enumerate all known controller devices. Enumeration has the side-
1902 * effect of probing them, so PCIe devices will be enumerated too.
1904 for (uclass_first_device_check(UCLASS_PCI, &bus);
1906 uclass_next_device_check(&bus)) {