1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2014 Google, Inc
4 * Written by Simon Glass <sjg@chromium.org>
14 #include <asm/global_data.h>
16 #include <dm/device-internal.h>
18 #include <dm/uclass-internal.h>
19 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
20 #include <asm/fsp/fsp_support.h>
22 #include <linux/delay.h>
23 #include "pci_internal.h"
25 DECLARE_GLOBAL_DATA_PTR;
27 int pci_get_bus(int busnum, struct udevice **busp)
31 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
33 /* Since buses may not be numbered yet try a little harder with bus 0 */
35 ret = uclass_first_device_err(UCLASS_PCI, busp);
38 ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, busp);
44 struct udevice *pci_get_controller(struct udevice *dev)
46 while (device_is_on_pci_bus(dev))
52 pci_dev_t dm_pci_get_bdf(const struct udevice *dev)
54 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
55 struct udevice *bus = dev->parent;
58 * This error indicates that @dev is a device on an unprobed PCI bus.
59 * The bus likely has bus=seq == -1, so the PCI_ADD_BUS() macro below
60 * will produce a bad BDF>
62 * A common cause of this problem is that this function is called in the
63 * of_to_plat() method of @dev. Accessing the PCI bus in that
64 * method is not allowed, since it has not yet been probed. To fix this,
65 * move that access to the probe() method of @dev instead.
67 if (!device_active(bus))
68 log_err("PCI: Device '%s' on unprobed bus '%s'\n", dev->name,
70 return PCI_ADD_BUS(dev_seq(bus), pplat->devfn);
74 * pci_get_bus_max() - returns the bus number of the last active bus
76 * @return last bus number, or -1 if no active buses
78 static int pci_get_bus_max(void)
84 ret = uclass_get(UCLASS_PCI, &uc);
85 uclass_foreach_dev(bus, uc) {
86 if (dev_seq(bus) > ret)
90 debug("%s: ret=%d\n", __func__, ret);
95 int pci_last_busno(void)
97 return pci_get_bus_max();
100 int pci_get_ff(enum pci_size_t size)
112 static void pci_dev_find_ofnode(struct udevice *bus, phys_addr_t bdf,
115 struct fdt_pci_addr addr;
119 dev_for_each_subnode(node, bus) {
120 ret = ofnode_read_pci_addr(node, FDT_PCI_SPACE_CONFIG, "reg",
125 if (PCI_MASK_BUS(addr.phys_hi) != PCI_MASK_BUS(bdf))
133 int pci_bus_find_devfn(const struct udevice *bus, pci_dev_t find_devfn,
134 struct udevice **devp)
138 for (device_find_first_child(bus, &dev);
140 device_find_next_child(&dev)) {
141 struct pci_child_plat *pplat;
143 pplat = dev_get_parent_plat(dev);
144 if (pplat && pplat->devfn == find_devfn) {
153 int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp)
158 ret = pci_get_bus(PCI_BUS(bdf), &bus);
161 return pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), devp);
164 static int pci_device_matches_ids(struct udevice *dev,
165 struct pci_device_id *ids)
167 struct pci_child_plat *pplat;
170 pplat = dev_get_parent_plat(dev);
173 for (i = 0; ids[i].vendor != 0; i++) {
174 if (pplat->vendor == ids[i].vendor &&
175 pplat->device == ids[i].device)
182 int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
183 int *indexp, struct udevice **devp)
187 /* Scan all devices on this bus */
188 for (device_find_first_child(bus, &dev);
190 device_find_next_child(&dev)) {
191 if (pci_device_matches_ids(dev, ids) >= 0) {
192 if ((*indexp)-- <= 0) {
202 int pci_find_device_id(struct pci_device_id *ids, int index,
203 struct udevice **devp)
207 /* Scan all known buses */
208 for (uclass_first_device(UCLASS_PCI, &bus);
210 uclass_next_device(&bus)) {
211 if (!pci_bus_find_devices(bus, ids, &index, devp))
219 static int dm_pci_bus_find_device(struct udevice *bus, unsigned int vendor,
220 unsigned int device, int *indexp,
221 struct udevice **devp)
223 struct pci_child_plat *pplat;
226 for (device_find_first_child(bus, &dev);
228 device_find_next_child(&dev)) {
229 pplat = dev_get_parent_plat(dev);
230 if (pplat->vendor == vendor && pplat->device == device) {
241 int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
242 struct udevice **devp)
246 /* Scan all known buses */
247 for (uclass_first_device(UCLASS_PCI, &bus);
249 uclass_next_device(&bus)) {
250 if (!dm_pci_bus_find_device(bus, vendor, device, &index, devp))
251 return device_probe(*devp);
258 int dm_pci_find_class(uint find_class, int index, struct udevice **devp)
262 /* Scan all known buses */
263 for (pci_find_first_device(&dev);
265 pci_find_next_device(&dev)) {
266 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
268 if (pplat->class == find_class && !index--) {
270 return device_probe(*devp);
278 int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
279 unsigned long value, enum pci_size_t size)
281 struct dm_pci_ops *ops;
283 ops = pci_get_ops(bus);
284 if (!ops->write_config)
286 return ops->write_config(bus, bdf, offset, value, size);
289 int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
295 ret = pci_bus_read_config(bus, bdf, offset, &val, PCI_SIZE_32);
301 return pci_bus_write_config(bus, bdf, offset, val, PCI_SIZE_32);
304 int pci_write_config(pci_dev_t bdf, int offset, unsigned long value,
305 enum pci_size_t size)
310 ret = pci_get_bus(PCI_BUS(bdf), &bus);
314 return pci_bus_write_config(bus, bdf, offset, value, size);
317 int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
318 enum pci_size_t size)
322 for (bus = dev; device_is_on_pci_bus(bus);)
324 return pci_bus_write_config(bus, dm_pci_get_bdf(dev), offset, value,
328 int pci_write_config32(pci_dev_t bdf, int offset, u32 value)
330 return pci_write_config(bdf, offset, value, PCI_SIZE_32);
333 int pci_write_config16(pci_dev_t bdf, int offset, u16 value)
335 return pci_write_config(bdf, offset, value, PCI_SIZE_16);
338 int pci_write_config8(pci_dev_t bdf, int offset, u8 value)
340 return pci_write_config(bdf, offset, value, PCI_SIZE_8);
343 int dm_pci_write_config8(struct udevice *dev, int offset, u8 value)
345 return dm_pci_write_config(dev, offset, value, PCI_SIZE_8);
348 int dm_pci_write_config16(struct udevice *dev, int offset, u16 value)
350 return dm_pci_write_config(dev, offset, value, PCI_SIZE_16);
353 int dm_pci_write_config32(struct udevice *dev, int offset, u32 value)
355 return dm_pci_write_config(dev, offset, value, PCI_SIZE_32);
358 int pci_bus_read_config(const struct udevice *bus, pci_dev_t bdf, int offset,
359 unsigned long *valuep, enum pci_size_t size)
361 struct dm_pci_ops *ops;
363 ops = pci_get_ops(bus);
364 if (!ops->read_config)
366 return ops->read_config(bus, bdf, offset, valuep, size);
369 int pci_read_config(pci_dev_t bdf, int offset, unsigned long *valuep,
370 enum pci_size_t size)
375 ret = pci_get_bus(PCI_BUS(bdf), &bus);
379 return pci_bus_read_config(bus, bdf, offset, valuep, size);
382 int dm_pci_read_config(const struct udevice *dev, int offset,
383 unsigned long *valuep, enum pci_size_t size)
385 const struct udevice *bus;
387 for (bus = dev; device_is_on_pci_bus(bus);)
389 return pci_bus_read_config(bus, dm_pci_get_bdf(dev), offset, valuep,
393 int pci_read_config32(pci_dev_t bdf, int offset, u32 *valuep)
398 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_32);
406 int pci_read_config16(pci_dev_t bdf, int offset, u16 *valuep)
411 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_16);
419 int pci_read_config8(pci_dev_t bdf, int offset, u8 *valuep)
424 ret = pci_read_config(bdf, offset, &value, PCI_SIZE_8);
432 int dm_pci_read_config8(const struct udevice *dev, int offset, u8 *valuep)
437 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_8);
445 int dm_pci_read_config16(const struct udevice *dev, int offset, u16 *valuep)
450 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_16);
458 int dm_pci_read_config32(const struct udevice *dev, int offset, u32 *valuep)
463 ret = dm_pci_read_config(dev, offset, &value, PCI_SIZE_32);
471 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set)
476 ret = dm_pci_read_config8(dev, offset, &val);
482 return dm_pci_write_config8(dev, offset, val);
485 int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set)
490 ret = dm_pci_read_config16(dev, offset, &val);
496 return dm_pci_write_config16(dev, offset, val);
499 int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set)
504 ret = dm_pci_read_config32(dev, offset, &val);
510 return dm_pci_write_config32(dev, offset, val);
513 static void set_vga_bridge_bits(struct udevice *dev)
515 struct udevice *parent = dev->parent;
518 while (dev_seq(parent) != 0) {
519 dm_pci_read_config16(parent, PCI_BRIDGE_CONTROL, &bc);
520 bc |= PCI_BRIDGE_CTL_VGA;
521 dm_pci_write_config16(parent, PCI_BRIDGE_CONTROL, bc);
522 parent = parent->parent;
526 int pci_auto_config_devices(struct udevice *bus)
528 struct pci_controller *hose = dev_get_uclass_priv(bus);
529 struct pci_child_plat *pplat;
530 unsigned int sub_bus;
534 sub_bus = dev_seq(bus);
535 debug("%s: start\n", __func__);
536 pciauto_config_init(hose);
537 for (ret = device_find_first_child(bus, &dev);
539 ret = device_find_next_child(&dev)) {
540 unsigned int max_bus;
543 debug("%s: device %s\n", __func__, dev->name);
544 if (dev_has_ofnode(dev) &&
545 dev_read_bool(dev, "pci,no-autoconfig"))
547 ret = dm_pciauto_config_device(dev);
549 return log_msg_ret("auto", ret);
551 sub_bus = max(sub_bus, max_bus);
553 pplat = dev_get_parent_plat(dev);
554 if (pplat->class == (PCI_CLASS_DISPLAY_VGA << 8))
555 set_vga_bridge_bits(dev);
557 debug("%s: done\n", __func__);
559 return log_msg_ret("sub", sub_bus);
562 int pci_generic_mmap_write_config(
563 const struct udevice *bus,
564 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
569 enum pci_size_t size)
573 if (addr_f(bus, bdf, offset, &address) < 0)
578 writeb(value, address);
581 writew(value, address);
584 writel(value, address);
591 int pci_generic_mmap_read_config(
592 const struct udevice *bus,
593 int (*addr_f)(const struct udevice *bus, pci_dev_t bdf, uint offset,
598 enum pci_size_t size)
602 if (addr_f(bus, bdf, offset, &address) < 0) {
603 *valuep = pci_get_ff(size);
609 *valuep = readb(address);
612 *valuep = readw(address);
615 *valuep = readl(address);
622 int dm_pci_hose_probe_bus(struct udevice *bus)
629 debug("%s\n", __func__);
631 ea_pos = dm_pci_find_capability(bus, PCI_CAP_ID_EA);
633 dm_pci_read_config8(bus, ea_pos + sizeof(u32) + sizeof(u8),
637 sub_bus = pci_get_bus_max() + 1;
639 debug("%s: bus = %d/%s\n", __func__, sub_bus, bus->name);
640 dm_pciauto_prescan_setup_bridge(bus, sub_bus);
642 ret = device_probe(bus);
644 debug("%s: Cannot probe bus %s: %d\n", __func__, bus->name,
646 return log_msg_ret("probe", ret);
650 sub_bus = pci_get_bus_max();
652 dm_pciauto_postscan_setup_bridge(bus, sub_bus);
658 * pci_match_one_device - Tell if a PCI device structure has a matching
659 * PCI device id structure
660 * @id: single PCI device id structure to match
661 * @find: the PCI device id structure to match against
663 * Returns true if the finding pci_device_id structure matched or false if
666 static bool pci_match_one_id(const struct pci_device_id *id,
667 const struct pci_device_id *find)
669 if ((id->vendor == PCI_ANY_ID || id->vendor == find->vendor) &&
670 (id->device == PCI_ANY_ID || id->device == find->device) &&
671 (id->subvendor == PCI_ANY_ID || id->subvendor == find->subvendor) &&
672 (id->subdevice == PCI_ANY_ID || id->subdevice == find->subdevice) &&
673 !((id->class ^ find->class) & id->class_mask))
680 * pci_find_and_bind_driver() - Find and bind the right PCI driver
682 * This only looks at certain fields in the descriptor.
684 * @parent: Parent bus
685 * @find_id: Specification of the driver to find
686 * @bdf: Bus/device/function addreess - see PCI_BDF()
687 * @devp: Returns a pointer to the device created
688 * @return 0 if OK, -EPERM if the device is not needed before relocation and
689 * therefore was not created, other -ve value on error
691 static int pci_find_and_bind_driver(struct udevice *parent,
692 struct pci_device_id *find_id,
693 pci_dev_t bdf, struct udevice **devp)
695 struct pci_driver_entry *start, *entry;
696 ofnode node = ofnode_null();
705 debug("%s: Searching for driver: vendor=%x, device=%x\n", __func__,
706 find_id->vendor, find_id->device);
708 /* Determine optional OF node */
709 if (ofnode_valid(dev_ofnode(parent)))
710 pci_dev_find_ofnode(parent, bdf, &node);
712 if (ofnode_valid(node) && !ofnode_is_available(node)) {
713 debug("%s: Ignoring disabled device\n", __func__);
714 return log_msg_ret("dis", -EPERM);
717 start = ll_entry_start(struct pci_driver_entry, pci_driver_entry);
718 n_ents = ll_entry_count(struct pci_driver_entry, pci_driver_entry);
719 for (entry = start; entry != start + n_ents; entry++) {
720 const struct pci_device_id *id;
722 const struct driver *drv;
724 for (id = entry->match;
725 id->vendor || id->subvendor || id->class_mask;
727 if (!pci_match_one_id(id, find_id))
733 * In the pre-relocation phase, we only bind devices
734 * whose driver has the DM_FLAG_PRE_RELOC set, to save
735 * precious memory space as on some platforms as that
736 * space is pretty limited (ie: using Cache As RAM).
738 if (!(gd->flags & GD_FLG_RELOC) &&
739 !(drv->flags & DM_FLAG_PRE_RELOC))
740 return log_msg_ret("pre", -EPERM);
743 * We could pass the descriptor to the driver as
744 * plat (instead of NULL) and allow its bind()
745 * method to return -ENOENT if it doesn't support this
746 * device. That way we could continue the search to
747 * find another driver. For now this doesn't seem
748 * necesssary, so just bind the first match.
750 ret = device_bind(parent, drv, drv->name, NULL, node,
754 debug("%s: Match found: %s\n", __func__, drv->name);
755 dev->driver_data = id->driver_data;
761 bridge = (find_id->class >> 8) == PCI_CLASS_BRIDGE_PCI;
763 * In the pre-relocation phase, we only bind bridge devices to save
764 * precious memory space as on some platforms as that space is pretty
765 * limited (ie: using Cache As RAM).
767 if (!(gd->flags & GD_FLG_RELOC) && !bridge)
768 return log_msg_ret("notbr", -EPERM);
770 /* Bind a generic driver so that the device can be used */
771 sprintf(name, "pci_%x:%x.%x", dev_seq(parent), PCI_DEV(bdf),
776 drv = bridge ? "pci_bridge_drv" : "pci_generic_drv";
778 ret = device_bind_driver_to_node(parent, drv, str, node, devp);
780 debug("%s: Failed to bind generic driver: %d\n", __func__, ret);
784 debug("%s: No match found: bound generic driver instead\n", __func__);
789 debug("%s: No match found: error %d\n", __func__, ret);
793 __weak extern void board_pci_fixup_dev(struct udevice *bus, struct udevice *dev)
797 int pci_bind_bus_devices(struct udevice *bus)
799 ulong vendor, device;
807 end = PCI_BDF(dev_seq(bus), PCI_MAX_PCI_DEVICES - 1,
808 PCI_MAX_PCI_FUNCTIONS - 1);
809 for (bdf = PCI_BDF(dev_seq(bus), 0, 0); bdf <= end;
810 bdf += PCI_BDF(0, 0, 1)) {
811 struct pci_child_plat *pplat;
817 if (PCI_FUNC(bdf) && !found_multi)
820 /* Check only the first access, we don't expect problems */
821 ret = pci_bus_read_config(bus, bdf, PCI_VENDOR_ID, &vendor,
826 if (vendor == 0xffff || vendor == 0x0000)
829 pci_bus_read_config(bus, bdf, PCI_HEADER_TYPE,
830 &header_type, PCI_SIZE_8);
833 found_multi = header_type & 0x80;
835 debug("%s: bus %d/%s: found device %x, function %d", __func__,
836 dev_seq(bus), bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
837 pci_bus_read_config(bus, bdf, PCI_DEVICE_ID, &device,
839 pci_bus_read_config(bus, bdf, PCI_CLASS_REVISION, &class,
843 /* Find this device in the device tree */
844 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
845 debug(": find ret=%d\n", ret);
847 /* If nothing in the device tree, bind a device */
848 if (ret == -ENODEV) {
849 struct pci_device_id find_id;
852 memset(&find_id, '\0', sizeof(find_id));
853 find_id.vendor = vendor;
854 find_id.device = device;
855 find_id.class = class;
856 if ((header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) {
857 pci_bus_read_config(bus, bdf,
858 PCI_SUBSYSTEM_VENDOR_ID,
860 find_id.subvendor = val & 0xffff;
861 find_id.subdevice = val >> 16;
863 ret = pci_find_and_bind_driver(bus, &find_id, bdf,
871 /* Update the platform data */
872 pplat = dev_get_parent_plat(dev);
873 pplat->devfn = PCI_MASK_BUS(bdf);
874 pplat->vendor = vendor;
875 pplat->device = device;
876 pplat->class = class;
878 if (IS_ENABLED(CONFIG_PCI_ARID)) {
879 ari_off = dm_pci_find_ext_capability(dev,
885 * Read Next Function number in ARI Cap
888 dm_pci_read_config16(dev, ari_off + 4,
891 * Update next scan on this function number,
892 * subtract 1 in BDF to satisfy loop increment.
894 if (ari_cap & 0xff00) {
895 bdf = PCI_BDF(PCI_BUS(bdf),
903 board_pci_fixup_dev(bus, dev);
908 printf("Cannot read bus configuration: %d\n", ret);
913 static void decode_regions(struct pci_controller *hose, ofnode parent_node,
916 int pci_addr_cells, addr_cells, size_cells;
917 int cells_per_record;
924 prop = ofnode_get_property(node, "ranges", &len);
926 debug("%s: Cannot decode regions\n", __func__);
930 pci_addr_cells = ofnode_read_simple_addr_cells(node);
931 addr_cells = ofnode_read_simple_addr_cells(parent_node);
932 size_cells = ofnode_read_simple_size_cells(node);
934 /* PCI addresses are always 3-cells */
936 cells_per_record = pci_addr_cells + addr_cells + size_cells;
937 hose->region_count = 0;
938 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
941 /* Dynamically allocate the regions array */
942 max_regions = len / cells_per_record + CONFIG_NR_DRAM_BANKS;
943 hose->regions = (struct pci_region *)
944 calloc(1, max_regions * sizeof(struct pci_region));
946 for (i = 0; i < max_regions; i++, len -= cells_per_record) {
947 u64 pci_addr, addr, size;
953 if (len < cells_per_record)
955 flags = fdt32_to_cpu(prop[0]);
956 space_code = (flags >> 24) & 3;
957 pci_addr = fdtdec_get_number(prop + 1, 2);
958 prop += pci_addr_cells;
959 addr = fdtdec_get_number(prop, addr_cells);
961 size = fdtdec_get_number(prop, size_cells);
963 debug("%s: region %d, pci_addr=%llx, addr=%llx, size=%llx, space_code=%d\n",
964 __func__, hose->region_count, pci_addr, addr, size, space_code);
965 if (space_code & 2) {
966 type = flags & (1U << 30) ? PCI_REGION_PREFETCH :
968 } else if (space_code & 1) {
969 type = PCI_REGION_IO;
974 if (!IS_ENABLED(CONFIG_SYS_PCI_64BIT) &&
975 type == PCI_REGION_MEM && upper_32_bits(pci_addr)) {
976 debug(" - beyond the 32-bit boundary, ignoring\n");
981 if (!IS_ENABLED(CONFIG_PCI_REGION_MULTI_ENTRY)) {
982 for (i = 0; i < hose->region_count; i++) {
983 if (hose->regions[i].flags == type)
989 pos = hose->region_count++;
990 debug(" - type=%d, pos=%d\n", type, pos);
991 pci_set_region(hose->regions + pos, pci_addr, addr, size, type);
994 /* Add a region for our local memory */
999 for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
1000 if (bd->bi_dram[i].size) {
1001 pci_set_region(hose->regions + hose->region_count++,
1002 bd->bi_dram[i].start,
1003 bd->bi_dram[i].start,
1004 bd->bi_dram[i].size,
1005 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
1012 static int pci_uclass_pre_probe(struct udevice *bus)
1014 struct pci_controller *hose;
1018 debug("%s, bus=%d/%s, parent=%s\n", __func__, dev_seq(bus), bus->name,
1020 hose = dev_get_uclass_priv(bus);
1023 * Set the sequence number, if device_bind() doesn't. We want control
1024 * of this so that numbers are allocated as devices are probed. That
1025 * ensures that sub-bus numbered is correct (sub-buses must get numbers
1026 * higher than their parents)
1028 if (dev_seq(bus) == -1) {
1029 ret = uclass_get(UCLASS_PCI, &uc);
1032 bus->seq_ = uclass_find_next_free_seq(uc);
1035 /* For bridges, use the top-level PCI controller */
1036 if (!device_is_on_pci_bus(bus)) {
1038 decode_regions(hose, dev_ofnode(bus->parent), dev_ofnode(bus));
1040 struct pci_controller *parent_hose;
1042 parent_hose = dev_get_uclass_priv(bus->parent);
1043 hose->ctlr = parent_hose->bus;
1047 hose->first_busno = dev_seq(bus);
1048 hose->last_busno = dev_seq(bus);
1049 if (dev_has_ofnode(bus)) {
1050 hose->skip_auto_config_until_reloc =
1052 "u-boot,skip-auto-config-until-reloc");
1058 static int pci_uclass_post_probe(struct udevice *bus)
1060 struct pci_controller *hose = dev_get_uclass_priv(bus);
1063 debug("%s: probing bus %d\n", __func__, dev_seq(bus));
1064 ret = pci_bind_bus_devices(bus);
1066 return log_msg_ret("bind", ret);
1068 if (CONFIG_IS_ENABLED(PCI_PNP) && ll_boot_init() &&
1069 (!hose->skip_auto_config_until_reloc ||
1070 (gd->flags & GD_FLG_RELOC))) {
1071 ret = pci_auto_config_devices(bus);
1073 return log_msg_ret("cfg", ret);
1076 #if defined(CONFIG_X86) && defined(CONFIG_HAVE_FSP)
1078 * Per Intel FSP specification, we should call FSP notify API to
1079 * inform FSP that PCI enumeration has been done so that FSP will
1080 * do any necessary initialization as required by the chipset's
1081 * BIOS Writer's Guide (BWG).
1083 * Unfortunately we have to put this call here as with driver model,
1084 * the enumeration is all done on a lazy basis as needed, so until
1085 * something is touched on PCI it won't happen.
1087 * Note we only call this 1) after U-Boot is relocated, and 2)
1088 * root bus has finished probing.
1090 if ((gd->flags & GD_FLG_RELOC) && dev_seq(bus) == 0 && ll_boot_init()) {
1091 ret = fsp_init_phase_pci();
1093 return log_msg_ret("fsp", ret);
1100 static int pci_uclass_child_post_bind(struct udevice *dev)
1102 struct pci_child_plat *pplat;
1104 if (!dev_has_ofnode(dev))
1107 pplat = dev_get_parent_plat(dev);
1109 /* Extract vendor id and device id if available */
1110 ofnode_read_pci_vendev(dev_ofnode(dev), &pplat->vendor, &pplat->device);
1112 /* Extract the devfn from fdt_pci_addr */
1113 pplat->devfn = pci_get_devfn(dev);
1118 static int pci_bridge_read_config(const struct udevice *bus, pci_dev_t bdf,
1119 uint offset, ulong *valuep,
1120 enum pci_size_t size)
1122 struct pci_controller *hose = dev_get_uclass_priv(bus);
1124 return pci_bus_read_config(hose->ctlr, bdf, offset, valuep, size);
1127 static int pci_bridge_write_config(struct udevice *bus, pci_dev_t bdf,
1128 uint offset, ulong value,
1129 enum pci_size_t size)
1131 struct pci_controller *hose = dev_get_uclass_priv(bus);
1133 return pci_bus_write_config(hose->ctlr, bdf, offset, value, size);
1136 static int skip_to_next_device(struct udevice *bus, struct udevice **devp)
1138 struct udevice *dev;
1142 * Scan through all the PCI controllers. On x86 there will only be one
1143 * but that is not necessarily true on other hardware.
1146 device_find_first_child(bus, &dev);
1151 ret = uclass_next_device(&bus);
1159 int pci_find_next_device(struct udevice **devp)
1161 struct udevice *child = *devp;
1162 struct udevice *bus = child->parent;
1165 /* First try all the siblings */
1168 device_find_next_child(&child);
1175 /* We ran out of siblings. Try the next bus */
1176 ret = uclass_next_device(&bus);
1180 return bus ? skip_to_next_device(bus, devp) : 0;
1183 int pci_find_first_device(struct udevice **devp)
1185 struct udevice *bus;
1189 ret = uclass_first_device(UCLASS_PCI, &bus);
1193 return skip_to_next_device(bus, devp);
1196 ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size)
1200 return (value >> ((offset & 3) * 8)) & 0xff;
1202 return (value >> ((offset & 2) * 8)) & 0xffff;
1208 ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
1209 enum pci_size_t size)
1212 uint val_mask, shift;
1227 shift = (offset & off_mask) * 8;
1228 ldata = (value & val_mask) << shift;
1229 mask = val_mask << shift;
1230 value = (old & ~mask) | ldata;
1235 int pci_get_dma_regions(struct udevice *dev, struct pci_region *memp, int index)
1237 int pci_addr_cells, addr_cells, size_cells;
1238 int cells_per_record;
1243 prop = ofnode_get_property(dev_ofnode(dev), "dma-ranges", &len);
1245 log_err("PCI: Device '%s': Cannot decode dma-ranges\n",
1250 pci_addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev));
1251 addr_cells = ofnode_read_simple_addr_cells(dev_ofnode(dev->parent));
1252 size_cells = ofnode_read_simple_size_cells(dev_ofnode(dev));
1254 /* PCI addresses are always 3-cells */
1256 cells_per_record = pci_addr_cells + addr_cells + size_cells;
1257 debug("%s: len=%d, cells_per_record=%d\n", __func__, len,
1261 memp->bus_start = fdtdec_get_number(prop + 1, 2);
1262 prop += pci_addr_cells;
1263 memp->phys_start = fdtdec_get_number(prop, addr_cells);
1265 memp->size = fdtdec_get_number(prop, size_cells);
1271 len -= cells_per_record;
1277 int pci_get_regions(struct udevice *dev, struct pci_region **iop,
1278 struct pci_region **memp, struct pci_region **prefp)
1280 struct udevice *bus = pci_get_controller(dev);
1281 struct pci_controller *hose = dev_get_uclass_priv(bus);
1287 for (i = 0; i < hose->region_count; i++) {
1288 switch (hose->regions[i].flags) {
1290 if (!*iop || (*iop)->size < hose->regions[i].size)
1291 *iop = hose->regions + i;
1293 case PCI_REGION_MEM:
1294 if (!*memp || (*memp)->size < hose->regions[i].size)
1295 *memp = hose->regions + i;
1297 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
1298 if (!*prefp || (*prefp)->size < hose->regions[i].size)
1299 *prefp = hose->regions + i;
1304 return (*iop != NULL) + (*memp != NULL) + (*prefp != NULL);
1307 u32 dm_pci_read_bar32(const struct udevice *dev, int barnum)
1312 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1313 dm_pci_read_config32(dev, bar, &addr);
1316 * If we get an invalid address, return this so that comparisons with
1317 * FDT_ADDR_T_NONE work correctly
1319 if (addr == 0xffffffff)
1321 else if (addr & PCI_BASE_ADDRESS_SPACE_IO)
1322 return addr & PCI_BASE_ADDRESS_IO_MASK;
1324 return addr & PCI_BASE_ADDRESS_MEM_MASK;
1327 void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr)
1331 bar = PCI_BASE_ADDRESS_0 + barnum * 4;
1332 dm_pci_write_config32(dev, bar, addr);
1335 static int _dm_pci_bus_to_phys(struct udevice *ctlr,
1336 pci_addr_t bus_addr, unsigned long flags,
1337 unsigned long skip_mask, phys_addr_t *pa)
1339 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
1340 struct pci_region *res;
1343 if (hose->region_count == 0) {
1348 for (i = 0; i < hose->region_count; i++) {
1349 res = &hose->regions[i];
1351 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1354 if (res->flags & skip_mask)
1357 if (bus_addr >= res->bus_start &&
1358 (bus_addr - res->bus_start) < res->size) {
1359 *pa = (bus_addr - res->bus_start + res->phys_start);
1367 phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t bus_addr,
1368 unsigned long flags)
1370 phys_addr_t phys_addr = 0;
1371 struct udevice *ctlr;
1374 /* The root controller has the region information */
1375 ctlr = pci_get_controller(dev);
1378 * if PCI_REGION_MEM is set we do a two pass search with preference
1379 * on matches that don't have PCI_REGION_SYS_MEMORY set
1381 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1382 ret = _dm_pci_bus_to_phys(ctlr, bus_addr,
1383 flags, PCI_REGION_SYS_MEMORY,
1389 ret = _dm_pci_bus_to_phys(ctlr, bus_addr, flags, 0, &phys_addr);
1392 puts("pci_hose_bus_to_phys: invalid physical address\n");
1397 int _dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1398 unsigned long flags, unsigned long skip_mask,
1401 struct pci_region *res;
1402 struct udevice *ctlr;
1403 pci_addr_t bus_addr;
1405 struct pci_controller *hose;
1407 /* The root controller has the region information */
1408 ctlr = pci_get_controller(dev);
1409 hose = dev_get_uclass_priv(ctlr);
1411 if (hose->region_count == 0) {
1416 for (i = 0; i < hose->region_count; i++) {
1417 res = &hose->regions[i];
1419 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
1422 if (res->flags & skip_mask)
1425 bus_addr = phys_addr - res->phys_start + res->bus_start;
1427 if (bus_addr >= res->bus_start &&
1428 (bus_addr - res->bus_start) < res->size) {
1437 pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t phys_addr,
1438 unsigned long flags)
1440 pci_addr_t bus_addr = 0;
1444 * if PCI_REGION_MEM is set we do a two pass search with preference
1445 * on matches that don't have PCI_REGION_SYS_MEMORY set
1447 if ((flags & PCI_REGION_TYPE) == PCI_REGION_MEM) {
1448 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags,
1449 PCI_REGION_SYS_MEMORY, &bus_addr);
1454 ret = _dm_pci_phys_to_bus(dev, phys_addr, flags, 0, &bus_addr);
1457 puts("pci_hose_phys_to_bus: invalid physical address\n");
1462 static phys_addr_t dm_pci_map_ea_virt(struct udevice *dev, int ea_off,
1463 struct pci_child_plat *pdata)
1465 phys_addr_t addr = 0;
1468 * In the case of a Virtual Function device using BAR
1469 * base and size, add offset for VFn BAR(1, 2, 3...n)
1471 if (pdata->is_virtfn) {
1475 /* MaxOffset, 1st DW */
1476 dm_pci_read_config32(dev, ea_off + 8, &ea_entry);
1477 sz = ea_entry & PCI_EA_FIELD_MASK;
1478 /* Fill up lower 2 bits */
1479 sz |= (~PCI_EA_FIELD_MASK);
1481 if (ea_entry & PCI_EA_IS_64) {
1482 /* MaxOffset 2nd DW */
1483 dm_pci_read_config32(dev, ea_off + 16, &ea_entry);
1484 sz |= ((u64)ea_entry) << 32;
1487 addr = (pdata->virtid - 1) * (sz + 1);
1493 static void *dm_pci_map_ea_bar(struct udevice *dev, int bar, int flags,
1494 int ea_off, struct pci_child_plat *pdata)
1496 int ea_cnt, i, entry_size;
1497 int bar_id = (bar - PCI_BASE_ADDRESS_0) >> 2;
1501 if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
1503 * In the case of a Virtual Function device, device is
1504 * Physical function, so pdata will point to required VF
1507 if (pdata->is_virtfn)
1508 bar_id += PCI_EA_BEI_VF_BAR0;
1511 /* EA capability structure header */
1512 dm_pci_read_config32(dev, ea_off, &ea_entry);
1513 ea_cnt = (ea_entry >> 16) & PCI_EA_NUM_ENT_MASK;
1514 ea_off += PCI_EA_FIRST_ENT;
1516 for (i = 0; i < ea_cnt; i++, ea_off += entry_size) {
1518 dm_pci_read_config32(dev, ea_off, &ea_entry);
1519 entry_size = ((ea_entry & PCI_EA_ES) + 1) << 2;
1521 if (((ea_entry & PCI_EA_BEI) >> 4) != bar_id)
1524 /* Base address, 1st DW */
1525 dm_pci_read_config32(dev, ea_off + 4, &ea_entry);
1526 addr = ea_entry & PCI_EA_FIELD_MASK;
1527 if (ea_entry & PCI_EA_IS_64) {
1528 /* Base address, 2nd DW, skip over 4B MaxOffset */
1529 dm_pci_read_config32(dev, ea_off + 12, &ea_entry);
1530 addr |= ((u64)ea_entry) << 32;
1533 if (IS_ENABLED(CONFIG_PCI_SRIOV))
1534 addr += dm_pci_map_ea_virt(dev, ea_off, pdata);
1536 /* size ignored for now */
1537 return map_physmem(addr, 0, flags);
1543 void *dm_pci_map_bar(struct udevice *dev, int bar, int flags)
1545 struct pci_child_plat *pdata = dev_get_parent_plat(dev);
1546 struct udevice *udev = dev;
1547 pci_addr_t pci_bus_addr;
1551 if (IS_ENABLED(CONFIG_PCI_SRIOV)) {
1553 * In case of Virtual Function devices, use PF udevice
1554 * as EA capability is defined in Physical Function
1556 if (pdata->is_virtfn)
1557 udev = pdata->pfdev;
1561 * if the function supports Enhanced Allocation use that instead of
1563 * Incase of virtual functions, pdata will help read VF BEI
1564 * and EA entry size.
1566 ea_off = dm_pci_find_capability(udev, PCI_CAP_ID_EA);
1568 return dm_pci_map_ea_bar(udev, bar, flags, ea_off, pdata);
1570 /* read BAR address */
1571 dm_pci_read_config32(udev, bar, &bar_response);
1572 pci_bus_addr = (pci_addr_t)(bar_response & ~0xf);
1575 * Pass "0" as the length argument to pci_bus_to_virt. The arg
1576 * isn't actually used on any platform because U-Boot assumes a static
1577 * linear mapping. In the future, this could read the BAR size
1578 * and pass that as the size if needed.
1580 return dm_pci_bus_to_virt(udev, pci_bus_addr, flags, 0, MAP_NOCACHE);
1583 static int _dm_pci_find_next_capability(struct udevice *dev, u8 pos, int cap)
1585 int ttl = PCI_FIND_CAP_TTL;
1589 dm_pci_read_config8(dev, pos, &pos);
1592 if (pos < PCI_STD_HEADER_SIZEOF)
1595 dm_pci_read_config16(dev, pos, &ent);
1608 int dm_pci_find_next_capability(struct udevice *dev, u8 start, int cap)
1610 return _dm_pci_find_next_capability(dev, start + PCI_CAP_LIST_NEXT,
1614 int dm_pci_find_capability(struct udevice *dev, int cap)
1620 dm_pci_read_config16(dev, PCI_STATUS, &status);
1621 if (!(status & PCI_STATUS_CAP_LIST))
1624 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
1625 if ((header_type & 0x7f) == PCI_HEADER_TYPE_CARDBUS)
1626 pos = PCI_CB_CAPABILITY_LIST;
1628 pos = PCI_CAPABILITY_LIST;
1630 return _dm_pci_find_next_capability(dev, pos, cap);
1633 int dm_pci_find_next_ext_capability(struct udevice *dev, int start, int cap)
1637 int pos = PCI_CFG_SPACE_SIZE;
1639 /* minimum 8 bytes per capability */
1640 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
1645 dm_pci_read_config32(dev, pos, &header);
1647 * If we have no capabilities, this is indicated by cap ID,
1648 * cap version and next pointer all being 0.
1654 if (PCI_EXT_CAP_ID(header) == cap)
1657 pos = PCI_EXT_CAP_NEXT(header);
1658 if (pos < PCI_CFG_SPACE_SIZE)
1661 dm_pci_read_config32(dev, pos, &header);
1667 int dm_pci_find_ext_capability(struct udevice *dev, int cap)
1669 return dm_pci_find_next_ext_capability(dev, 0, cap);
1672 int dm_pci_flr(struct udevice *dev)
1677 /* look for PCI Express Capability */
1678 pcie_off = dm_pci_find_capability(dev, PCI_CAP_ID_EXP);
1682 /* check FLR capability */
1683 dm_pci_read_config32(dev, pcie_off + PCI_EXP_DEVCAP, &cap);
1684 if (!(cap & PCI_EXP_DEVCAP_FLR))
1687 dm_pci_clrset_config16(dev, pcie_off + PCI_EXP_DEVCTL, 0,
1688 PCI_EXP_DEVCTL_BCR_FLR);
1690 /* wait 100ms, per PCI spec */
1696 #if defined(CONFIG_PCI_SRIOV)
1697 int pci_sriov_init(struct udevice *pdev, int vf_en)
1700 struct udevice *bus;
1701 struct udevice *dev;
1711 pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1713 debug("Error: SRIOV capability not found\n");
1717 dm_pci_read_config16(pdev, pos + PCI_SRIOV_CTRL, &ctrl);
1719 dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
1720 if (vf_en > total_vf)
1722 dm_pci_write_config16(pdev, pos + PCI_SRIOV_NUM_VF, vf_en);
1724 ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
1725 dm_pci_write_config16(pdev, pos + PCI_SRIOV_CTRL, ctrl);
1727 dm_pci_read_config16(pdev, pos + PCI_SRIOV_NUM_VF, &num_vfs);
1728 if (num_vfs > vf_en)
1731 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_OFFSET, &vf_offset);
1732 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_STRIDE, &vf_stride);
1734 dm_pci_read_config16(pdev, PCI_VENDOR_ID, &vendor);
1735 dm_pci_read_config16(pdev, pos + PCI_SRIOV_VF_DID, &device);
1737 bdf = dm_pci_get_bdf(pdev);
1739 pci_get_bus(PCI_BUS(bdf), &bus);
1744 bdf += PCI_BDF(0, 0, vf_offset);
1746 for (vf = 0; vf < num_vfs; vf++) {
1747 struct pci_child_plat *pplat;
1750 pci_bus_read_config(bus, bdf, PCI_CLASS_DEVICE,
1751 &class, PCI_SIZE_16);
1753 debug("%s: bus %d/%s: found VF %x:%x\n", __func__,
1754 dev_seq(bus), bus->name, PCI_DEV(bdf), PCI_FUNC(bdf));
1756 /* Find this device in the device tree */
1757 ret = pci_bus_find_devfn(bus, PCI_MASK_BUS(bdf), &dev);
1759 if (ret == -ENODEV) {
1760 struct pci_device_id find_id;
1762 memset(&find_id, '\0', sizeof(find_id));
1763 find_id.vendor = vendor;
1764 find_id.device = device;
1765 find_id.class = class;
1767 ret = pci_find_and_bind_driver(bus, &find_id,
1774 /* Update the platform data */
1775 pplat = dev_get_parent_plat(dev);
1776 pplat->devfn = PCI_MASK_BUS(bdf);
1777 pplat->vendor = vendor;
1778 pplat->device = device;
1779 pplat->class = class;
1780 pplat->is_virtfn = true;
1781 pplat->pfdev = pdev;
1782 pplat->virtid = vf * vf_stride + vf_offset;
1784 debug("%s: bus %d/%s: found VF %x:%x %x:%x class %lx id %x\n",
1785 __func__, dev_seq(dev), dev->name, PCI_DEV(bdf),
1786 PCI_FUNC(bdf), vendor, device, class, pplat->virtid);
1787 bdf += PCI_BDF(0, 0, vf_stride);
1793 int pci_sriov_get_totalvfs(struct udevice *pdev)
1798 pos = dm_pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1800 debug("Error: SRIOV capability not found\n");
1804 dm_pci_read_config16(pdev, pos + PCI_SRIOV_TOTAL_VF, &total_vf);
1810 UCLASS_DRIVER(pci) = {
1813 .flags = DM_UC_FLAG_SEQ_ALIAS | DM_UC_FLAG_NO_AUTO_SEQ,
1814 .post_bind = dm_scan_fdt_dev,
1815 .pre_probe = pci_uclass_pre_probe,
1816 .post_probe = pci_uclass_post_probe,
1817 .child_post_bind = pci_uclass_child_post_bind,
1818 .per_device_auto = sizeof(struct pci_controller),
1819 .per_child_plat_auto = sizeof(struct pci_child_plat),
1822 static const struct dm_pci_ops pci_bridge_ops = {
1823 .read_config = pci_bridge_read_config,
1824 .write_config = pci_bridge_write_config,
1827 static const struct udevice_id pci_bridge_ids[] = {
1828 { .compatible = "pci-bridge" },
1832 U_BOOT_DRIVER(pci_bridge_drv) = {
1833 .name = "pci_bridge_drv",
1835 .of_match = pci_bridge_ids,
1836 .ops = &pci_bridge_ops,
1839 UCLASS_DRIVER(pci_generic) = {
1840 .id = UCLASS_PCI_GENERIC,
1841 .name = "pci_generic",
1844 static const struct udevice_id pci_generic_ids[] = {
1845 { .compatible = "pci-generic" },
1849 U_BOOT_DRIVER(pci_generic_drv) = {
1850 .name = "pci_generic_drv",
1851 .id = UCLASS_PCI_GENERIC,
1852 .of_match = pci_generic_ids,
1857 struct udevice *bus;
1860 * Enumerate all known controller devices. Enumeration has the side-
1861 * effect of probing them, so PCIe devices will be enumerated too.
1863 for (uclass_first_device_check(UCLASS_PCI, &bus);
1865 uclass_next_device_check(&bus)) {