3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/init.h>
14 #include <linux/export.h>
15 #include <linux/ioport.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
18 #include <linux/msi.h>
19 #include <linux/smp.h>
20 #include <linux/errno.h>
22 #include <linux/slab.h>
26 static int pci_msi_enable = 1;
28 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
33 int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
35 struct msi_chip *chip = dev->bus->msi;
38 if (!chip || !chip->setup_irq)
41 err = chip->setup_irq(chip, dev, desc);
45 irq_set_chip_data(desc->irq, chip);
50 void __weak arch_teardown_msi_irq(unsigned int irq)
52 struct msi_chip *chip = irq_get_chip_data(irq);
54 if (!chip || !chip->teardown_irq)
57 chip->teardown_irq(chip, irq);
60 int __weak arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
62 struct msi_chip *chip = dev->bus->msi;
64 if (!chip || !chip->check_device)
67 return chip->check_device(chip, dev, nvec, type);
70 int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
72 struct msi_desc *entry;
76 * If an architecture wants to support multiple MSI, it needs to
77 * override arch_setup_msi_irqs()
79 if (type == PCI_CAP_ID_MSI && nvec > 1)
82 list_for_each_entry(entry, &dev->msi_list, list) {
83 ret = arch_setup_msi_irq(dev, entry);
94 * We have a default implementation available as a separate non-weak
95 * function, as it is used by the Xen x86 PCI code
97 void default_teardown_msi_irqs(struct pci_dev *dev)
99 struct msi_desc *entry;
101 list_for_each_entry(entry, &dev->msi_list, list) {
105 if (entry->nvec_used)
106 nvec = entry->nvec_used;
108 nvec = 1 << entry->msi_attrib.multiple;
109 for (i = 0; i < nvec; i++)
110 arch_teardown_msi_irq(entry->irq + i);
114 void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
116 return default_teardown_msi_irqs(dev);
119 static void default_restore_msi_irq(struct pci_dev *dev, int irq)
121 struct msi_desc *entry;
124 if (dev->msix_enabled) {
125 list_for_each_entry(entry, &dev->msi_list, list) {
126 if (irq == entry->irq)
129 } else if (dev->msi_enabled) {
130 entry = irq_get_msi_desc(irq);
134 write_msi_msg(irq, &entry->msg);
137 void __weak arch_restore_msi_irqs(struct pci_dev *dev)
139 return default_restore_msi_irqs(dev);
142 static void msi_set_enable(struct pci_dev *dev, int enable)
146 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
147 control &= ~PCI_MSI_FLAGS_ENABLE;
149 control |= PCI_MSI_FLAGS_ENABLE;
150 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
153 static void msix_set_enable(struct pci_dev *dev, int enable)
157 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
158 control &= ~PCI_MSIX_FLAGS_ENABLE;
160 control |= PCI_MSIX_FLAGS_ENABLE;
161 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
164 static inline __attribute_const__ u32 msi_mask(unsigned x)
166 /* Don't shift by >= width of type */
169 return (1 << (1 << x)) - 1;
172 static inline __attribute_const__ u32 msi_capable_mask(u16 control)
174 return msi_mask((control >> 1) & 7);
177 static inline __attribute_const__ u32 msi_enabled_mask(u16 control)
179 return msi_mask((control >> 4) & 7);
183 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
184 * mask all MSI interrupts by clearing the MSI enable bit does not work
185 * reliably as devices without an INTx disable bit will then generate a
186 * level IRQ which will never be cleared.
188 u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
190 u32 mask_bits = desc->masked;
192 if (!desc->msi_attrib.maskbit)
197 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
202 __weak u32 arch_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
204 return default_msi_mask_irq(desc, mask, flag);
207 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
209 desc->masked = arch_msi_mask_irq(desc, mask, flag);
213 * This internal function does not flush PCI writes to the device.
214 * All users must ensure that they read from the device before either
215 * assuming that the device state is up to date, or returning out of this
216 * file. This saves a few milliseconds when initialising devices with lots
217 * of MSI-X interrupts.
219 u32 default_msix_mask_irq(struct msi_desc *desc, u32 flag)
221 u32 mask_bits = desc->masked;
222 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
223 PCI_MSIX_ENTRY_VECTOR_CTRL;
224 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
226 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
227 writel(mask_bits, desc->mask_base + offset);
232 __weak u32 arch_msix_mask_irq(struct msi_desc *desc, u32 flag)
234 return default_msix_mask_irq(desc, flag);
237 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
239 desc->masked = arch_msix_mask_irq(desc, flag);
242 static void msi_set_mask_bit(struct irq_data *data, u32 flag)
244 struct msi_desc *desc = irq_data_get_msi(data);
246 if (desc->msi_attrib.is_msix) {
247 msix_mask_irq(desc, flag);
248 readl(desc->mask_base); /* Flush write to device */
250 unsigned offset = data->irq - desc->dev->irq;
251 msi_mask_irq(desc, 1 << offset, flag << offset);
255 void mask_msi_irq(struct irq_data *data)
257 msi_set_mask_bit(data, 1);
260 void unmask_msi_irq(struct irq_data *data)
262 msi_set_mask_bit(data, 0);
265 void default_restore_msi_irqs(struct pci_dev *dev)
267 struct msi_desc *entry;
269 list_for_each_entry(entry, &dev->msi_list, list) {
270 default_restore_msi_irq(dev, entry->irq);
274 void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
276 BUG_ON(entry->dev->current_state != PCI_D0);
278 if (entry->msi_attrib.is_msix) {
279 void __iomem *base = entry->mask_base +
280 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
282 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
283 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
284 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
286 struct pci_dev *dev = entry->dev;
287 int pos = dev->msi_cap;
290 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
292 if (entry->msi_attrib.is_64) {
293 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
295 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
298 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
304 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
306 struct msi_desc *entry = irq_get_msi_desc(irq);
308 __read_msi_msg(entry, msg);
311 void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
313 /* Assert that the cache is valid, assuming that
314 * valid messages are not all-zeroes. */
315 BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo |
321 void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
323 struct msi_desc *entry = irq_get_msi_desc(irq);
325 __get_cached_msi_msg(entry, msg);
328 void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
330 if (entry->dev->current_state != PCI_D0) {
331 /* Don't touch the hardware now */
332 } else if (entry->msi_attrib.is_msix) {
334 base = entry->mask_base +
335 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
337 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
338 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
339 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
341 struct pci_dev *dev = entry->dev;
342 int pos = dev->msi_cap;
345 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
346 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
347 msgctl |= entry->msi_attrib.multiple << 4;
348 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
350 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
352 if (entry->msi_attrib.is_64) {
353 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
355 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
358 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
365 void write_msi_msg(unsigned int irq, struct msi_msg *msg)
367 struct msi_desc *entry = irq_get_msi_desc(irq);
369 __write_msi_msg(entry, msg);
372 static void free_msi_irqs(struct pci_dev *dev)
374 struct msi_desc *entry, *tmp;
375 struct attribute **msi_attrs;
376 struct device_attribute *dev_attr;
379 list_for_each_entry(entry, &dev->msi_list, list) {
383 if (entry->nvec_used)
384 nvec = entry->nvec_used;
386 nvec = 1 << entry->msi_attrib.multiple;
387 for (i = 0; i < nvec; i++)
388 BUG_ON(irq_has_action(entry->irq + i));
391 arch_teardown_msi_irqs(dev);
393 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
394 if (entry->msi_attrib.is_msix) {
395 if (list_is_last(&entry->list, &dev->msi_list))
396 iounmap(entry->mask_base);
400 * Its possible that we get into this path
401 * When populate_msi_sysfs fails, which means the entries
402 * were not registered with sysfs. In that case don't
405 if (entry->kobj.parent) {
406 kobject_del(&entry->kobj);
407 kobject_put(&entry->kobj);
410 list_del(&entry->list);
414 if (dev->msi_irq_groups) {
415 sysfs_remove_groups(&dev->dev.kobj, dev->msi_irq_groups);
416 msi_attrs = dev->msi_irq_groups[0]->attrs;
417 while (msi_attrs[count]) {
418 dev_attr = container_of(msi_attrs[count],
419 struct device_attribute, attr);
420 kfree(dev_attr->attr.name);
425 kfree(dev->msi_irq_groups[0]);
426 kfree(dev->msi_irq_groups);
427 dev->msi_irq_groups = NULL;
431 static struct msi_desc *alloc_msi_entry(struct pci_dev *dev)
433 struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL);
437 INIT_LIST_HEAD(&desc->list);
443 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
445 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
446 pci_intx(dev, enable);
449 static void __pci_restore_msi_state(struct pci_dev *dev)
452 struct msi_desc *entry;
454 if (!dev->msi_enabled)
457 entry = irq_get_msi_desc(dev->irq);
459 pci_intx_for_msi(dev, 0);
460 msi_set_enable(dev, 0);
461 arch_restore_msi_irqs(dev);
463 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
464 msi_mask_irq(entry, msi_capable_mask(control), entry->masked);
465 control &= ~PCI_MSI_FLAGS_QSIZE;
466 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
467 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
470 static void __pci_restore_msix_state(struct pci_dev *dev)
472 struct msi_desc *entry;
475 if (!dev->msix_enabled)
477 BUG_ON(list_empty(&dev->msi_list));
478 entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
479 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
481 /* route the table */
482 pci_intx_for_msi(dev, 0);
483 control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL;
484 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
486 arch_restore_msi_irqs(dev);
487 list_for_each_entry(entry, &dev->msi_list, list) {
488 msix_mask_irq(entry, entry->masked);
491 control &= ~PCI_MSIX_FLAGS_MASKALL;
492 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
495 void pci_restore_msi_state(struct pci_dev *dev)
497 __pci_restore_msi_state(dev);
498 __pci_restore_msix_state(dev);
500 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
502 static ssize_t msi_mode_show(struct device *dev, struct device_attribute *attr,
505 struct pci_dev *pdev = to_pci_dev(dev);
506 struct msi_desc *entry;
510 retval = kstrtoul(attr->attr.name, 10, &irq);
514 list_for_each_entry(entry, &pdev->msi_list, list) {
515 if (entry->irq == irq) {
516 return sprintf(buf, "%s\n",
517 entry->msi_attrib.is_msix ? "msix" : "msi");
523 static int populate_msi_sysfs(struct pci_dev *pdev)
525 struct attribute **msi_attrs;
526 struct attribute *msi_attr;
527 struct device_attribute *msi_dev_attr;
528 struct attribute_group *msi_irq_group;
529 const struct attribute_group **msi_irq_groups;
530 struct msi_desc *entry;
535 /* Determine how many msi entries we have */
536 list_for_each_entry(entry, &pdev->msi_list, list) {
542 /* Dynamically create the MSI attributes for the PCI device */
543 msi_attrs = kzalloc(sizeof(void *) * (num_msi + 1), GFP_KERNEL);
546 list_for_each_entry(entry, &pdev->msi_list, list) {
547 char *name = kmalloc(20, GFP_KERNEL);
551 msi_dev_attr = kzalloc(sizeof(*msi_dev_attr), GFP_KERNEL);
557 sprintf(name, "%d", entry->irq);
558 sysfs_attr_init(&msi_dev_attr->attr);
559 msi_dev_attr->attr.name = name;
560 msi_dev_attr->attr.mode = S_IRUGO;
561 msi_dev_attr->show = msi_mode_show;
562 msi_attrs[count] = &msi_dev_attr->attr;
566 msi_irq_group = kzalloc(sizeof(*msi_irq_group), GFP_KERNEL);
569 msi_irq_group->name = "msi_irqs";
570 msi_irq_group->attrs = msi_attrs;
572 msi_irq_groups = kzalloc(sizeof(void *) * 2, GFP_KERNEL);
574 goto error_irq_group;
575 msi_irq_groups[0] = msi_irq_group;
577 ret = sysfs_create_groups(&pdev->dev.kobj, msi_irq_groups);
579 goto error_irq_groups;
580 pdev->msi_irq_groups = msi_irq_groups;
585 kfree(msi_irq_groups);
587 kfree(msi_irq_group);
590 msi_attr = msi_attrs[count];
592 msi_dev_attr = container_of(msi_attr, struct device_attribute, attr);
593 kfree(msi_attr->name);
596 msi_attr = msi_attrs[count];
603 * msi_capability_init - configure device's MSI capability structure
604 * @dev: pointer to the pci_dev data structure of MSI device function
605 * @nvec: number of interrupts to allocate
607 * Setup the MSI capability structure of the device with the requested
608 * number of interrupts. A return value of zero indicates the successful
609 * setup of an entry with the new MSI irq. A negative return value indicates
610 * an error, and a positive return value indicates the number of interrupts
611 * which could have been allocated.
613 static int msi_capability_init(struct pci_dev *dev, int nvec)
615 struct msi_desc *entry;
620 msi_set_enable(dev, 0); /* Disable MSI during set up */
622 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
623 /* MSI Entry Initialization */
624 entry = alloc_msi_entry(dev);
628 entry->msi_attrib.is_msix = 0;
629 entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
630 entry->msi_attrib.entry_nr = 0;
631 entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
632 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
633 entry->msi_attrib.pos = dev->msi_cap;
635 if (control & PCI_MSI_FLAGS_64BIT)
636 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
638 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
639 /* All MSIs are unmasked by default, Mask them all */
640 if (entry->msi_attrib.maskbit)
641 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
642 mask = msi_capable_mask(control);
643 msi_mask_irq(entry, mask, mask);
645 list_add_tail(&entry->list, &dev->msi_list);
647 /* Configure MSI capability structure */
648 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
650 msi_mask_irq(entry, mask, ~mask);
655 ret = populate_msi_sysfs(dev);
657 msi_mask_irq(entry, mask, ~mask);
662 /* Set MSI enabled bits */
663 pci_intx_for_msi(dev, 0);
664 msi_set_enable(dev, 1);
665 dev->msi_enabled = 1;
667 dev->irq = entry->irq;
671 static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
673 resource_size_t phys_addr;
677 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
679 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
680 table_offset &= PCI_MSIX_TABLE_OFFSET;
681 phys_addr = pci_resource_start(dev, bir) + table_offset;
683 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
686 static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
687 struct msix_entry *entries, int nvec)
689 struct msi_desc *entry;
692 for (i = 0; i < nvec; i++) {
693 entry = alloc_msi_entry(dev);
699 /* No enough memory. Don't try again */
703 entry->msi_attrib.is_msix = 1;
704 entry->msi_attrib.is_64 = 1;
705 entry->msi_attrib.entry_nr = entries[i].entry;
706 entry->msi_attrib.default_irq = dev->irq;
707 entry->msi_attrib.pos = dev->msix_cap;
708 entry->mask_base = base;
710 list_add_tail(&entry->list, &dev->msi_list);
716 static void msix_program_entries(struct pci_dev *dev,
717 struct msix_entry *entries)
719 struct msi_desc *entry;
722 list_for_each_entry(entry, &dev->msi_list, list) {
723 int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE +
724 PCI_MSIX_ENTRY_VECTOR_CTRL;
726 entries[i].vector = entry->irq;
727 irq_set_msi_desc(entry->irq, entry);
728 entry->masked = readl(entry->mask_base + offset);
729 msix_mask_irq(entry, 1);
735 * msix_capability_init - configure device's MSI-X capability
736 * @dev: pointer to the pci_dev data structure of MSI-X device function
737 * @entries: pointer to an array of struct msix_entry entries
738 * @nvec: number of @entries
740 * Setup the MSI-X capability structure of device function with a
741 * single MSI-X irq. A return of zero indicates the successful setup of
742 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
744 static int msix_capability_init(struct pci_dev *dev,
745 struct msix_entry *entries, int nvec)
751 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
753 /* Ensure MSI-X is disabled while it is set up */
754 control &= ~PCI_MSIX_FLAGS_ENABLE;
755 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
757 /* Request & Map MSI-X table region */
758 base = msix_map_region(dev, msix_table_size(control));
762 ret = msix_setup_entries(dev, base, entries, nvec);
766 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
771 * Some devices require MSI-X to be enabled before we can touch the
772 * MSI-X registers. We need to mask all the vectors to prevent
773 * interrupts coming in before they're fully set up.
775 control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE;
776 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
778 msix_program_entries(dev, entries);
780 ret = populate_msi_sysfs(dev);
784 /* Set MSI-X enabled bits and unmask the function */
785 pci_intx_for_msi(dev, 0);
786 dev->msix_enabled = 1;
788 control &= ~PCI_MSIX_FLAGS_MASKALL;
789 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
796 * If we had some success, report the number of irqs
797 * we succeeded in setting up.
799 struct msi_desc *entry;
802 list_for_each_entry(entry, &dev->msi_list, list) {
817 * pci_msi_check_device - check whether MSI may be enabled on a device
818 * @dev: pointer to the pci_dev data structure of MSI device function
819 * @nvec: how many MSIs have been requested ?
820 * @type: are we checking for MSI or MSI-X ?
822 * Look at global flags, the device itself, and its parent buses
823 * to determine if MSI/-X are supported for the device. If MSI/-X is
824 * supported return 0, else return an error code.
826 static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type)
831 /* MSI must be globally enabled and supported by the device */
832 if (!pci_msi_enable || !dev || dev->no_msi)
836 * You can't ask to have 0 or less MSIs configured.
838 * b) the list manipulation code assumes nvec >= 1.
844 * Any bridge which does NOT route MSI transactions from its
845 * secondary bus to its primary bus must set NO_MSI flag on
846 * the secondary pci_bus.
847 * We expect only arch-specific PCI host bus controller driver
848 * or quirks for specific PCI bridges to be setting NO_MSI.
850 for (bus = dev->bus; bus; bus = bus->parent)
851 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
854 ret = arch_msi_check_device(dev, nvec, type);
862 * pci_msi_vec_count - Return the number of MSI vectors a device can send
863 * @dev: device to report about
865 * This function returns the number of MSI vectors a device requested via
866 * Multiple Message Capable register. It returns a negative errno if the
867 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
868 * and returns a power of two, up to a maximum of 2^5 (32), according to the
871 int pci_msi_vec_count(struct pci_dev *dev)
879 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
880 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
884 EXPORT_SYMBOL(pci_msi_vec_count);
887 * pci_enable_msi_block - configure device's MSI capability structure
888 * @dev: device to configure
889 * @nvec: number of interrupts to configure
891 * Allocate IRQs for a device with the MSI capability.
892 * This function returns a negative errno if an error occurs. If it
893 * is unable to allocate the number of interrupts requested, it returns
894 * the number of interrupts it might be able to allocate. If it successfully
895 * allocates at least the number of interrupts requested, it returns 0 and
896 * updates the @dev's irq member to the lowest new interrupt number; the
897 * other interrupt numbers allocated to this device are consecutive.
899 int pci_enable_msi_block(struct pci_dev *dev, int nvec)
903 if (dev->current_state != PCI_D0)
906 maxvec = pci_msi_vec_count(dev);
912 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI);
916 WARN_ON(!!dev->msi_enabled);
918 /* Check whether driver already requested MSI-X irqs */
919 if (dev->msix_enabled) {
920 dev_info(&dev->dev, "can't enable MSI "
921 "(MSI-X already enabled)\n");
925 status = msi_capability_init(dev, nvec);
928 EXPORT_SYMBOL(pci_enable_msi_block);
930 void pci_msi_shutdown(struct pci_dev *dev)
932 struct msi_desc *desc;
936 if (!pci_msi_enable || !dev || !dev->msi_enabled)
939 BUG_ON(list_empty(&dev->msi_list));
940 desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
942 msi_set_enable(dev, 0);
943 pci_intx_for_msi(dev, 1);
944 dev->msi_enabled = 0;
946 /* Return the device with MSI unmasked as initial states */
947 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl);
948 mask = msi_capable_mask(ctrl);
949 /* Keep cached state to be restored */
950 arch_msi_mask_irq(desc, mask, ~mask);
952 /* Restore dev->irq to its default pin-assertion irq */
953 dev->irq = desc->msi_attrib.default_irq;
956 void pci_disable_msi(struct pci_dev *dev)
958 if (!pci_msi_enable || !dev || !dev->msi_enabled)
961 pci_msi_shutdown(dev);
964 EXPORT_SYMBOL(pci_disable_msi);
967 * pci_msix_vec_count - return the number of device's MSI-X table entries
968 * @dev: pointer to the pci_dev data structure of MSI-X device function
969 * This function returns the number of device's MSI-X table entries and
970 * therefore the number of MSI-X vectors device is capable of sending.
971 * It returns a negative errno if the device is not capable of sending MSI-X
974 int pci_msix_vec_count(struct pci_dev *dev)
981 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
982 return msix_table_size(control);
984 EXPORT_SYMBOL(pci_msix_vec_count);
987 * pci_enable_msix - configure device's MSI-X capability structure
988 * @dev: pointer to the pci_dev data structure of MSI-X device function
989 * @entries: pointer to an array of MSI-X entries
990 * @nvec: number of MSI-X irqs requested for allocation by device driver
992 * Setup the MSI-X capability structure of device function with the number
993 * of requested irqs upon its software driver call to request for
994 * MSI-X mode enabled on its hardware device function. A return of zero
995 * indicates the successful configuration of MSI-X capability structure
996 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
997 * Or a return of > 0 indicates that driver request is exceeding the number
998 * of irqs or MSI-X vectors available. Driver should use the returned value to
999 * re-send its request.
1001 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
1003 int status, nr_entries;
1006 if (!entries || !dev->msix_cap || dev->current_state != PCI_D0)
1009 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX);
1013 nr_entries = pci_msix_vec_count(dev);
1016 if (nvec > nr_entries)
1019 /* Check for any invalid entries */
1020 for (i = 0; i < nvec; i++) {
1021 if (entries[i].entry >= nr_entries)
1022 return -EINVAL; /* invalid entry */
1023 for (j = i + 1; j < nvec; j++) {
1024 if (entries[i].entry == entries[j].entry)
1025 return -EINVAL; /* duplicate entry */
1028 WARN_ON(!!dev->msix_enabled);
1030 /* Check whether driver already requested for MSI irq */
1031 if (dev->msi_enabled) {
1032 dev_info(&dev->dev, "can't enable MSI-X "
1033 "(MSI IRQ already assigned)\n");
1036 status = msix_capability_init(dev, entries, nvec);
1039 EXPORT_SYMBOL(pci_enable_msix);
1041 void pci_msix_shutdown(struct pci_dev *dev)
1043 struct msi_desc *entry;
1045 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1048 /* Return the device with MSI-X masked as initial states */
1049 list_for_each_entry(entry, &dev->msi_list, list) {
1050 /* Keep cached states to be restored */
1051 arch_msix_mask_irq(entry, 1);
1054 msix_set_enable(dev, 0);
1055 pci_intx_for_msi(dev, 1);
1056 dev->msix_enabled = 0;
1059 void pci_disable_msix(struct pci_dev *dev)
1061 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1064 pci_msix_shutdown(dev);
1067 EXPORT_SYMBOL(pci_disable_msix);
1070 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
1071 * @dev: pointer to the pci_dev data structure of MSI(X) device function
1073 * Being called during hotplug remove, from which the device function
1074 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
1075 * allocated for this device function, are reclaimed to unused state,
1076 * which may be used later on.
1078 void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1080 if (!pci_msi_enable || !dev)
1083 if (dev->msi_enabled || dev->msix_enabled)
1087 void pci_no_msi(void)
1093 * pci_msi_enabled - is MSI enabled?
1095 * Returns true if MSI has not been disabled by the command-line option
1098 int pci_msi_enabled(void)
1100 return pci_msi_enable;
1102 EXPORT_SYMBOL(pci_msi_enabled);
1104 void pci_msi_init_pci_dev(struct pci_dev *dev)
1106 INIT_LIST_HEAD(&dev->msi_list);
1108 /* Disable the msi hardware to avoid screaming interrupts
1109 * during boot. This is the power on reset default so
1110 * usually this should be a noop.
1112 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1114 msi_set_enable(dev, 0);
1116 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1118 msix_set_enable(dev, 0);
1122 * pci_enable_msi_range - configure device's MSI capability structure
1123 * @dev: device to configure
1124 * @minvec: minimal number of interrupts to configure
1125 * @maxvec: maximum number of interrupts to configure
1127 * This function tries to allocate a maximum possible number of interrupts in a
1128 * range between @minvec and @maxvec. It returns a negative errno if an error
1129 * occurs. If it succeeds, it returns the actual number of interrupts allocated
1130 * and updates the @dev's irq member to the lowest new interrupt number;
1131 * the other interrupt numbers allocated to this device are consecutive.
1133 int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec)
1138 if (maxvec < minvec)
1142 rc = pci_enable_msi_block(dev, nvec);
1145 } else if (rc > 0) {
1154 EXPORT_SYMBOL(pci_enable_msi_range);
1157 * pci_enable_msix_range - configure device's MSI-X capability structure
1158 * @dev: pointer to the pci_dev data structure of MSI-X device function
1159 * @entries: pointer to an array of MSI-X entries
1160 * @minvec: minimum number of MSI-X irqs requested
1161 * @maxvec: maximum number of MSI-X irqs requested
1163 * Setup the MSI-X capability structure of device function with a maximum
1164 * possible number of interrupts in the range between @minvec and @maxvec
1165 * upon its software driver call to request for MSI-X mode enabled on its
1166 * hardware device function. It returns a negative errno if an error occurs.
1167 * If it succeeds, it returns the actual number of interrupts allocated and
1168 * indicates the successful configuration of MSI-X capability structure
1169 * with new allocated MSI-X interrupts.
1171 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1172 int minvec, int maxvec)
1177 if (maxvec < minvec)
1181 rc = pci_enable_msix(dev, entries, nvec);
1184 } else if (rc > 0) {
1193 EXPORT_SYMBOL(pci_enable_msix_range);