1 // SPDX-License-Identifier: GPL-2.0
3 * PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 * Copyright (C) 2016 Christoph Hellwig.
10 #include <linux/err.h>
12 #include <linux/irq.h>
13 #include <linux/interrupt.h>
14 #include <linux/export.h>
15 #include <linux/ioport.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
18 #include <linux/msi.h>
19 #include <linux/smp.h>
20 #include <linux/errno.h>
22 #include <linux/acpi_iort.h>
23 #include <linux/slab.h>
24 #include <linux/irqdomain.h>
25 #include <linux/of_irq.h>
31 static int pci_msi_enable = 1;
32 int pci_msi_ignore_mask;
34 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
36 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
37 static int pci_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
39 struct irq_domain *domain;
41 domain = dev_get_msi_domain(&dev->dev);
42 if (domain && irq_domain_is_hierarchy(domain))
43 return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
45 return arch_setup_msi_irqs(dev, nvec, type);
48 static void pci_msi_teardown_msi_irqs(struct pci_dev *dev)
50 struct irq_domain *domain;
52 domain = dev_get_msi_domain(&dev->dev);
53 if (domain && irq_domain_is_hierarchy(domain))
54 msi_domain_free_irqs(domain, &dev->dev);
56 arch_teardown_msi_irqs(dev);
59 #define pci_msi_setup_msi_irqs arch_setup_msi_irqs
60 #define pci_msi_teardown_msi_irqs arch_teardown_msi_irqs
63 #ifdef CONFIG_PCI_MSI_ARCH_FALLBACKS
65 int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
70 void __weak arch_teardown_msi_irq(unsigned int irq)
74 int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
76 struct msi_desc *entry;
80 * If an architecture wants to support multiple MSI, it needs to
81 * override arch_setup_msi_irqs()
83 if (type == PCI_CAP_ID_MSI && nvec > 1)
86 for_each_pci_msi_entry(entry, dev) {
87 ret = arch_setup_msi_irq(dev, entry);
97 void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
100 struct msi_desc *entry;
102 for_each_pci_msi_entry(entry, dev)
104 for (i = 0; i < entry->nvec_used; i++)
105 arch_teardown_msi_irq(entry->irq + i);
107 #endif /* CONFIG_PCI_MSI_ARCH_FALLBACKS */
109 static void default_restore_msi_irq(struct pci_dev *dev, int irq)
111 struct msi_desc *entry;
114 if (dev->msix_enabled) {
115 for_each_pci_msi_entry(entry, dev) {
116 if (irq == entry->irq)
119 } else if (dev->msi_enabled) {
120 entry = irq_get_msi_desc(irq);
124 __pci_write_msi_msg(entry, &entry->msg);
127 void __weak arch_restore_msi_irqs(struct pci_dev *dev)
129 return default_restore_msi_irqs(dev);
133 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
134 * mask all MSI interrupts by clearing the MSI enable bit does not work
135 * reliably as devices without an INTx disable bit will then generate a
136 * level IRQ which will never be cleared.
138 static inline __attribute_const__ u32 msi_multi_mask(struct msi_desc *desc)
140 /* Don't shift by >= width of type */
141 if (desc->msi_attrib.multi_cap >= 5)
143 return (1 << (1 << desc->msi_attrib.multi_cap)) - 1;
146 static noinline void pci_msi_update_mask(struct msi_desc *desc, u32 clear, u32 set)
148 raw_spinlock_t *lock = &desc->dev->msi_lock;
151 if (!desc->msi_attrib.can_mask)
154 raw_spin_lock_irqsave(lock, flags);
155 desc->msi_mask &= ~clear;
156 desc->msi_mask |= set;
157 pci_write_config_dword(msi_desc_to_pci_dev(desc), desc->mask_pos,
159 raw_spin_unlock_irqrestore(lock, flags);
162 static inline void pci_msi_mask(struct msi_desc *desc, u32 mask)
164 pci_msi_update_mask(desc, 0, mask);
167 static inline void pci_msi_unmask(struct msi_desc *desc, u32 mask)
169 pci_msi_update_mask(desc, mask, 0);
172 static inline void __iomem *pci_msix_desc_addr(struct msi_desc *desc)
174 return desc->mask_base + desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
178 * This internal function does not flush PCI writes to the device. All
179 * users must ensure that they read from the device before either assuming
180 * that the device state is up to date, or returning out of this file.
181 * It does not affect the msi_desc::msix_ctrl cache either. Use with care!
183 static void pci_msix_write_vector_ctrl(struct msi_desc *desc, u32 ctrl)
185 void __iomem *desc_addr = pci_msix_desc_addr(desc);
187 if (desc->msi_attrib.can_mask)
188 writel(ctrl, desc_addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
191 static inline void pci_msix_mask(struct msi_desc *desc)
193 desc->msix_ctrl |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
194 pci_msix_write_vector_ctrl(desc, desc->msix_ctrl);
195 /* Flush write to device */
196 readl(desc->mask_base);
199 static inline void pci_msix_unmask(struct msi_desc *desc)
201 desc->msix_ctrl &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
202 pci_msix_write_vector_ctrl(desc, desc->msix_ctrl);
205 static void __pci_msi_mask_desc(struct msi_desc *desc, u32 mask)
207 if (desc->msi_attrib.is_msix)
210 pci_msi_mask(desc, mask);
213 static void __pci_msi_unmask_desc(struct msi_desc *desc, u32 mask)
215 if (desc->msi_attrib.is_msix)
216 pci_msix_unmask(desc);
218 pci_msi_unmask(desc, mask);
222 * pci_msi_mask_irq - Generic IRQ chip callback to mask PCI/MSI interrupts
223 * @data: pointer to irqdata associated to that interrupt
225 void pci_msi_mask_irq(struct irq_data *data)
227 struct msi_desc *desc = irq_data_get_msi_desc(data);
229 __pci_msi_mask_desc(desc, BIT(data->irq - desc->irq));
231 EXPORT_SYMBOL_GPL(pci_msi_mask_irq);
234 * pci_msi_unmask_irq - Generic IRQ chip callback to unmask PCI/MSI interrupts
235 * @data: pointer to irqdata associated to that interrupt
237 void pci_msi_unmask_irq(struct irq_data *data)
239 struct msi_desc *desc = irq_data_get_msi_desc(data);
241 __pci_msi_unmask_desc(desc, BIT(data->irq - desc->irq));
243 EXPORT_SYMBOL_GPL(pci_msi_unmask_irq);
245 void default_restore_msi_irqs(struct pci_dev *dev)
247 struct msi_desc *entry;
249 for_each_pci_msi_entry(entry, dev)
250 default_restore_msi_irq(dev, entry->irq);
253 void __pci_read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
255 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
257 BUG_ON(dev->current_state != PCI_D0);
259 if (entry->msi_attrib.is_msix) {
260 void __iomem *base = pci_msix_desc_addr(entry);
262 if (WARN_ON_ONCE(entry->msi_attrib.is_virtual))
265 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
266 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
267 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
269 int pos = dev->msi_cap;
272 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
274 if (entry->msi_attrib.is_64) {
275 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
277 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
280 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
286 void __pci_write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
288 struct pci_dev *dev = msi_desc_to_pci_dev(entry);
290 if (dev->current_state != PCI_D0 || pci_dev_is_disconnected(dev)) {
291 /* Don't touch the hardware now */
292 } else if (entry->msi_attrib.is_msix) {
293 void __iomem *base = pci_msix_desc_addr(entry);
294 u32 ctrl = entry->msix_ctrl;
295 bool unmasked = !(ctrl & PCI_MSIX_ENTRY_CTRL_MASKBIT);
297 if (entry->msi_attrib.is_virtual)
301 * The specification mandates that the entry is masked
302 * when the message is modified:
304 * "If software changes the Address or Data value of an
305 * entry while the entry is unmasked, the result is
309 pci_msix_write_vector_ctrl(entry, ctrl | PCI_MSIX_ENTRY_CTRL_MASKBIT);
311 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
312 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
313 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
316 pci_msix_write_vector_ctrl(entry, ctrl);
318 /* Ensure that the writes are visible in the device */
319 readl(base + PCI_MSIX_ENTRY_DATA);
321 int pos = dev->msi_cap;
324 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
325 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
326 msgctl |= entry->msi_attrib.multiple << 4;
327 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
329 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
331 if (entry->msi_attrib.is_64) {
332 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
334 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
337 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
340 /* Ensure that the writes are visible in the device */
341 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
347 if (entry->write_msi_msg)
348 entry->write_msi_msg(entry, entry->write_msi_msg_data);
352 void pci_write_msi_msg(unsigned int irq, struct msi_msg *msg)
354 struct msi_desc *entry = irq_get_msi_desc(irq);
356 __pci_write_msi_msg(entry, msg);
358 EXPORT_SYMBOL_GPL(pci_write_msi_msg);
360 static void free_msi_irqs(struct pci_dev *dev)
362 struct list_head *msi_list = dev_to_msi_list(&dev->dev);
363 struct msi_desc *entry, *tmp;
366 for_each_pci_msi_entry(entry, dev)
368 for (i = 0; i < entry->nvec_used; i++)
369 BUG_ON(irq_has_action(entry->irq + i));
371 if (dev->msi_irq_groups) {
372 msi_destroy_sysfs(&dev->dev, dev->msi_irq_groups);
373 dev->msi_irq_groups = NULL;
376 pci_msi_teardown_msi_irqs(dev);
378 list_for_each_entry_safe(entry, tmp, msi_list, list) {
379 if (entry->msi_attrib.is_msix) {
380 if (list_is_last(&entry->list, msi_list))
381 iounmap(entry->mask_base);
384 list_del(&entry->list);
385 free_msi_entry(entry);
389 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
391 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
392 pci_intx(dev, enable);
395 static void pci_msi_set_enable(struct pci_dev *dev, int enable)
399 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
400 control &= ~PCI_MSI_FLAGS_ENABLE;
402 control |= PCI_MSI_FLAGS_ENABLE;
403 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
406 static void __pci_restore_msi_state(struct pci_dev *dev)
409 struct msi_desc *entry;
411 if (!dev->msi_enabled)
414 entry = irq_get_msi_desc(dev->irq);
416 pci_intx_for_msi(dev, 0);
417 pci_msi_set_enable(dev, 0);
418 arch_restore_msi_irqs(dev);
420 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
421 pci_msi_update_mask(entry, 0, 0);
422 control &= ~PCI_MSI_FLAGS_QSIZE;
423 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
424 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
427 static void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
431 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
434 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
437 static void __pci_restore_msix_state(struct pci_dev *dev)
439 struct msi_desc *entry;
441 if (!dev->msix_enabled)
443 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
445 /* route the table */
446 pci_intx_for_msi(dev, 0);
447 pci_msix_clear_and_set_ctrl(dev, 0,
448 PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL);
450 arch_restore_msi_irqs(dev);
451 for_each_pci_msi_entry(entry, dev)
452 pci_msix_write_vector_ctrl(entry, entry->msix_ctrl);
454 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
457 void pci_restore_msi_state(struct pci_dev *dev)
459 __pci_restore_msi_state(dev);
460 __pci_restore_msix_state(dev);
462 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
464 static struct msi_desc *
465 msi_setup_entry(struct pci_dev *dev, int nvec, struct irq_affinity *affd)
467 struct irq_affinity_desc *masks = NULL;
468 struct msi_desc *entry;
472 masks = irq_create_affinity_masks(nvec, affd);
474 /* MSI Entry Initialization */
475 entry = alloc_msi_entry(&dev->dev, nvec, masks);
479 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
480 /* Lies, damned lies, and MSIs */
481 if (dev->dev_flags & PCI_DEV_FLAGS_HAS_MSI_MASKING)
482 control |= PCI_MSI_FLAGS_MASKBIT;
484 entry->msi_attrib.is_msix = 0;
485 entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
486 entry->msi_attrib.is_virtual = 0;
487 entry->msi_attrib.entry_nr = 0;
488 entry->msi_attrib.can_mask = !pci_msi_ignore_mask &&
489 !!(control & PCI_MSI_FLAGS_MASKBIT);
490 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
491 entry->msi_attrib.multi_cap = (control & PCI_MSI_FLAGS_QMASK) >> 1;
492 entry->msi_attrib.multiple = ilog2(__roundup_pow_of_two(nvec));
494 if (control & PCI_MSI_FLAGS_64BIT)
495 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
497 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
499 /* Save the initial mask status */
500 if (entry->msi_attrib.can_mask)
501 pci_read_config_dword(dev, entry->mask_pos, &entry->msi_mask);
508 static int msi_verify_entries(struct pci_dev *dev)
510 struct msi_desc *entry;
512 if (!dev->no_64bit_msi)
515 for_each_pci_msi_entry(entry, dev) {
516 if (entry->msg.address_hi) {
517 pci_err(dev, "arch assigned 64-bit MSI address %#x%08x but device only supports 32 bits\n",
518 entry->msg.address_hi, entry->msg.address_lo);
526 * msi_capability_init - configure device's MSI capability structure
527 * @dev: pointer to the pci_dev data structure of MSI device function
528 * @nvec: number of interrupts to allocate
529 * @affd: description of automatic IRQ affinity assignments (may be %NULL)
531 * Setup the MSI capability structure of the device with the requested
532 * number of interrupts. A return value of zero indicates the successful
533 * setup of an entry with the new MSI IRQ. A negative return value indicates
534 * an error, and a positive return value indicates the number of interrupts
535 * which could have been allocated.
537 static int msi_capability_init(struct pci_dev *dev, int nvec,
538 struct irq_affinity *affd)
540 const struct attribute_group **groups;
541 struct msi_desc *entry;
544 pci_msi_set_enable(dev, 0); /* Disable MSI during set up */
546 entry = msi_setup_entry(dev, nvec, affd);
550 /* All MSIs are unmasked by default; mask them all */
551 pci_msi_mask(entry, msi_multi_mask(entry));
553 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
555 /* Configure MSI capability structure */
556 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
560 ret = msi_verify_entries(dev);
564 groups = msi_populate_sysfs(&dev->dev);
565 if (IS_ERR(groups)) {
566 ret = PTR_ERR(groups);
570 dev->msi_irq_groups = groups;
572 /* Set MSI enabled bits */
573 pci_intx_for_msi(dev, 0);
574 pci_msi_set_enable(dev, 1);
575 dev->msi_enabled = 1;
577 pcibios_free_irq(dev);
578 dev->irq = entry->irq;
582 pci_msi_unmask(entry, msi_multi_mask(entry));
587 static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
589 resource_size_t phys_addr;
594 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
596 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
597 flags = pci_resource_flags(dev, bir);
598 if (!flags || (flags & IORESOURCE_UNSET))
601 table_offset &= PCI_MSIX_TABLE_OFFSET;
602 phys_addr = pci_resource_start(dev, bir) + table_offset;
604 return ioremap(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
607 static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
608 struct msix_entry *entries, int nvec,
609 struct irq_affinity *affd)
611 struct irq_affinity_desc *curmsk, *masks = NULL;
612 struct msi_desc *entry;
615 int vec_count = pci_msix_vec_count(dev);
618 masks = irq_create_affinity_masks(nvec, affd);
620 for (i = 0, curmsk = masks; i < nvec; i++) {
621 entry = alloc_msi_entry(&dev->dev, 1, curmsk);
627 /* No enough memory. Don't try again */
632 entry->msi_attrib.is_msix = 1;
633 entry->msi_attrib.is_64 = 1;
636 entry->msi_attrib.entry_nr = entries[i].entry;
638 entry->msi_attrib.entry_nr = i;
640 entry->msi_attrib.is_virtual =
641 entry->msi_attrib.entry_nr >= vec_count;
643 entry->msi_attrib.can_mask = !pci_msi_ignore_mask &&
644 !entry->msi_attrib.is_virtual;
646 entry->msi_attrib.default_irq = dev->irq;
647 entry->mask_base = base;
649 if (entry->msi_attrib.can_mask) {
650 addr = pci_msix_desc_addr(entry);
651 entry->msix_ctrl = readl(addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
654 list_add_tail(&entry->list, dev_to_msi_list(&dev->dev));
664 static void msix_update_entries(struct pci_dev *dev, struct msix_entry *entries)
666 struct msi_desc *entry;
668 for_each_pci_msi_entry(entry, dev) {
670 entries->vector = entry->irq;
676 static void msix_mask_all(void __iomem *base, int tsize)
678 u32 ctrl = PCI_MSIX_ENTRY_CTRL_MASKBIT;
681 if (pci_msi_ignore_mask)
684 for (i = 0; i < tsize; i++, base += PCI_MSIX_ENTRY_SIZE)
685 writel(ctrl, base + PCI_MSIX_ENTRY_VECTOR_CTRL);
689 * msix_capability_init - configure device's MSI-X capability
690 * @dev: pointer to the pci_dev data structure of MSI-X device function
691 * @entries: pointer to an array of struct msix_entry entries
692 * @nvec: number of @entries
693 * @affd: Optional pointer to enable automatic affinity assignment
695 * Setup the MSI-X capability structure of device function with a
696 * single MSI-X IRQ. A return of zero indicates the successful setup of
697 * requested MSI-X entries with allocated IRQs or non-zero for otherwise.
699 static int msix_capability_init(struct pci_dev *dev, struct msix_entry *entries,
700 int nvec, struct irq_affinity *affd)
702 const struct attribute_group **groups;
708 * Some devices require MSI-X to be enabled before the MSI-X
709 * registers can be accessed. Mask all the vectors to prevent
710 * interrupts coming in before they're fully set up.
712 pci_msix_clear_and_set_ctrl(dev, 0, PCI_MSIX_FLAGS_MASKALL |
713 PCI_MSIX_FLAGS_ENABLE);
715 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
716 /* Request & Map MSI-X table region */
717 tsize = msix_table_size(control);
718 base = msix_map_region(dev, tsize);
724 ret = msix_setup_entries(dev, base, entries, nvec, affd);
728 ret = pci_msi_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
732 /* Check if all MSI entries honor device restrictions */
733 ret = msi_verify_entries(dev);
737 msix_update_entries(dev, entries);
739 groups = msi_populate_sysfs(&dev->dev);
740 if (IS_ERR(groups)) {
741 ret = PTR_ERR(groups);
745 dev->msi_irq_groups = groups;
747 /* Set MSI-X enabled bits and unmask the function */
748 pci_intx_for_msi(dev, 0);
749 dev->msix_enabled = 1;
752 * Ensure that all table entries are masked to prevent
753 * stale entries from firing in a crash kernel.
755 * Done late to deal with a broken Marvell NVME device
756 * which takes the MSI-X mask bits into account even
757 * when MSI-X is disabled, which prevents MSI delivery.
759 msix_mask_all(base, tsize);
760 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0);
762 pcibios_free_irq(dev);
768 * If we had some success, report the number of IRQs
769 * we succeeded in setting up.
771 struct msi_desc *entry;
774 for_each_pci_msi_entry(entry, dev) {
786 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE, 0);
792 * pci_msi_supported - check whether MSI may be enabled on a device
793 * @dev: pointer to the pci_dev data structure of MSI device function
794 * @nvec: how many MSIs have been requested?
796 * Look at global flags, the device itself, and its parent buses
797 * to determine if MSI/-X are supported for the device. If MSI/-X is
798 * supported return 1, else return 0.
800 static int pci_msi_supported(struct pci_dev *dev, int nvec)
804 /* MSI must be globally enabled and supported by the device */
808 if (!dev || dev->no_msi)
812 * You can't ask to have 0 or less MSIs configured.
814 * b) the list manipulation code assumes nvec >= 1.
820 * Any bridge which does NOT route MSI transactions from its
821 * secondary bus to its primary bus must set NO_MSI flag on
822 * the secondary pci_bus.
824 * The NO_MSI flag can either be set directly by:
825 * - arch-specific PCI host bus controller drivers (deprecated)
826 * - quirks for specific PCI bridges
828 * or indirectly by platform-specific PCI host bridge drivers by
829 * advertising the 'msi_domain' property, which results in
830 * the NO_MSI flag when no MSI domain is found for this bridge
833 for (bus = dev->bus; bus; bus = bus->parent)
834 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
841 * pci_msi_vec_count - Return the number of MSI vectors a device can send
842 * @dev: device to report about
844 * This function returns the number of MSI vectors a device requested via
845 * Multiple Message Capable register. It returns a negative errno if the
846 * device is not capable sending MSI interrupts. Otherwise, the call succeeds
847 * and returns a power of two, up to a maximum of 2^5 (32), according to the
850 int pci_msi_vec_count(struct pci_dev *dev)
858 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
859 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
863 EXPORT_SYMBOL(pci_msi_vec_count);
865 static void pci_msi_shutdown(struct pci_dev *dev)
867 struct msi_desc *desc;
869 if (!pci_msi_enable || !dev || !dev->msi_enabled)
872 BUG_ON(list_empty(dev_to_msi_list(&dev->dev)));
873 desc = first_pci_msi_entry(dev);
875 pci_msi_set_enable(dev, 0);
876 pci_intx_for_msi(dev, 1);
877 dev->msi_enabled = 0;
879 /* Return the device with MSI unmasked as initial states */
880 pci_msi_unmask(desc, msi_multi_mask(desc));
882 /* Restore dev->irq to its default pin-assertion IRQ */
883 dev->irq = desc->msi_attrib.default_irq;
884 pcibios_alloc_irq(dev);
887 void pci_disable_msi(struct pci_dev *dev)
889 if (!pci_msi_enable || !dev || !dev->msi_enabled)
892 pci_msi_shutdown(dev);
895 EXPORT_SYMBOL(pci_disable_msi);
898 * pci_msix_vec_count - return the number of device's MSI-X table entries
899 * @dev: pointer to the pci_dev data structure of MSI-X device function
900 * This function returns the number of device's MSI-X table entries and
901 * therefore the number of MSI-X vectors device is capable of sending.
902 * It returns a negative errno if the device is not capable of sending MSI-X
905 int pci_msix_vec_count(struct pci_dev *dev)
912 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
913 return msix_table_size(control);
915 EXPORT_SYMBOL(pci_msix_vec_count);
917 static int __pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries,
918 int nvec, struct irq_affinity *affd, int flags)
923 if (!pci_msi_supported(dev, nvec) || dev->current_state != PCI_D0)
926 nr_entries = pci_msix_vec_count(dev);
929 if (nvec > nr_entries && !(flags & PCI_IRQ_VIRTUAL))
933 /* Check for any invalid entries */
934 for (i = 0; i < nvec; i++) {
935 if (entries[i].entry >= nr_entries)
936 return -EINVAL; /* invalid entry */
937 for (j = i + 1; j < nvec; j++) {
938 if (entries[i].entry == entries[j].entry)
939 return -EINVAL; /* duplicate entry */
944 /* Check whether driver already requested for MSI IRQ */
945 if (dev->msi_enabled) {
946 pci_info(dev, "can't enable MSI-X (MSI IRQ already assigned)\n");
949 return msix_capability_init(dev, entries, nvec, affd);
952 static void pci_msix_shutdown(struct pci_dev *dev)
954 struct msi_desc *entry;
956 if (!pci_msi_enable || !dev || !dev->msix_enabled)
959 if (pci_dev_is_disconnected(dev)) {
960 dev->msix_enabled = 0;
964 /* Return the device with MSI-X masked as initial states */
965 for_each_pci_msi_entry(entry, dev)
966 pci_msix_mask(entry);
968 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
969 pci_intx_for_msi(dev, 1);
970 dev->msix_enabled = 0;
971 pcibios_alloc_irq(dev);
974 void pci_disable_msix(struct pci_dev *dev)
976 if (!pci_msi_enable || !dev || !dev->msix_enabled)
979 pci_msix_shutdown(dev);
982 EXPORT_SYMBOL(pci_disable_msix);
984 void pci_no_msi(void)
990 * pci_msi_enabled - is MSI enabled?
992 * Returns true if MSI has not been disabled by the command-line option
995 int pci_msi_enabled(void)
997 return pci_msi_enable;
999 EXPORT_SYMBOL(pci_msi_enabled);
1001 static int __pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec,
1002 struct irq_affinity *affd)
1007 if (!pci_msi_supported(dev, minvec) || dev->current_state != PCI_D0)
1010 /* Check whether driver already requested MSI-X IRQs */
1011 if (dev->msix_enabled) {
1012 pci_info(dev, "can't enable MSI (MSI-X already enabled)\n");
1016 if (maxvec < minvec)
1019 if (WARN_ON_ONCE(dev->msi_enabled))
1022 nvec = pci_msi_vec_count(dev);
1033 nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
1038 rc = msi_capability_init(dev, nvec, affd);
1051 /* deprecated, don't use */
1052 int pci_enable_msi(struct pci_dev *dev)
1054 int rc = __pci_enable_msi_range(dev, 1, 1, NULL);
1059 EXPORT_SYMBOL(pci_enable_msi);
1061 static int __pci_enable_msix_range(struct pci_dev *dev,
1062 struct msix_entry *entries, int minvec,
1063 int maxvec, struct irq_affinity *affd,
1066 int rc, nvec = maxvec;
1068 if (maxvec < minvec)
1071 if (WARN_ON_ONCE(dev->msix_enabled))
1076 nvec = irq_calc_affinity_vectors(minvec, nvec, affd);
1081 rc = __pci_enable_msix(dev, entries, nvec, affd, flags);
1095 * pci_enable_msix_range - configure device's MSI-X capability structure
1096 * @dev: pointer to the pci_dev data structure of MSI-X device function
1097 * @entries: pointer to an array of MSI-X entries
1098 * @minvec: minimum number of MSI-X IRQs requested
1099 * @maxvec: maximum number of MSI-X IRQs requested
1101 * Setup the MSI-X capability structure of device function with a maximum
1102 * possible number of interrupts in the range between @minvec and @maxvec
1103 * upon its software driver call to request for MSI-X mode enabled on its
1104 * hardware device function. It returns a negative errno if an error occurs.
1105 * If it succeeds, it returns the actual number of interrupts allocated and
1106 * indicates the successful configuration of MSI-X capability structure
1107 * with new allocated MSI-X interrupts.
1109 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1110 int minvec, int maxvec)
1112 return __pci_enable_msix_range(dev, entries, minvec, maxvec, NULL, 0);
1114 EXPORT_SYMBOL(pci_enable_msix_range);
1117 * pci_alloc_irq_vectors_affinity - allocate multiple IRQs for a device
1118 * @dev: PCI device to operate on
1119 * @min_vecs: minimum number of vectors required (must be >= 1)
1120 * @max_vecs: maximum (desired) number of vectors
1121 * @flags: flags or quirks for the allocation
1122 * @affd: optional description of the affinity requirements
1124 * Allocate up to @max_vecs interrupt vectors for @dev, using MSI-X or MSI
1125 * vectors if available, and fall back to a single legacy vector
1126 * if neither is available. Return the number of vectors allocated,
1127 * (which might be smaller than @max_vecs) if successful, or a negative
1128 * error code on error. If less than @min_vecs interrupt vectors are
1129 * available for @dev the function will fail with -ENOSPC.
1131 * To get the Linux IRQ number used for a vector that can be passed to
1132 * request_irq() use the pci_irq_vector() helper.
1134 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1135 unsigned int max_vecs, unsigned int flags,
1136 struct irq_affinity *affd)
1138 struct irq_affinity msi_default_affd = {0};
1139 int nvecs = -ENOSPC;
1141 if (flags & PCI_IRQ_AFFINITY) {
1143 affd = &msi_default_affd;
1149 if (flags & PCI_IRQ_MSIX) {
1150 nvecs = __pci_enable_msix_range(dev, NULL, min_vecs, max_vecs,
1156 if (flags & PCI_IRQ_MSI) {
1157 nvecs = __pci_enable_msi_range(dev, min_vecs, max_vecs, affd);
1162 /* use legacy IRQ if allowed */
1163 if (flags & PCI_IRQ_LEGACY) {
1164 if (min_vecs == 1 && dev->irq) {
1166 * Invoke the affinity spreading logic to ensure that
1167 * the device driver can adjust queue configuration
1168 * for the single interrupt case.
1171 irq_create_affinity_masks(1, affd);
1179 EXPORT_SYMBOL(pci_alloc_irq_vectors_affinity);
1182 * pci_free_irq_vectors - free previously allocated IRQs for a device
1183 * @dev: PCI device to operate on
1185 * Undoes the allocations and enabling in pci_alloc_irq_vectors().
1187 void pci_free_irq_vectors(struct pci_dev *dev)
1189 pci_disable_msix(dev);
1190 pci_disable_msi(dev);
1192 EXPORT_SYMBOL(pci_free_irq_vectors);
1195 * pci_irq_vector - return Linux IRQ number of a device vector
1196 * @dev: PCI device to operate on
1197 * @nr: Interrupt vector index (0-based)
1199 * @nr has the following meanings depending on the interrupt mode:
1200 * MSI-X: The index in the MSI-X vector table
1201 * MSI: The index of the enabled MSI vectors
1204 * Return: The Linux interrupt number or -EINVAl if @nr is out of range.
1206 int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1208 if (dev->msix_enabled) {
1209 struct msi_desc *entry;
1211 for_each_pci_msi_entry(entry, dev) {
1212 if (entry->msi_attrib.entry_nr == nr)
1219 if (dev->msi_enabled) {
1220 struct msi_desc *entry = first_pci_msi_entry(dev);
1222 if (WARN_ON_ONCE(nr >= entry->nvec_used))
1225 if (WARN_ON_ONCE(nr > 0))
1229 return dev->irq + nr;
1231 EXPORT_SYMBOL(pci_irq_vector);
1234 * pci_irq_get_affinity - return the affinity of a particular MSI vector
1235 * @dev: PCI device to operate on
1236 * @nr: device-relative interrupt vector index (0-based).
1238 * @nr has the following meanings depending on the interrupt mode:
1239 * MSI-X: The index in the MSI-X vector table
1240 * MSI: The index of the enabled MSI vectors
1243 * Return: A cpumask pointer or NULL if @nr is out of range
1245 const struct cpumask *pci_irq_get_affinity(struct pci_dev *dev, int nr)
1247 if (dev->msix_enabled) {
1248 struct msi_desc *entry;
1250 for_each_pci_msi_entry(entry, dev) {
1251 if (entry->msi_attrib.entry_nr == nr)
1252 return &entry->affinity->mask;
1256 } else if (dev->msi_enabled) {
1257 struct msi_desc *entry = first_pci_msi_entry(dev);
1259 if (WARN_ON_ONCE(!entry || !entry->affinity ||
1260 nr >= entry->nvec_used))
1263 return &entry->affinity[nr].mask;
1265 return cpu_possible_mask;
1268 EXPORT_SYMBOL(pci_irq_get_affinity);
1270 struct pci_dev *msi_desc_to_pci_dev(struct msi_desc *desc)
1272 return to_pci_dev(desc->dev);
1274 EXPORT_SYMBOL(msi_desc_to_pci_dev);
1276 void *msi_desc_to_pci_sysdata(struct msi_desc *desc)
1278 struct pci_dev *dev = msi_desc_to_pci_dev(desc);
1280 return dev->bus->sysdata;
1282 EXPORT_SYMBOL_GPL(msi_desc_to_pci_sysdata);
1284 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
1286 * pci_msi_domain_write_msg - Helper to write MSI message to PCI config space
1287 * @irq_data: Pointer to interrupt data of the MSI interrupt
1288 * @msg: Pointer to the message
1290 void pci_msi_domain_write_msg(struct irq_data *irq_data, struct msi_msg *msg)
1292 struct msi_desc *desc = irq_data_get_msi_desc(irq_data);
1295 * For MSI-X desc->irq is always equal to irq_data->irq. For
1296 * MSI only the first interrupt of MULTI MSI passes the test.
1298 if (desc->irq == irq_data->irq)
1299 __pci_write_msi_msg(desc, msg);
1303 * pci_msi_domain_calc_hwirq - Generate a unique ID for an MSI source
1304 * @desc: Pointer to the MSI descriptor
1306 * The ID number is only used within the irqdomain.
1308 static irq_hw_number_t pci_msi_domain_calc_hwirq(struct msi_desc *desc)
1310 struct pci_dev *dev = msi_desc_to_pci_dev(desc);
1312 return (irq_hw_number_t)desc->msi_attrib.entry_nr |
1313 pci_dev_id(dev) << 11 |
1314 (pci_domain_nr(dev->bus) & 0xFFFFFFFF) << 27;
1317 static inline bool pci_msi_desc_is_multi_msi(struct msi_desc *desc)
1319 return !desc->msi_attrib.is_msix && desc->nvec_used > 1;
1323 * pci_msi_domain_check_cap - Verify that @domain supports the capabilities
1325 * @domain: The interrupt domain to check
1326 * @info: The domain info for verification
1327 * @dev: The device to check
1330 * 0 if the functionality is supported
1331 * 1 if Multi MSI is requested, but the domain does not support it
1332 * -ENOTSUPP otherwise
1334 int pci_msi_domain_check_cap(struct irq_domain *domain,
1335 struct msi_domain_info *info, struct device *dev)
1337 struct msi_desc *desc = first_pci_msi_entry(to_pci_dev(dev));
1339 /* Special handling to support __pci_enable_msi_range() */
1340 if (pci_msi_desc_is_multi_msi(desc) &&
1341 !(info->flags & MSI_FLAG_MULTI_PCI_MSI))
1343 else if (desc->msi_attrib.is_msix && !(info->flags & MSI_FLAG_PCI_MSIX))
1349 static int pci_msi_domain_handle_error(struct irq_domain *domain,
1350 struct msi_desc *desc, int error)
1352 /* Special handling to support __pci_enable_msi_range() */
1353 if (pci_msi_desc_is_multi_msi(desc) && error == -ENOSPC)
1359 static void pci_msi_domain_set_desc(msi_alloc_info_t *arg,
1360 struct msi_desc *desc)
1363 arg->hwirq = pci_msi_domain_calc_hwirq(desc);
1366 static struct msi_domain_ops pci_msi_domain_ops_default = {
1367 .set_desc = pci_msi_domain_set_desc,
1368 .msi_check = pci_msi_domain_check_cap,
1369 .handle_error = pci_msi_domain_handle_error,
1372 static void pci_msi_domain_update_dom_ops(struct msi_domain_info *info)
1374 struct msi_domain_ops *ops = info->ops;
1377 info->ops = &pci_msi_domain_ops_default;
1379 if (ops->set_desc == NULL)
1380 ops->set_desc = pci_msi_domain_set_desc;
1381 if (ops->msi_check == NULL)
1382 ops->msi_check = pci_msi_domain_check_cap;
1383 if (ops->handle_error == NULL)
1384 ops->handle_error = pci_msi_domain_handle_error;
1388 static void pci_msi_domain_update_chip_ops(struct msi_domain_info *info)
1390 struct irq_chip *chip = info->chip;
1393 if (!chip->irq_write_msi_msg)
1394 chip->irq_write_msi_msg = pci_msi_domain_write_msg;
1395 if (!chip->irq_mask)
1396 chip->irq_mask = pci_msi_mask_irq;
1397 if (!chip->irq_unmask)
1398 chip->irq_unmask = pci_msi_unmask_irq;
1402 * pci_msi_create_irq_domain - Create a MSI interrupt domain
1403 * @fwnode: Optional fwnode of the interrupt controller
1404 * @info: MSI domain info
1405 * @parent: Parent irq domain
1407 * Updates the domain and chip ops and creates a MSI interrupt domain.
1410 * A domain pointer or NULL in case of failure.
1412 struct irq_domain *pci_msi_create_irq_domain(struct fwnode_handle *fwnode,
1413 struct msi_domain_info *info,
1414 struct irq_domain *parent)
1416 struct irq_domain *domain;
1418 if (WARN_ON(info->flags & MSI_FLAG_LEVEL_CAPABLE))
1419 info->flags &= ~MSI_FLAG_LEVEL_CAPABLE;
1421 if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
1422 pci_msi_domain_update_dom_ops(info);
1423 if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
1424 pci_msi_domain_update_chip_ops(info);
1426 info->flags |= MSI_FLAG_ACTIVATE_EARLY;
1427 if (IS_ENABLED(CONFIG_GENERIC_IRQ_RESERVATION_MODE))
1428 info->flags |= MSI_FLAG_MUST_REACTIVATE;
1430 /* PCI-MSI is oneshot-safe */
1431 info->chip->flags |= IRQCHIP_ONESHOT_SAFE;
1433 domain = msi_create_irq_domain(fwnode, info, parent);
1437 irq_domain_update_bus_token(domain, DOMAIN_BUS_PCI_MSI);
1440 EXPORT_SYMBOL_GPL(pci_msi_create_irq_domain);
1443 * Users of the generic MSI infrastructure expect a device to have a single ID,
1444 * so with DMA aliases we have to pick the least-worst compromise. Devices with
1445 * DMA phantom functions tend to still emit MSIs from the real function number,
1446 * so we ignore those and only consider topological aliases where either the
1447 * alias device or RID appears on a different bus number. We also make the
1448 * reasonable assumption that bridges are walked in an upstream direction (so
1449 * the last one seen wins), and the much braver assumption that the most likely
1450 * case is that of PCI->PCIe so we should always use the alias RID. This echoes
1451 * the logic from intel_irq_remapping's set_msi_sid(), which presumably works
1452 * well enough in practice; in the face of the horrible PCIe<->PCI-X conditions
1453 * for taking ownership all we can really do is close our eyes and hope...
1455 static int get_msi_id_cb(struct pci_dev *pdev, u16 alias, void *data)
1458 u8 bus = PCI_BUS_NUM(*pa);
1460 if (pdev->bus->number != bus || PCI_BUS_NUM(alias) != bus)
1467 * pci_msi_domain_get_msi_rid - Get the MSI requester id (RID)
1468 * @domain: The interrupt domain
1469 * @pdev: The PCI device.
1471 * The RID for a device is formed from the alias, with a firmware
1472 * supplied mapping applied
1476 u32 pci_msi_domain_get_msi_rid(struct irq_domain *domain, struct pci_dev *pdev)
1478 struct device_node *of_node;
1479 u32 rid = pci_dev_id(pdev);
1481 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1483 of_node = irq_domain_get_of_node(domain);
1484 rid = of_node ? of_msi_map_id(&pdev->dev, of_node, rid) :
1485 iort_msi_map_id(&pdev->dev, rid);
1491 * pci_msi_get_device_domain - Get the MSI domain for a given PCI device
1492 * @pdev: The PCI device
1494 * Use the firmware data to find a device-specific MSI domain
1495 * (i.e. not one that is set as a default).
1497 * Returns: The corresponding MSI domain or NULL if none has been found.
1499 struct irq_domain *pci_msi_get_device_domain(struct pci_dev *pdev)
1501 struct irq_domain *dom;
1502 u32 rid = pci_dev_id(pdev);
1504 pci_for_each_dma_alias(pdev, get_msi_id_cb, &rid);
1505 dom = of_msi_map_get_device_domain(&pdev->dev, rid, DOMAIN_BUS_PCI_MSI);
1507 dom = iort_get_device_domain(&pdev->dev, rid,
1508 DOMAIN_BUS_PCI_MSI);
1513 * pci_dev_has_special_msi_domain - Check whether the device is handled by
1514 * a non-standard PCI-MSI domain
1515 * @pdev: The PCI device to check.
1517 * Returns: True if the device irqdomain or the bus irqdomain is
1518 * non-standard PCI/MSI.
1520 bool pci_dev_has_special_msi_domain(struct pci_dev *pdev)
1522 struct irq_domain *dom = dev_get_msi_domain(&pdev->dev);
1525 dom = dev_get_msi_domain(&pdev->bus->dev);
1530 return dom->bus_token != DOMAIN_BUS_PCI_MSI;
1533 #endif /* CONFIG_PCI_MSI_IRQ_DOMAIN */
1534 #endif /* CONFIG_PCI_MSI */
1536 void pci_msi_init(struct pci_dev *dev)
1541 * Disable the MSI hardware to avoid screaming interrupts
1542 * during boot. This is the power on reset default so
1543 * usually this should be a noop.
1545 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1549 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl);
1550 if (ctrl & PCI_MSI_FLAGS_ENABLE)
1551 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS,
1552 ctrl & ~PCI_MSI_FLAGS_ENABLE);
1554 if (!(ctrl & PCI_MSI_FLAGS_64BIT))
1555 dev->no_64bit_msi = 1;
1558 void pci_msix_init(struct pci_dev *dev)
1562 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1566 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
1567 if (ctrl & PCI_MSIX_FLAGS_ENABLE)
1568 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS,
1569 ctrl & ~PCI_MSIX_FLAGS_ENABLE);