3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/init.h>
14 #include <linux/export.h>
15 #include <linux/ioport.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
18 #include <linux/msi.h>
19 #include <linux/smp.h>
20 #include <linux/errno.h>
22 #include <linux/slab.h>
26 static int pci_msi_enable = 1;
28 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
33 int __weak arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
35 struct msi_chip *chip = dev->bus->msi;
38 if (!chip || !chip->setup_irq)
41 err = chip->setup_irq(chip, dev, desc);
45 irq_set_chip_data(desc->irq, chip);
50 void __weak arch_teardown_msi_irq(unsigned int irq)
52 struct msi_chip *chip = irq_get_chip_data(irq);
54 if (!chip || !chip->teardown_irq)
57 chip->teardown_irq(chip, irq);
60 int __weak arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
62 struct msi_chip *chip = dev->bus->msi;
64 if (!chip || !chip->check_device)
67 return chip->check_device(chip, dev, nvec, type);
70 int __weak arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
72 struct msi_desc *entry;
76 * If an architecture wants to support multiple MSI, it needs to
77 * override arch_setup_msi_irqs()
79 if (type == PCI_CAP_ID_MSI && nvec > 1)
82 list_for_each_entry(entry, &dev->msi_list, list) {
83 ret = arch_setup_msi_irq(dev, entry);
94 * We have a default implementation available as a separate non-weak
95 * function, as it is used by the Xen x86 PCI code
97 void default_teardown_msi_irqs(struct pci_dev *dev)
99 struct msi_desc *entry;
101 list_for_each_entry(entry, &dev->msi_list, list) {
105 if (entry->nvec_used)
106 nvec = entry->nvec_used;
108 nvec = 1 << entry->msi_attrib.multiple;
109 for (i = 0; i < nvec; i++)
110 arch_teardown_msi_irq(entry->irq + i);
114 void __weak arch_teardown_msi_irqs(struct pci_dev *dev)
116 return default_teardown_msi_irqs(dev);
119 void default_restore_msi_irqs(struct pci_dev *dev, int irq)
121 struct msi_desc *entry;
124 if (dev->msix_enabled) {
125 list_for_each_entry(entry, &dev->msi_list, list) {
126 if (irq == entry->irq)
129 } else if (dev->msi_enabled) {
130 entry = irq_get_msi_desc(irq);
134 write_msi_msg(irq, &entry->msg);
137 void __weak arch_restore_msi_irqs(struct pci_dev *dev, int irq)
139 return default_restore_msi_irqs(dev, irq);
142 static void msi_set_enable(struct pci_dev *dev, int enable)
146 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
147 control &= ~PCI_MSI_FLAGS_ENABLE;
149 control |= PCI_MSI_FLAGS_ENABLE;
150 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
153 static void msix_set_enable(struct pci_dev *dev, int enable)
157 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
158 control &= ~PCI_MSIX_FLAGS_ENABLE;
160 control |= PCI_MSIX_FLAGS_ENABLE;
161 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
164 static inline __attribute_const__ u32 msi_mask(unsigned x)
166 /* Don't shift by >= width of type */
169 return (1 << (1 << x)) - 1;
172 static inline __attribute_const__ u32 msi_capable_mask(u16 control)
174 return msi_mask((control >> 1) & 7);
177 static inline __attribute_const__ u32 msi_enabled_mask(u16 control)
179 return msi_mask((control >> 4) & 7);
183 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
184 * mask all MSI interrupts by clearing the MSI enable bit does not work
185 * reliably as devices without an INTx disable bit will then generate a
186 * level IRQ which will never be cleared.
188 u32 default_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
190 u32 mask_bits = desc->masked;
192 if (!desc->msi_attrib.maskbit)
197 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
202 __weak u32 arch_msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
204 return default_msi_mask_irq(desc, mask, flag);
207 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
209 desc->masked = arch_msi_mask_irq(desc, mask, flag);
213 * This internal function does not flush PCI writes to the device.
214 * All users must ensure that they read from the device before either
215 * assuming that the device state is up to date, or returning out of this
216 * file. This saves a few milliseconds when initialising devices with lots
217 * of MSI-X interrupts.
219 u32 default_msix_mask_irq(struct msi_desc *desc, u32 flag)
221 u32 mask_bits = desc->masked;
222 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
223 PCI_MSIX_ENTRY_VECTOR_CTRL;
224 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
226 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
227 writel(mask_bits, desc->mask_base + offset);
232 __weak u32 arch_msix_mask_irq(struct msi_desc *desc, u32 flag)
234 return default_msix_mask_irq(desc, flag);
237 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
239 desc->masked = arch_msix_mask_irq(desc, flag);
242 static void msi_set_mask_bit(struct irq_data *data, u32 flag)
244 struct msi_desc *desc = irq_data_get_msi(data);
246 if (desc->msi_attrib.is_msix) {
247 msix_mask_irq(desc, flag);
248 readl(desc->mask_base); /* Flush write to device */
250 unsigned offset = data->irq - desc->dev->irq;
251 msi_mask_irq(desc, 1 << offset, flag << offset);
255 void mask_msi_irq(struct irq_data *data)
257 msi_set_mask_bit(data, 1);
260 void unmask_msi_irq(struct irq_data *data)
262 msi_set_mask_bit(data, 0);
265 void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
267 BUG_ON(entry->dev->current_state != PCI_D0);
269 if (entry->msi_attrib.is_msix) {
270 void __iomem *base = entry->mask_base +
271 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
273 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
274 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
275 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
277 struct pci_dev *dev = entry->dev;
278 int pos = dev->msi_cap;
281 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
283 if (entry->msi_attrib.is_64) {
284 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
286 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
289 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
295 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
297 struct msi_desc *entry = irq_get_msi_desc(irq);
299 __read_msi_msg(entry, msg);
302 void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
304 /* Assert that the cache is valid, assuming that
305 * valid messages are not all-zeroes. */
306 BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo |
312 void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
314 struct msi_desc *entry = irq_get_msi_desc(irq);
316 __get_cached_msi_msg(entry, msg);
319 void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
321 if (entry->dev->current_state != PCI_D0) {
322 /* Don't touch the hardware now */
323 } else if (entry->msi_attrib.is_msix) {
325 base = entry->mask_base +
326 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
328 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
329 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
330 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
332 struct pci_dev *dev = entry->dev;
333 int pos = dev->msi_cap;
336 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
337 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
338 msgctl |= entry->msi_attrib.multiple << 4;
339 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
341 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
343 if (entry->msi_attrib.is_64) {
344 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
346 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
349 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
356 void write_msi_msg(unsigned int irq, struct msi_msg *msg)
358 struct msi_desc *entry = irq_get_msi_desc(irq);
360 __write_msi_msg(entry, msg);
363 static void free_msi_irqs(struct pci_dev *dev)
365 struct msi_desc *entry, *tmp;
367 list_for_each_entry(entry, &dev->msi_list, list) {
371 if (entry->nvec_used)
372 nvec = entry->nvec_used;
374 nvec = 1 << entry->msi_attrib.multiple;
375 for (i = 0; i < nvec; i++)
376 BUG_ON(irq_has_action(entry->irq + i));
379 arch_teardown_msi_irqs(dev);
381 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
382 if (entry->msi_attrib.is_msix) {
383 if (list_is_last(&entry->list, &dev->msi_list))
384 iounmap(entry->mask_base);
388 * Its possible that we get into this path
389 * When populate_msi_sysfs fails, which means the entries
390 * were not registered with sysfs. In that case don't
393 if (entry->kobj.parent) {
394 kobject_del(&entry->kobj);
395 kobject_put(&entry->kobj);
398 list_del(&entry->list);
403 static struct msi_desc *alloc_msi_entry(struct pci_dev *dev)
405 struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL);
409 INIT_LIST_HEAD(&desc->list);
415 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
417 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
418 pci_intx(dev, enable);
421 static void __pci_restore_msi_state(struct pci_dev *dev)
424 struct msi_desc *entry;
426 if (!dev->msi_enabled)
429 entry = irq_get_msi_desc(dev->irq);
431 pci_intx_for_msi(dev, 0);
432 msi_set_enable(dev, 0);
433 arch_restore_msi_irqs(dev, dev->irq);
435 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
436 msi_mask_irq(entry, msi_capable_mask(control), entry->masked);
437 control &= ~PCI_MSI_FLAGS_QSIZE;
438 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
439 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
442 static void __pci_restore_msix_state(struct pci_dev *dev)
444 struct msi_desc *entry;
447 if (!dev->msix_enabled)
449 BUG_ON(list_empty(&dev->msi_list));
450 entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
451 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
453 /* route the table */
454 pci_intx_for_msi(dev, 0);
455 control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL;
456 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
458 list_for_each_entry(entry, &dev->msi_list, list) {
459 arch_restore_msi_irqs(dev, entry->irq);
460 msix_mask_irq(entry, entry->masked);
463 control &= ~PCI_MSIX_FLAGS_MASKALL;
464 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
467 void pci_restore_msi_state(struct pci_dev *dev)
469 __pci_restore_msi_state(dev);
470 __pci_restore_msix_state(dev);
472 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
475 #define to_msi_attr(obj) container_of(obj, struct msi_attribute, attr)
476 #define to_msi_desc(obj) container_of(obj, struct msi_desc, kobj)
478 struct msi_attribute {
479 struct attribute attr;
480 ssize_t (*show)(struct msi_desc *entry, struct msi_attribute *attr,
482 ssize_t (*store)(struct msi_desc *entry, struct msi_attribute *attr,
483 const char *buf, size_t count);
486 static ssize_t show_msi_mode(struct msi_desc *entry, struct msi_attribute *atr,
489 return sprintf(buf, "%s\n", entry->msi_attrib.is_msix ? "msix" : "msi");
492 static ssize_t msi_irq_attr_show(struct kobject *kobj,
493 struct attribute *attr, char *buf)
495 struct msi_attribute *attribute = to_msi_attr(attr);
496 struct msi_desc *entry = to_msi_desc(kobj);
498 if (!attribute->show)
501 return attribute->show(entry, attribute, buf);
504 static const struct sysfs_ops msi_irq_sysfs_ops = {
505 .show = msi_irq_attr_show,
508 static struct msi_attribute mode_attribute =
509 __ATTR(mode, S_IRUGO, show_msi_mode, NULL);
512 static struct attribute *msi_irq_default_attrs[] = {
513 &mode_attribute.attr,
517 static void msi_kobj_release(struct kobject *kobj)
519 struct msi_desc *entry = to_msi_desc(kobj);
521 pci_dev_put(entry->dev);
524 static struct kobj_type msi_irq_ktype = {
525 .release = msi_kobj_release,
526 .sysfs_ops = &msi_irq_sysfs_ops,
527 .default_attrs = msi_irq_default_attrs,
530 static int populate_msi_sysfs(struct pci_dev *pdev)
532 struct msi_desc *entry;
533 struct kobject *kobj;
537 pdev->msi_kset = kset_create_and_add("msi_irqs", NULL, &pdev->dev.kobj);
541 list_for_each_entry(entry, &pdev->msi_list, list) {
543 kobj->kset = pdev->msi_kset;
545 ret = kobject_init_and_add(kobj, &msi_irq_ktype, NULL,
556 list_for_each_entry(entry, &pdev->msi_list, list) {
559 kobject_del(&entry->kobj);
560 kobject_put(&entry->kobj);
567 * msi_capability_init - configure device's MSI capability structure
568 * @dev: pointer to the pci_dev data structure of MSI device function
569 * @nvec: number of interrupts to allocate
571 * Setup the MSI capability structure of the device with the requested
572 * number of interrupts. A return value of zero indicates the successful
573 * setup of an entry with the new MSI irq. A negative return value indicates
574 * an error, and a positive return value indicates the number of interrupts
575 * which could have been allocated.
577 static int msi_capability_init(struct pci_dev *dev, int nvec)
579 struct msi_desc *entry;
584 msi_set_enable(dev, 0); /* Disable MSI during set up */
586 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
587 /* MSI Entry Initialization */
588 entry = alloc_msi_entry(dev);
592 entry->msi_attrib.is_msix = 0;
593 entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
594 entry->msi_attrib.entry_nr = 0;
595 entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
596 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
597 entry->msi_attrib.pos = dev->msi_cap;
599 if (control & PCI_MSI_FLAGS_64BIT)
600 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_64;
602 entry->mask_pos = dev->msi_cap + PCI_MSI_MASK_32;
603 /* All MSIs are unmasked by default, Mask them all */
604 if (entry->msi_attrib.maskbit)
605 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
606 mask = msi_capable_mask(control);
607 msi_mask_irq(entry, mask, mask);
609 list_add_tail(&entry->list, &dev->msi_list);
611 /* Configure MSI capability structure */
612 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
614 msi_mask_irq(entry, mask, ~mask);
619 ret = populate_msi_sysfs(dev);
621 msi_mask_irq(entry, mask, ~mask);
626 /* Set MSI enabled bits */
627 pci_intx_for_msi(dev, 0);
628 msi_set_enable(dev, 1);
629 dev->msi_enabled = 1;
631 dev->irq = entry->irq;
635 static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
637 resource_size_t phys_addr;
641 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
643 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
644 table_offset &= PCI_MSIX_TABLE_OFFSET;
645 phys_addr = pci_resource_start(dev, bir) + table_offset;
647 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
650 static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
651 struct msix_entry *entries, int nvec)
653 struct msi_desc *entry;
656 for (i = 0; i < nvec; i++) {
657 entry = alloc_msi_entry(dev);
663 /* No enough memory. Don't try again */
667 entry->msi_attrib.is_msix = 1;
668 entry->msi_attrib.is_64 = 1;
669 entry->msi_attrib.entry_nr = entries[i].entry;
670 entry->msi_attrib.default_irq = dev->irq;
671 entry->msi_attrib.pos = dev->msix_cap;
672 entry->mask_base = base;
674 list_add_tail(&entry->list, &dev->msi_list);
680 static void msix_program_entries(struct pci_dev *dev,
681 struct msix_entry *entries)
683 struct msi_desc *entry;
686 list_for_each_entry(entry, &dev->msi_list, list) {
687 int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE +
688 PCI_MSIX_ENTRY_VECTOR_CTRL;
690 entries[i].vector = entry->irq;
691 irq_set_msi_desc(entry->irq, entry);
692 entry->masked = readl(entry->mask_base + offset);
693 msix_mask_irq(entry, 1);
699 * msix_capability_init - configure device's MSI-X capability
700 * @dev: pointer to the pci_dev data structure of MSI-X device function
701 * @entries: pointer to an array of struct msix_entry entries
702 * @nvec: number of @entries
704 * Setup the MSI-X capability structure of device function with a
705 * single MSI-X irq. A return of zero indicates the successful setup of
706 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
708 static int msix_capability_init(struct pci_dev *dev,
709 struct msix_entry *entries, int nvec)
715 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
717 /* Ensure MSI-X is disabled while it is set up */
718 control &= ~PCI_MSIX_FLAGS_ENABLE;
719 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
721 /* Request & Map MSI-X table region */
722 base = msix_map_region(dev, msix_table_size(control));
726 ret = msix_setup_entries(dev, base, entries, nvec);
730 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
735 * Some devices require MSI-X to be enabled before we can touch the
736 * MSI-X registers. We need to mask all the vectors to prevent
737 * interrupts coming in before they're fully set up.
739 control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE;
740 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
742 msix_program_entries(dev, entries);
744 ret = populate_msi_sysfs(dev);
750 /* Set MSI-X enabled bits and unmask the function */
751 pci_intx_for_msi(dev, 0);
752 dev->msix_enabled = 1;
754 control &= ~PCI_MSIX_FLAGS_MASKALL;
755 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
762 * If we had some success, report the number of irqs
763 * we succeeded in setting up.
765 struct msi_desc *entry;
768 list_for_each_entry(entry, &dev->msi_list, list) {
782 * pci_msi_check_device - check whether MSI may be enabled on a device
783 * @dev: pointer to the pci_dev data structure of MSI device function
784 * @nvec: how many MSIs have been requested ?
785 * @type: are we checking for MSI or MSI-X ?
787 * Look at global flags, the device itself, and its parent buses
788 * to determine if MSI/-X are supported for the device. If MSI/-X is
789 * supported return 0, else return an error code.
791 static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type)
796 /* MSI must be globally enabled and supported by the device */
797 if (!pci_msi_enable || !dev || dev->no_msi)
801 * You can't ask to have 0 or less MSIs configured.
803 * b) the list manipulation code assumes nvec >= 1.
809 * Any bridge which does NOT route MSI transactions from its
810 * secondary bus to its primary bus must set NO_MSI flag on
811 * the secondary pci_bus.
812 * We expect only arch-specific PCI host bus controller driver
813 * or quirks for specific PCI bridges to be setting NO_MSI.
815 for (bus = dev->bus; bus; bus = bus->parent)
816 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
819 ret = arch_msi_check_device(dev, nvec, type);
827 * pci_enable_msi_block - configure device's MSI capability structure
828 * @dev: device to configure
829 * @nvec: number of interrupts to configure
831 * Allocate IRQs for a device with the MSI capability.
832 * This function returns a negative errno if an error occurs. If it
833 * is unable to allocate the number of interrupts requested, it returns
834 * the number of interrupts it might be able to allocate. If it successfully
835 * allocates at least the number of interrupts requested, it returns 0 and
836 * updates the @dev's irq member to the lowest new interrupt number; the
837 * other interrupt numbers allocated to this device are consecutive.
839 int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
844 if (!dev->msi_cap || dev->current_state != PCI_D0)
847 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
848 maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
852 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI);
856 WARN_ON(!!dev->msi_enabled);
858 /* Check whether driver already requested MSI-X irqs */
859 if (dev->msix_enabled) {
860 dev_info(&dev->dev, "can't enable MSI "
861 "(MSI-X already enabled)\n");
865 status = msi_capability_init(dev, nvec);
868 EXPORT_SYMBOL(pci_enable_msi_block);
870 int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec)
875 if (!dev->msi_cap || dev->current_state != PCI_D0)
878 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
879 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
886 ret = pci_enable_msi_block(dev, nvec);
893 EXPORT_SYMBOL(pci_enable_msi_block_auto);
895 void pci_msi_shutdown(struct pci_dev *dev)
897 struct msi_desc *desc;
901 if (!pci_msi_enable || !dev || !dev->msi_enabled)
904 BUG_ON(list_empty(&dev->msi_list));
905 desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
907 msi_set_enable(dev, 0);
908 pci_intx_for_msi(dev, 1);
909 dev->msi_enabled = 0;
911 /* Return the device with MSI unmasked as initial states */
912 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl);
913 mask = msi_capable_mask(ctrl);
914 /* Keep cached state to be restored */
915 arch_msi_mask_irq(desc, mask, ~mask);
917 /* Restore dev->irq to its default pin-assertion irq */
918 dev->irq = desc->msi_attrib.default_irq;
921 void pci_disable_msi(struct pci_dev *dev)
923 if (!pci_msi_enable || !dev || !dev->msi_enabled)
926 pci_msi_shutdown(dev);
928 kset_unregister(dev->msi_kset);
929 dev->msi_kset = NULL;
931 EXPORT_SYMBOL(pci_disable_msi);
934 * pci_msix_table_size - return the number of device's MSI-X table entries
935 * @dev: pointer to the pci_dev data structure of MSI-X device function
937 int pci_msix_table_size(struct pci_dev *dev)
944 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
945 return msix_table_size(control);
949 * pci_enable_msix - configure device's MSI-X capability structure
950 * @dev: pointer to the pci_dev data structure of MSI-X device function
951 * @entries: pointer to an array of MSI-X entries
952 * @nvec: number of MSI-X irqs requested for allocation by device driver
954 * Setup the MSI-X capability structure of device function with the number
955 * of requested irqs upon its software driver call to request for
956 * MSI-X mode enabled on its hardware device function. A return of zero
957 * indicates the successful configuration of MSI-X capability structure
958 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
959 * Or a return of > 0 indicates that driver request is exceeding the number
960 * of irqs or MSI-X vectors available. Driver should use the returned value to
961 * re-send its request.
963 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
965 int status, nr_entries;
968 if (!entries || !dev->msix_cap || dev->current_state != PCI_D0)
971 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX);
975 nr_entries = pci_msix_table_size(dev);
976 if (nvec > nr_entries)
979 /* Check for any invalid entries */
980 for (i = 0; i < nvec; i++) {
981 if (entries[i].entry >= nr_entries)
982 return -EINVAL; /* invalid entry */
983 for (j = i + 1; j < nvec; j++) {
984 if (entries[i].entry == entries[j].entry)
985 return -EINVAL; /* duplicate entry */
988 WARN_ON(!!dev->msix_enabled);
990 /* Check whether driver already requested for MSI irq */
991 if (dev->msi_enabled) {
992 dev_info(&dev->dev, "can't enable MSI-X "
993 "(MSI IRQ already assigned)\n");
996 status = msix_capability_init(dev, entries, nvec);
999 EXPORT_SYMBOL(pci_enable_msix);
1001 void pci_msix_shutdown(struct pci_dev *dev)
1003 struct msi_desc *entry;
1005 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1008 /* Return the device with MSI-X masked as initial states */
1009 list_for_each_entry(entry, &dev->msi_list, list) {
1010 /* Keep cached states to be restored */
1011 arch_msix_mask_irq(entry, 1);
1014 msix_set_enable(dev, 0);
1015 pci_intx_for_msi(dev, 1);
1016 dev->msix_enabled = 0;
1019 void pci_disable_msix(struct pci_dev *dev)
1021 if (!pci_msi_enable || !dev || !dev->msix_enabled)
1024 pci_msix_shutdown(dev);
1026 kset_unregister(dev->msi_kset);
1027 dev->msi_kset = NULL;
1029 EXPORT_SYMBOL(pci_disable_msix);
1032 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
1033 * @dev: pointer to the pci_dev data structure of MSI(X) device function
1035 * Being called during hotplug remove, from which the device function
1036 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
1037 * allocated for this device function, are reclaimed to unused state,
1038 * which may be used later on.
1040 void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1042 if (!pci_msi_enable || !dev)
1045 if (dev->msi_enabled || dev->msix_enabled)
1049 void pci_no_msi(void)
1055 * pci_msi_enabled - is MSI enabled?
1057 * Returns true if MSI has not been disabled by the command-line option
1060 int pci_msi_enabled(void)
1062 return pci_msi_enable;
1064 EXPORT_SYMBOL(pci_msi_enabled);
1066 void pci_msi_init_pci_dev(struct pci_dev *dev)
1068 INIT_LIST_HEAD(&dev->msi_list);
1070 /* Disable the msi hardware to avoid screaming interrupts
1071 * during boot. This is the power on reset default so
1072 * usually this should be a noop.
1074 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1076 msi_set_enable(dev, 0);
1078 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1080 msix_set_enable(dev, 0);