2 * pci-rcar-gen2: internal PCI bus support
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Cogent Embedded, Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/delay.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/slab.h>
23 /* AHB-PCI Bridge PCI communication registers */
24 #define RCAR_AHBPCI_PCICOM_OFFSET 0x800
26 #define RCAR_PCIAHB_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
27 #define RCAR_PCIAHB_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
28 #define RCAR_PCIAHB_PREFETCH0 0x0
29 #define RCAR_PCIAHB_PREFETCH4 0x1
30 #define RCAR_PCIAHB_PREFETCH8 0x2
31 #define RCAR_PCIAHB_PREFETCH16 0x3
33 #define RCAR_AHBPCI_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
34 #define RCAR_AHBPCI_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
35 #define RCAR_AHBPCI_WIN_CTR_MEM (3 << 1)
36 #define RCAR_AHBPCI_WIN_CTR_CFG (5 << 1)
37 #define RCAR_AHBPCI_WIN1_HOST (1 << 30)
38 #define RCAR_AHBPCI_WIN1_DEVICE (1 << 31)
40 #define RCAR_PCI_INT_ENABLE_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
41 #define RCAR_PCI_INT_STATUS_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
42 #define RCAR_PCI_INT_SIGTABORT (1 << 0)
43 #define RCAR_PCI_INT_SIGRETABORT (1 << 1)
44 #define RCAR_PCI_INT_REMABORT (1 << 2)
45 #define RCAR_PCI_INT_PERR (1 << 3)
46 #define RCAR_PCI_INT_SIGSERR (1 << 4)
47 #define RCAR_PCI_INT_RESERR (1 << 5)
48 #define RCAR_PCI_INT_WIN1ERR (1 << 12)
49 #define RCAR_PCI_INT_WIN2ERR (1 << 13)
50 #define RCAR_PCI_INT_A (1 << 16)
51 #define RCAR_PCI_INT_B (1 << 17)
52 #define RCAR_PCI_INT_PME (1 << 19)
53 #define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT | \
54 RCAR_PCI_INT_SIGRETABORT | \
55 RCAR_PCI_INT_SIGRETABORT | \
56 RCAR_PCI_INT_REMABORT | \
58 RCAR_PCI_INT_SIGSERR | \
59 RCAR_PCI_INT_RESERR | \
60 RCAR_PCI_INT_WIN1ERR | \
63 #define RCAR_AHB_BUS_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
64 #define RCAR_AHB_BUS_MMODE_HTRANS (1 << 0)
65 #define RCAR_AHB_BUS_MMODE_BYTE_BURST (1 << 1)
66 #define RCAR_AHB_BUS_MMODE_WR_INCR (1 << 2)
67 #define RCAR_AHB_BUS_MMODE_HBUS_REQ (1 << 7)
68 #define RCAR_AHB_BUS_SMODE_READYCTR (1 << 17)
69 #define RCAR_AHB_BUS_MODE (RCAR_AHB_BUS_MMODE_HTRANS | \
70 RCAR_AHB_BUS_MMODE_BYTE_BURST | \
71 RCAR_AHB_BUS_MMODE_WR_INCR | \
72 RCAR_AHB_BUS_MMODE_HBUS_REQ | \
73 RCAR_AHB_BUS_SMODE_READYCTR)
75 #define RCAR_USBCTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x34)
76 #define RCAR_USBCTR_USBH_RST (1 << 0)
77 #define RCAR_USBCTR_PCICLK_MASK (1 << 1)
78 #define RCAR_USBCTR_PLL_RST (1 << 2)
79 #define RCAR_USBCTR_DIRPD (1 << 8)
80 #define RCAR_USBCTR_PCIAHB_WIN2_EN (1 << 9)
81 #define RCAR_USBCTR_PCIAHB_WIN1_256M (0 << 10)
82 #define RCAR_USBCTR_PCIAHB_WIN1_512M (1 << 10)
83 #define RCAR_USBCTR_PCIAHB_WIN1_1G (2 << 10)
84 #define RCAR_USBCTR_PCIAHB_WIN1_2G (3 << 10)
85 #define RCAR_USBCTR_PCIAHB_WIN1_MASK (3 << 10)
87 #define RCAR_PCI_ARBITER_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x40)
88 #define RCAR_PCI_ARBITER_PCIREQ0 (1 << 0)
89 #define RCAR_PCI_ARBITER_PCIREQ1 (1 << 1)
90 #define RCAR_PCI_ARBITER_PCIBP_MODE (1 << 12)
92 #define RCAR_PCI_UNIT_REV_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
94 /* Number of internal PCI controllers */
95 #define RCAR_PCI_NR_CONTROLLERS 3
97 struct rcar_pci_priv {
100 struct resource io_res;
101 struct resource mem_res;
102 struct resource *cfg_res;
106 /* PCI configuration space operations */
107 static void __iomem *rcar_pci_cfg_base(struct pci_bus *bus, unsigned int devfn,
110 struct pci_sys_data *sys = bus->sysdata;
111 struct rcar_pci_priv *priv = sys->private_data;
114 if (sys->busnr != bus->number || PCI_FUNC(devfn))
117 /* Only one EHCI/OHCI device built-in */
118 slot = PCI_SLOT(devfn);
122 val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG :
123 RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG;
125 iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG);
126 return priv->reg + (slot >> 1) * 0x100 + where;
129 static int rcar_pci_read_config(struct pci_bus *bus, unsigned int devfn,
130 int where, int size, u32 *val)
132 void __iomem *reg = rcar_pci_cfg_base(bus, devfn, where);
135 return PCIBIOS_DEVICE_NOT_FOUND;
142 *val = ioread16(reg);
145 *val = ioread32(reg);
149 return PCIBIOS_SUCCESSFUL;
152 static int rcar_pci_write_config(struct pci_bus *bus, unsigned int devfn,
153 int where, int size, u32 val)
155 void __iomem *reg = rcar_pci_cfg_base(bus, devfn, where);
158 return PCIBIOS_DEVICE_NOT_FOUND;
172 return PCIBIOS_SUCCESSFUL;
175 /* PCI interrupt mapping */
176 static int __init rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
178 struct pci_sys_data *sys = dev->bus->sysdata;
179 struct rcar_pci_priv *priv = sys->private_data;
184 #ifdef CONFIG_PCI_DEBUG
185 /* if debug enabled, then attach an error handler irq to the bridge */
187 static irqreturn_t rcar_pci_err_irq(int irq, void *pw)
189 struct rcar_pci_priv *priv = pw;
190 u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG);
192 if (status & RCAR_PCI_INT_ALLERRORS) {
193 dev_err(priv->dev, "error irq: status %08x\n", status);
195 /* clear the error(s) */
196 iowrite32(status & RCAR_PCI_INT_ALLERRORS,
197 priv->reg + RCAR_PCI_INT_STATUS_REG);
204 static void rcar_pci_setup_errirq(struct rcar_pci_priv *priv)
209 ret = devm_request_irq(priv->dev, priv->irq, rcar_pci_err_irq,
210 IRQF_SHARED, "error irq", priv);
212 dev_err(priv->dev, "cannot claim IRQ for error handling\n");
216 val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG);
217 val |= RCAR_PCI_INT_ALLERRORS;
218 iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG);
221 static inline void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) { }
224 /* PCI host controller setup */
225 static int __init rcar_pci_setup(int nr, struct pci_sys_data *sys)
227 struct rcar_pci_priv *priv = sys->private_data;
228 void __iomem *reg = priv->reg;
231 pm_runtime_enable(priv->dev);
232 pm_runtime_get_sync(priv->dev);
234 val = ioread32(reg + RCAR_PCI_UNIT_REV_REG);
235 dev_info(priv->dev, "PCI: bus%u revision %x\n", sys->busnr, val);
237 /* Disable Direct Power Down State and assert reset */
238 val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD;
239 val |= RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST;
240 iowrite32(val, reg + RCAR_USBCTR_REG);
243 /* De-assert reset and set PCIAHB window1 size to 1GB */
244 val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK | RCAR_USBCTR_PCICLK_MASK |
245 RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST);
246 iowrite32(val | RCAR_USBCTR_PCIAHB_WIN1_1G, reg + RCAR_USBCTR_REG);
248 /* Configure AHB master and slave modes */
249 iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG);
251 /* Configure PCI arbiter */
252 val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG);
253 val |= RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 |
254 RCAR_PCI_ARBITER_PCIBP_MODE;
255 iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);
257 /* PCI-AHB mapping: 0x40000000-0x80000000 */
258 iowrite32(0x40000000 | RCAR_PCIAHB_PREFETCH16,
259 reg + RCAR_PCIAHB_WIN1_CTR_REG);
261 /* AHB-PCI mapping: OHCI/EHCI registers */
262 val = priv->mem_res.start | RCAR_AHBPCI_WIN_CTR_MEM;
263 iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG);
265 /* Enable AHB-PCI bridge PCI configuration access */
266 iowrite32(RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG,
267 reg + RCAR_AHBPCI_WIN1_CTR_REG);
268 /* Set PCI-AHB Window1 address */
269 iowrite32(0x40000000 | PCI_BASE_ADDRESS_MEM_PREFETCH,
270 reg + PCI_BASE_ADDRESS_1);
271 /* Set AHB-PCI bridge PCI communication area address */
272 val = priv->cfg_res->start + RCAR_AHBPCI_PCICOM_OFFSET;
273 iowrite32(val, reg + PCI_BASE_ADDRESS_0);
275 val = ioread32(reg + PCI_COMMAND);
276 val |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
277 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
278 iowrite32(val, reg + PCI_COMMAND);
280 /* Enable PCI interrupts */
281 iowrite32(RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME,
282 reg + RCAR_PCI_INT_ENABLE_REG);
285 rcar_pci_setup_errirq(priv);
287 /* Add PCI resources */
288 pci_add_resource(&sys->resources, &priv->io_res);
289 pci_add_resource(&sys->resources, &priv->mem_res);
294 static struct pci_ops rcar_pci_ops = {
295 .read = rcar_pci_read_config,
296 .write = rcar_pci_write_config,
299 static struct hw_pci rcar_hw_pci __initdata = {
300 .map_irq = rcar_pci_map_irq,
301 .ops = &rcar_pci_ops,
302 .setup = rcar_pci_setup,
305 static int rcar_pci_count __initdata;
307 static int __init rcar_pci_add_controller(struct rcar_pci_priv *priv)
312 if (rcar_hw_pci.nr_controllers < rcar_pci_count)
315 /* (Re)allocate private data pointer array if needed */
316 count = rcar_pci_count + RCAR_PCI_NR_CONTROLLERS;
317 private_data = kzalloc(count * sizeof(void *), GFP_KERNEL);
321 rcar_pci_count = count;
322 if (rcar_hw_pci.private_data) {
323 memcpy(private_data, rcar_hw_pci.private_data,
324 rcar_hw_pci.nr_controllers * sizeof(void *));
325 kfree(rcar_hw_pci.private_data);
328 rcar_hw_pci.private_data = private_data;
331 /* Add private data pointer to the array */
332 rcar_hw_pci.private_data[rcar_hw_pci.nr_controllers++] = priv;
336 static int __init rcar_pci_probe(struct platform_device *pdev)
338 struct resource *cfg_res, *mem_res;
339 struct rcar_pci_priv *priv;
342 cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
343 reg = devm_ioremap_resource(&pdev->dev, cfg_res);
347 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
348 if (!mem_res || !mem_res->start)
351 priv = devm_kzalloc(&pdev->dev,
352 sizeof(struct rcar_pci_priv), GFP_KERNEL);
356 priv->mem_res = *mem_res;
358 * The controller does not support/use port I/O,
359 * so setup a dummy port I/O region here.
361 priv->io_res.start = priv->mem_res.start;
362 priv->io_res.end = priv->mem_res.end;
363 priv->io_res.flags = IORESOURCE_IO;
365 priv->cfg_res = cfg_res;
367 priv->irq = platform_get_irq(pdev, 0);
369 priv->dev = &pdev->dev;
372 dev_err(&pdev->dev, "no valid irq found\n");
376 return rcar_pci_add_controller(priv);
379 static struct platform_driver rcar_pci_driver = {
381 .name = "pci-rcar-gen2",
385 static int __init rcar_pci_init(void)
389 retval = platform_driver_probe(&rcar_pci_driver, rcar_pci_probe);
391 pci_common_init(&rcar_hw_pci);
393 /* Private data pointer array is not needed any more */
394 kfree(rcar_hw_pci.private_data);
395 rcar_hw_pci.private_data = NULL;
400 subsys_initcall(rcar_pci_init);
402 MODULE_LICENSE("GPL v2");
403 MODULE_DESCRIPTION("Renesas R-Car Gen2 internal PCI");
404 MODULE_AUTHOR("Valentine Barshak <valentine.barshak@cogentembedded.com>");