1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007-2012 Freescale Semiconductor, Inc.
11 #include <asm/fsl_serdes.h>
12 #include <linux/delay.h>
14 DECLARE_GLOBAL_DATA_PTR;
17 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
19 * Initialize controller and call the common driver/pci pci_hose_scan to
20 * scan for bridges and devices.
22 * Hose fields which need to be pre-initialized by board specific code:
32 #include <asm/fsl_pci.h>
34 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
35 #define CONFIG_SYS_PCI_MEMORY_BUS 0
38 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS
39 #define CONFIG_SYS_PCI_MEMORY_PHYS 0
42 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
43 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
46 /* Setup one inbound ATMU window.
48 * We let the caller decide what the window size should be
50 static void set_inbound_window(volatile pit_t *pi,
54 u32 sz = (__ilog2_u64(size) - 1);
55 #ifdef CONFIG_SYS_FSL_ERRATUM_A005434
58 u32 flag = PIWAR_LOCAL;
61 flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
63 out_be32(&pi->pitar, r->phys_start >> 12);
64 out_be32(&pi->piwbar, r->bus_start >> 12);
65 #ifdef CONFIG_SYS_PCI_64BIT
66 out_be32(&pi->piwbear, r->bus_start >> 44);
68 out_be32(&pi->piwbear, 0);
70 if (r->flags & PCI_REGION_PREFETCH)
72 out_be32(&pi->piwar, flag | sz);
75 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr)
77 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr;
79 /* Reset hose to make sure its in a clean state */
80 memset(hose, 0, sizeof(struct pci_controller));
82 pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
84 return fsl_is_pci_agent(hose);
87 static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
88 u64 out_lo, u8 pcie_cap,
91 struct pci_region *r = hose->regions + hose->region_count;
92 u64 sz = min((u64)gd->ram_size, (1ull << 32));
94 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
95 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
98 /* we have no space available for inbound memory mapping */
99 if (bus_start > out_lo) {
100 printf ("no space for inbound mapping of memory\n");
105 if ((bus_start + sz) > out_lo) {
106 sz = out_lo - bus_start;
107 debug ("limiting size to %llx\n", sz);
110 pci_sz = 1ull << __ilog2_u64(sz);
112 * we can overlap inbound/outbound windows on PCI-E since RX & TX
115 if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) {
116 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
117 (u64)bus_start, (u64)phys_start, (u64)sz);
118 pci_set_region(r, bus_start, phys_start, sz,
119 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
120 PCI_REGION_PREFETCH);
122 /* if we aren't an exact power of two match, pci_sz is smaller
123 * round it up to the next power of two. We report the actual
124 * size to pci region tracking.
127 sz = 2ull << __ilog2_u64(sz);
129 set_inbound_window(pi--, r++, sz);
130 sz = 0; /* make sure we dont set the R2 window */
132 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
133 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
134 pci_set_region(r, bus_start, phys_start, pci_sz,
135 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
136 PCI_REGION_PREFETCH);
137 set_inbound_window(pi--, r++, pci_sz);
141 phys_start += pci_sz;
143 pci_sz = 1ull << __ilog2_u64(sz);
145 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
146 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
147 pci_set_region(r, bus_start, phys_start, pci_sz,
148 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
149 PCI_REGION_PREFETCH);
150 set_inbound_window(pi--, r++, pci_sz);
153 phys_start += pci_sz;
157 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
159 * On 64-bit capable systems, set up a mapping for all of DRAM
160 * in high pci address space.
162 pci_sz = 1ull << __ilog2_u64(gd->ram_size);
163 /* round up to the next largest power of two */
164 if (gd->ram_size > pci_sz)
165 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
166 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
167 (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
168 (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
171 CONFIG_SYS_PCI64_MEMORY_BUS,
172 CONFIG_SYS_PCI_MEMORY_PHYS,
174 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
175 PCI_REGION_PREFETCH);
176 set_inbound_window(pi--, r++, pci_sz);
178 pci_sz = 1ull << __ilog2_u64(sz);
180 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
181 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
182 pci_set_region(r, bus_start, phys_start, pci_sz,
183 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
184 PCI_REGION_PREFETCH);
187 phys_start += pci_sz;
188 set_inbound_window(pi--, r++, pci_sz);
192 #ifdef CONFIG_PHYS_64BIT
193 if (sz && (((u64)gd->ram_size) < (1ull << 32)))
194 printf("Was not able to map all of memory via "
195 "inbound windows -- %lld remaining\n", sz);
198 hose->region_count = r - hose->regions;
203 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
204 static void fsl_pcie_boot_master(pit_t *pi)
206 /* configure inbound window for slave's u-boot image */
207 debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
208 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
209 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
210 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
211 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
212 struct pci_region r_inbound;
213 u32 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE)
215 pci_set_region(&r_inbound,
216 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
217 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
219 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
221 set_inbound_window(pi--, &r_inbound,
222 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
224 /* configure inbound window for slave's u-boot image */
225 debug("PCIEBOOT - MASTER: Inbound window for slave's image; "
226 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
227 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
228 (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
229 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
230 pci_set_region(&r_inbound,
231 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
232 CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
234 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
236 set_inbound_window(pi--, &r_inbound,
237 CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
239 /* configure inbound window for slave's ucode and ENV */
240 debug("PCIEBOOT - MASTER: Inbound window for slave's "
242 "Local = 0x%llx, Bus = 0x%llx, Size = 0x%x\n",
243 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
244 (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
245 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
246 sz_inbound = __ilog2_u64(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE)
248 pci_set_region(&r_inbound,
249 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
250 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
252 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
254 set_inbound_window(pi--, &r_inbound,
255 CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
258 static void fsl_pcie_boot_master_release_slave(int port)
260 unsigned long release_addr;
262 /* now release slave's core 0 */
265 release_addr = CONFIG_SYS_PCIE1_MEM_VIRT
266 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
268 #ifdef CONFIG_SYS_PCIE2_MEM_VIRT
270 release_addr = CONFIG_SYS_PCIE2_MEM_VIRT
271 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
274 #ifdef CONFIG_SYS_PCIE3_MEM_VIRT
276 release_addr = CONFIG_SYS_PCIE3_MEM_VIRT
277 + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET;
284 if (release_addr != 0) {
285 out_be32((void *)release_addr,
286 CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
287 debug("PCIEBOOT - MASTER: "
288 "Release slave successfully! Now the slave should start up!\n");
290 debug("PCIEBOOT - MASTER: "
291 "Release slave failed!\n");
296 void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
298 u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
299 u32 cfg_data = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_data;
303 int enabled, r, inbound = 0;
311 #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
315 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
316 struct pci_region *reg = hose->regions + hose->region_count;
317 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
319 /* Initialize ATMU registers based on hose regions and flags */
320 volatile pot_t *po = &pci->pot[1]; /* skip 0 */
323 u64 out_hi = 0, out_lo = -1ULL;
324 u32 pcicsrbar, pcicsrbar_sz;
326 pci_setup_indirect(hose, cfg_addr, cfg_data);
329 /* Configure the PCIE controller core clock ratio */
330 pci_hose_write_config_dword(hose, dev, 0x440,
331 ((gd->bus_clk / 1000000) *
332 (16 / PEX_CCB_DIV)) / 333);
334 block_rev = in_be32(&pci->block_rev1);
335 if (PEX_IP_BLK_REV_2_2 <= block_rev) {
336 pi = &pci->pit[2]; /* 0xDC0 */
338 pi = &pci->pit[3]; /* 0xDE0 */
341 /* Handle setup of outbound windows first */
342 for (r = 0; r < hose->region_count; r++) {
343 unsigned long flags = hose->regions[r].flags;
344 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
346 flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE;
347 if (flags != PCI_REGION_SYS_MEMORY) {
348 u64 start = hose->regions[r].bus_start;
349 u64 end = start + hose->regions[r].size;
351 out_be32(&po->powbar, hose->regions[r].phys_start >> 12);
352 out_be32(&po->potar, start >> 12);
353 #ifdef CONFIG_SYS_PCI_64BIT
354 out_be32(&po->potear, start >> 44);
356 out_be32(&po->potear, 0);
358 if (hose->regions[r].flags & PCI_REGION_IO) {
359 out_be32(&po->powar, POWAR_EN | sz |
360 POWAR_IO_READ | POWAR_IO_WRITE);
362 out_be32(&po->powar, POWAR_EN | sz |
363 POWAR_MEM_READ | POWAR_MEM_WRITE);
364 out_lo = min(start, out_lo);
365 out_hi = max(end, out_hi);
370 debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi);
372 /* setup PCSRBAR/PEXCSRBAR */
373 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
374 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
375 pcicsrbar_sz = ~pcicsrbar_sz + 1;
377 if (out_hi < (0x100000000ull - pcicsrbar_sz) ||
378 (out_lo > 0x100000000ull))
379 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
381 pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz;
382 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar);
384 out_lo = min(out_lo, (u64)pcicsrbar);
386 debug("PCICSRBAR @ 0x%x\n", pcicsrbar);
388 pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS,
389 pcicsrbar_sz, PCI_REGION_SYS_MEMORY);
390 hose->region_count++;
392 /* see if we are a PCIe or PCI controller */
393 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
394 pci_dcr = pcie_cap_pos + 0x08;
395 pci_dsr = pcie_cap_pos + 0x0a;
396 pci_lsr = pcie_cap_pos + 0x12;
398 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
400 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
401 /* boot from PCIE --master */
402 char *s = env_get("bootmaster");
404 sprintf(pcie, "PCIE%d", pci_info->pci_num);
406 if (s && (strcmp(s, pcie) == 0)) {
407 debug("PCIEBOOT - MASTER: Master port [ %d ] for pcie boot.\n",
409 fsl_pcie_boot_master((pit_t *)pi);
412 inbound = fsl_pci_setup_inbound_windows(hose,
413 out_lo, pcie_cap, pi);
417 inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
420 for (r = 0; r < hose->region_count; r++)
421 debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n", r,
422 (u64)hose->regions[r].phys_start,
423 (u64)hose->regions[r].bus_start,
424 (u64)hose->regions[r].size,
425 hose->regions[r].flags);
427 pci_register_hose(hose);
428 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */
429 hose->current_busno = hose->first_busno;
431 out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */
432 out_be32(&pci->peer, ~0x20140); /* Enable All Error Interrupts except
433 * - Master abort (pci)
434 * - Master PERR (pci)
437 pci_hose_read_config_dword(hose, dev, pci_dcr, &temp32);
438 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */
439 pci_hose_write_config_dword(hose, dev, pci_dcr, temp32);
441 #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
442 pci_lcr = pcie_cap_pos + 0x10;
444 pci_hose_read_config_dword(hose, dev, pci_lcr, &temp32);
445 temp32 &= ~0x03; /* Disable ASPM */
446 pci_hose_write_config_dword(hose, dev, pci_lcr, temp32);
449 if (pcie_cap == PCI_CAP_ID_EXP) {
450 if (block_rev >= PEX_IP_BLK_REV_3_0) {
451 #define PEX_CSR0_LTSSM_MASK 0xFC
452 #define PEX_CSR0_LTSSM_SHIFT 2
453 ltssm = (in_be32(&pci->pex_csr0)
454 & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
455 enabled = (ltssm == 0x11) ? 1 : 0;
456 #ifdef CONFIG_FSL_PCIE_RESET
458 /* assert PCIe reset */
459 setbits_be32(&pci->pdb_stat, 0x08000000);
460 (void) in_be32(&pci->pdb_stat);
462 /* clear PCIe reset */
463 clrbits_be32(&pci->pdb_stat, 0x08000000);
465 for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
466 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
472 /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); */
473 /* enabled = ltssm >= PCI_LTSSM_L0; */
474 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
475 enabled = ltssm >= PCI_LTSSM_L0;
477 #ifdef CONFIG_FSL_PCIE_RESET
480 debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm);
481 /* assert PCIe reset */
482 setbits_be32(&pci->pdb_stat, 0x08000000);
483 (void) in_be32(&pci->pdb_stat);
485 debug(" Asserting PCIe reset @%p = %x\n",
486 &pci->pdb_stat, in_be32(&pci->pdb_stat));
487 /* clear PCIe reset */
488 clrbits_be32(&pci->pdb_stat, 0x08000000);
490 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
491 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
494 debug("....PCIe link error. "
495 "LTSSM=0x%02x.\n", ltssm);
497 enabled = ltssm >= PCI_LTSSM_L0;
499 /* we need to re-write the bar0 since a reset will
502 pci_hose_write_config_dword(hose, dev,
503 PCI_BASE_ADDRESS_0, pcicsrbar);
508 #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
510 serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
511 temp32 = in_be32(&srds_regs->srdspccr0);
513 if ((temp32 >> 28) == 3) {
516 out_be32(&srds_regs->srdspccr0, 2 << 28);
517 setbits_be32(&pci->pdb_stat, 0x08000000);
518 in_be32(&pci->pdb_stat);
520 clrbits_be32(&pci->pdb_stat, 0x08000000);
522 for (i=0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
523 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
526 enabled = ltssm >= PCI_LTSSM_L0;
531 /* Let the user know there's no PCIe link for root
532 * complex. for endpoint, the link may not setup, so
533 * print undetermined.
535 if (fsl_is_pci_agent(hose))
536 printf("undetermined, regs @ 0x%lx\n", pci_info->regs);
538 printf("no link, regs @ 0x%lx\n", pci_info->regs);
539 hose->last_busno = hose->first_busno;
543 out_be32(&pci->pme_msg_det, 0xffffffff);
544 out_be32(&pci->pme_msg_int_en, 0xffffffff);
546 /* Print the negotiated PCIe link width */
547 pci_hose_read_config_word(hose, dev, pci_lsr, &temp16);
548 printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
549 (temp16 & 0xf), pci_info->regs);
551 hose->current_busno++; /* Start scan with secondary */
552 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
555 #ifdef CONFIG_SYS_FSL_ERRATUM_A007815
556 /* The Read-Only Write Enable bit defaults to 1 instead of 0.
557 * Set to 0 to protect the read-only registers.
559 clrbits_be32(&pci->dbi_ro_wr_en, 0x01);
562 /* Use generic setup_device to initialize standard pci regs,
563 * but do not allocate any windows since any BAR found (such
564 * as PCSRBAR) is not in this cpu's memory space.
566 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
567 hose->pci_prefetch, hose->pci_io);
570 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
571 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
572 temp16 | PCI_COMMAND_MEMORY);
575 #ifndef CONFIG_PCI_NOSCAN
576 if (!fsl_is_pci_agent(hose)) {
577 debug(" Scanning PCI bus %02x\n",
578 hose->current_busno);
579 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
581 debug(" Not scanning PCI bus %02x. PI=%x\n",
582 hose->current_busno, temp8);
583 hose->last_busno = hose->current_busno;
586 /* if we are PCIe - update limit regs and subordinate busno
587 * for the virtual P2P bridge
589 if (pcie_cap == PCI_CAP_ID_EXP) {
590 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
593 hose->last_busno = hose->current_busno;
596 /* Clear all error indications */
597 if (pcie_cap == PCI_CAP_ID_EXP)
598 out_be32(&pci->pme_msg_det, 0xffffffff);
599 out_be32(&pci->pedr, 0xffffffff);
601 pci_hose_read_config_word(hose, dev, pci_dsr, &temp16);
603 pci_hose_write_config_word(hose, dev, pci_dsr, 0xffff);
606 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
608 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
612 int fsl_is_pci_agent(struct pci_controller *hose)
616 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
618 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
619 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
620 if (pcie_cap == PCI_CAP_ID_EXP) {
623 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE,
625 return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
629 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
630 /* Programming Interface (PCI_CLASS_PROG)
631 * 0 == pci host or pcie root-complex,
632 * 1 == pci agent or pcie end-point
634 return (prog_if == FSL_PROG_IF_AGENT);
638 int fsl_pci_init_port(struct fsl_pci_info *pci_info,
639 struct pci_controller *hose, int busno)
641 volatile ccsr_fsl_pci_t *pci;
642 struct pci_region *r;
643 pci_dev_t dev = PCI_BDF(busno,0,0);
647 pci = (ccsr_fsl_pci_t *) pci_info->regs;
649 /* on non-PCIe controllers we don't have pme_msg_det so this code
650 * should do nothing since the read will return 0
652 if (in_be32(&pci->pme_msg_det)) {
653 out_be32(&pci->pme_msg_det, 0xffffffff);
654 debug (" with errors. Clearing. Now 0x%08x",
658 r = hose->regions + hose->region_count;
660 /* outbound memory */
674 hose->region_count = r - hose->regions;
675 hose->first_busno = busno;
677 fsl_pci_init(hose, pci_info);
679 if (fsl_is_pci_agent(hose)) {
680 fsl_pci_config_unlock(hose);
681 hose->last_busno = hose->first_busno;
682 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
684 /* boot from PCIE --master releases slave's core 0 */
685 char *s = env_get("bootmaster");
687 sprintf(pcie, "PCIE%d", pci_info->pci_num);
689 if (s && (strcmp(s, pcie) == 0))
690 fsl_pcie_boot_master_release_slave(pci_info->pci_num);
694 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
695 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
696 printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
697 "e" : "", pci_info->pci_num,
698 hose->first_busno, hose->last_busno);
699 return(hose->last_busno + 1);
702 /* Enable inbound PCI config cycles for agent/endpoint interface */
703 void fsl_pci_config_unlock(struct pci_controller *hose)
705 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
710 if (!fsl_is_pci_agent(hose))
713 pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
714 pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
715 if (pcie_cap != 0x0) {
716 ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr;
717 u32 block_rev = in_be32(&pci->block_rev1);
718 /* PCIe - set CFG_READY bit of Configuration Ready Register */
719 if (block_rev >= PEX_IP_BLK_REV_3_0)
720 setbits_be32(&pci->config, FSL_PCIE_V3_CFG_RDY);
722 pci_hose_write_config_byte(hose, dev,
723 FSL_PCIE_CFG_RDY, 0x1);
725 /* PCI - clear ACL bit of PBFR */
726 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
728 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
732 #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || \
733 defined(CONFIG_PCIE3) || defined(CONFIG_PCIE4)
734 int fsl_configure_pcie(struct fsl_pci_info *info,
735 struct pci_controller *hose,
736 const char *connected, int busno)
740 set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
741 set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
743 is_endpoint = fsl_setup_hose(hose, info->regs);
744 printf("PCIe%u: %s", info->pci_num,
745 is_endpoint ? "Endpoint" : "Root Complex");
747 printf(" of %s", connected);
750 return fsl_pci_init_port(info, hose, busno);
753 #if defined(CONFIG_FSL_CORENET)
754 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
755 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR3_PCIE1
756 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR3_PCIE2
757 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR3_PCIE3
758 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR3_PCIE4
760 #define _DEVDISR_PCIE1 FSL_CORENET_DEVDISR_PCIE1
761 #define _DEVDISR_PCIE2 FSL_CORENET_DEVDISR_PCIE2
762 #define _DEVDISR_PCIE3 FSL_CORENET_DEVDISR_PCIE3
763 #define _DEVDISR_PCIE4 FSL_CORENET_DEVDISR_PCIE4
765 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
766 #elif defined(CONFIG_MPC85xx)
767 #define _DEVDISR_PCIE1 MPC85xx_DEVDISR_PCIE
768 #define _DEVDISR_PCIE2 MPC85xx_DEVDISR_PCIE2
769 #define _DEVDISR_PCIE3 MPC85xx_DEVDISR_PCIE3
770 #define _DEVDISR_PCIE4 0
771 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR
772 #elif defined(CONFIG_MPC86xx)
773 #define _DEVDISR_PCIE1 MPC86xx_DEVDISR_PCIE1
774 #define _DEVDISR_PCIE2 MPC86xx_DEVDISR_PCIE2
775 #define _DEVDISR_PCIE3 0
776 #define _DEVDISR_PCIE4 0
777 #define CONFIG_SYS_MPC8xxx_GUTS_ADDR \
778 (&((immap_t *)CONFIG_SYS_IMMR)->im_gur)
780 #error "No defines for DEVDISR_PCIE"
783 /* Implement a dummy function for those platforms w/o SERDES */
784 static const char *__board_serdes_name(enum srds_prtcl device)
787 #ifdef CONFIG_SYS_PCIE1_NAME
789 return CONFIG_SYS_PCIE1_NAME;
791 #ifdef CONFIG_SYS_PCIE2_NAME
793 return CONFIG_SYS_PCIE2_NAME;
795 #ifdef CONFIG_SYS_PCIE3_NAME
797 return CONFIG_SYS_PCIE3_NAME;
799 #ifdef CONFIG_SYS_PCIE4_NAME
801 return CONFIG_SYS_PCIE4_NAME;
810 __attribute__((weak, alias("__board_serdes_name"))) const char *
811 board_serdes_name(enum srds_prtcl device);
813 static u32 devdisr_mask[] = {
820 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
821 struct fsl_pci_info *pci_info)
823 struct pci_controller *hose;
824 int num = dev - PCIE1;
826 hose = calloc(1, sizeof(struct pci_controller));
830 if (is_serdes_configured(dev) && !(devdisr & devdisr_mask[num])) {
831 busno = fsl_configure_pcie(pci_info, hose,
832 board_serdes_name(dev), busno);
834 printf("PCIe%d: disabled\n", num + 1);
840 int fsl_pcie_init_board(int busno)
842 struct fsl_pci_info pci_info;
843 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC8xxx_GUTS_ADDR;
847 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
848 addr = &gur->devdisr3;
850 addr = &gur->devdisr;
852 devdisr = in_be32(addr);
855 SET_STD_PCIE_INFO(pci_info, 1);
856 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE1, &pci_info);
858 setbits_be32(addr, _DEVDISR_PCIE1); /* disable */
862 SET_STD_PCIE_INFO(pci_info, 2);
863 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE2, &pci_info);
865 setbits_be32(addr, _DEVDISR_PCIE2); /* disable */
869 SET_STD_PCIE_INFO(pci_info, 3);
870 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE3, &pci_info);
872 setbits_be32(addr, _DEVDISR_PCIE3); /* disable */
876 SET_STD_PCIE_INFO(pci_info, 4);
877 busno = fsl_pcie_init_ctrl(busno, devdisr, PCIE4, &pci_info);
879 setbits_be32(addr, _DEVDISR_PCIE4); /* disable */
885 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
886 struct fsl_pci_info *pci_info)
891 int fsl_pcie_init_board(int busno)
897 #ifdef CONFIG_OF_BOARD_SETUP
898 #include <linux/libfdt.h>
899 #include <fdt_support.h>
901 void ft_fsl_pci_setup(void *blob, const char *pci_compat,
902 unsigned long ctrl_addr)
906 phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr;
907 struct pci_controller *hose;
909 hose = find_hose_by_cfg_addr((void *)(ctrl_addr));
911 /* convert ctrl_addr to true physical address */
912 p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR;
913 p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS;
915 off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr);
920 /* We assume a cfg_addr not being set means we didn't setup the controller */
921 if ((hose == NULL) || (hose->cfg_addr == NULL)) {
922 fdt_del_node(blob, off);
925 bus_range[1] = hose->last_busno - hose->first_busno;
926 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
927 fdt_pci_dma_ranges(blob, off, hose);