2 * Copyright 2007-2010 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 DECLARE_GLOBAL_DATA_PTR;
25 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
27 * Initialize controller and call the common driver/pci pci_hose_scan to
28 * scan for bridges and devices.
30 * Hose fields which need to be pre-initialized by board specific code:
40 #include <asm/fsl_pci.h>
42 /* Freescale-specific PCI config registers */
43 #define FSL_PCI_PBFR 0x44
44 #define FSL_PCIE_CAP_ID 0x4c
45 #define FSL_PCIE_CFG_RDY 0x4b0
46 #define FSL_PROG_IF_AGENT 0x1
48 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
49 pci_dev_t dev, int sub_bus);
50 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
51 pci_dev_t dev, int sub_bus);
52 void pciauto_config_init(struct pci_controller *hose);
54 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
55 #define CONFIG_SYS_PCI_MEMORY_BUS 0
58 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS
59 #define CONFIG_SYS_PCI_MEMORY_PHYS 0
62 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
63 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
66 /* Setup one inbound ATMU window.
68 * We let the caller decide what the window size should be
70 static void set_inbound_window(volatile pit_t *pi,
74 u32 sz = (__ilog2_u64(size) - 1);
75 u32 flag = PIWAR_EN | PIWAR_LOCAL |
76 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
78 out_be32(&pi->pitar, r->phys_start >> 12);
79 out_be32(&pi->piwbar, r->bus_start >> 12);
80 #ifdef CONFIG_SYS_PCI_64BIT
81 out_be32(&pi->piwbear, r->bus_start >> 44);
83 out_be32(&pi->piwbear, 0);
85 if (r->flags & PCI_REGION_PREFETCH)
87 out_be32(&pi->piwar, flag | sz);
90 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr)
92 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) addr;
94 /* Reset hose to make sure its in a clean state */
95 memset(hose, 0, sizeof(struct pci_controller));
97 pci_setup_indirect(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
99 return fsl_is_pci_agent(hose);
102 static int fsl_pci_setup_inbound_windows(struct pci_controller *hose,
103 u64 out_lo, u8 pcie_cap,
106 struct pci_region *r = hose->regions + hose->region_count;
107 u64 sz = min((u64)gd->ram_size, (1ull << 32));
109 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
110 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
113 /* we have no space available for inbound memory mapping */
114 if (bus_start > out_lo) {
115 printf ("no space for inbound mapping of memory\n");
120 if ((bus_start + sz) > out_lo) {
121 sz = out_lo - bus_start;
122 debug ("limiting size to %llx\n", sz);
125 pci_sz = 1ull << __ilog2_u64(sz);
127 * we can overlap inbound/outbound windows on PCI-E since RX & TX
130 if ((pcie_cap == PCI_CAP_ID_EXP) && (pci_sz < sz)) {
131 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
132 (u64)bus_start, (u64)phys_start, (u64)sz);
133 pci_set_region(r, bus_start, phys_start, sz,
134 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
135 PCI_REGION_PREFETCH);
137 /* if we aren't an exact power of two match, pci_sz is smaller
138 * round it up to the next power of two. We report the actual
139 * size to pci region tracking.
142 sz = 2ull << __ilog2_u64(sz);
144 set_inbound_window(pi--, r++, sz);
145 sz = 0; /* make sure we dont set the R2 window */
147 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
148 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
149 pci_set_region(r, bus_start, phys_start, pci_sz,
150 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
151 PCI_REGION_PREFETCH);
152 set_inbound_window(pi--, r++, pci_sz);
156 phys_start += pci_sz;
158 pci_sz = 1ull << __ilog2_u64(sz);
160 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
161 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
162 pci_set_region(r, bus_start, phys_start, pci_sz,
163 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
164 PCI_REGION_PREFETCH);
165 set_inbound_window(pi--, r++, pci_sz);
168 phys_start += pci_sz;
172 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
174 * On 64-bit capable systems, set up a mapping for all of DRAM
175 * in high pci address space.
177 pci_sz = 1ull << __ilog2_u64(gd->ram_size);
178 /* round up to the next largest power of two */
179 if (gd->ram_size > pci_sz)
180 pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
181 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
182 (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
183 (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
186 CONFIG_SYS_PCI64_MEMORY_BUS,
187 CONFIG_SYS_PCI_MEMORY_PHYS,
189 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
190 PCI_REGION_PREFETCH);
191 set_inbound_window(pi--, r++, pci_sz);
193 pci_sz = 1ull << __ilog2_u64(sz);
195 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
196 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
197 pci_set_region(r, bus_start, phys_start, pci_sz,
198 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY |
199 PCI_REGION_PREFETCH);
202 phys_start += pci_sz;
203 set_inbound_window(pi--, r++, pci_sz);
207 #ifdef CONFIG_PHYS_64BIT
208 if (sz && (((u64)gd->ram_size) < (1ull << 32)))
209 printf("Was not able to map all of memory via "
210 "inbound windows -- %lld remaining\n", sz);
213 hose->region_count = r - hose->regions;
218 void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data)
222 int enabled, r, inbound = 0;
225 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
226 struct pci_region *reg = hose->regions + hose->region_count;
227 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
229 /* Initialize ATMU registers based on hose regions and flags */
230 volatile pot_t *po = &pci->pot[1]; /* skip 0 */
231 volatile pit_t *pi = &pci->pit[2]; /* ranges from: 3 to 1 */
233 u64 out_hi = 0, out_lo = -1ULL;
234 u32 pcicsrbar, pcicsrbar_sz;
240 pci_setup_indirect(hose, cfg_addr, cfg_data);
242 /* Handle setup of outbound windows first */
243 for (r = 0; r < hose->region_count; r++) {
244 unsigned long flags = hose->regions[r].flags;
245 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
247 flags &= PCI_REGION_SYS_MEMORY|PCI_REGION_TYPE;
248 if (flags != PCI_REGION_SYS_MEMORY) {
249 u64 start = hose->regions[r].bus_start;
250 u64 end = start + hose->regions[r].size;
252 out_be32(&po->powbar, hose->regions[r].phys_start >> 12);
253 out_be32(&po->potar, start >> 12);
254 #ifdef CONFIG_SYS_PCI_64BIT
255 out_be32(&po->potear, start >> 44);
257 out_be32(&po->potear, 0);
259 if (hose->regions[r].flags & PCI_REGION_IO) {
260 out_be32(&po->powar, POWAR_EN | sz |
261 POWAR_IO_READ | POWAR_IO_WRITE);
263 out_be32(&po->powar, POWAR_EN | sz |
264 POWAR_MEM_READ | POWAR_MEM_WRITE);
265 out_lo = min(start, out_lo);
266 out_hi = max(end, out_hi);
271 debug("Outbound memory range: %llx:%llx\n", out_lo, out_hi);
273 /* setup PCSRBAR/PEXCSRBAR */
274 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
275 pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
276 pcicsrbar_sz = ~pcicsrbar_sz + 1;
278 if (out_hi < (0x100000000ull - pcicsrbar_sz) ||
279 (out_lo > 0x100000000ull))
280 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
282 pcicsrbar = (out_lo - pcicsrbar_sz) & -pcicsrbar_sz;
283 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, pcicsrbar);
285 out_lo = min(out_lo, (u64)pcicsrbar);
287 debug("PCICSRBAR @ 0x%x\n", pcicsrbar);
289 pci_set_region(reg++, pcicsrbar, CONFIG_SYS_CCSRBAR_PHYS,
290 pcicsrbar_sz, PCI_REGION_SYS_MEMORY);
291 hose->region_count++;
293 /* see if we are a PCIe or PCI controller */
294 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
297 inbound = fsl_pci_setup_inbound_windows(hose, out_lo, pcie_cap, pi);
299 for (r = 0; r < hose->region_count; r++)
300 debug("PCI reg:%d %016llx:%016llx %016llx %08x\n", r,
301 (u64)hose->regions[r].phys_start,
302 hose->regions[r].bus_start,
303 hose->regions[r].size,
304 hose->regions[r].flags);
306 pci_register_hose(hose);
307 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */
308 hose->current_busno = hose->first_busno;
310 out_be32(&pci->pedr, 0xffffffff); /* Clear any errors */
311 out_be32(&pci->peer, ~0x20140); /* Enable All Error Interupts except
312 * - Master abort (pci)
313 * - Master PERR (pci)
316 pci_hose_read_config_dword(hose, dev, PCI_DCR, &temp32);
317 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */
318 pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
320 if (pcie_cap == PCI_CAP_ID_EXP) {
321 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
322 enabled = ltssm >= PCI_LTSSM_L0;
324 #ifdef CONFIG_FSL_PCIE_RESET
327 debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm);
328 /* assert PCIe reset */
329 setbits_be32(&pci->pdb_stat, 0x08000000);
330 (void) in_be32(&pci->pdb_stat);
332 debug(" Asserting PCIe reset @%x = %x\n",
333 &pci->pdb_stat, in_be32(&pci->pdb_stat));
334 /* clear PCIe reset */
335 clrbits_be32(&pci->pdb_stat, 0x08000000);
337 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
338 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
341 debug("....PCIe link error. "
342 "LTSSM=0x%02x.\n", ltssm);
344 enabled = ltssm >= PCI_LTSSM_L0;
346 /* we need to re-write the bar0 since a reset will
349 pci_hose_write_config_dword(hose, dev,
350 PCI_BASE_ADDRESS_0, pcicsrbar);
355 debug("....PCIE link error. Skipping scan."
356 "LTSSM=0x%02x\n", ltssm);
357 hose->last_busno = hose->first_busno;
361 out_be32(&pci->pme_msg_det, 0xffffffff);
362 out_be32(&pci->pme_msg_int_en, 0xffffffff);
364 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
365 neg_link_w = (temp16 & 0x3f0 ) >> 4;
366 printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n",
369 hose->current_busno++; /* Start scan with secondary */
370 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
373 /* Use generic setup_device to initialize standard pci regs,
374 * but do not allocate any windows since any BAR found (such
375 * as PCSRBAR) is not in this cpu's memory space.
377 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
378 hose->pci_prefetch, hose->pci_io);
381 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
382 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
383 temp16 | PCI_COMMAND_MEMORY);
386 #ifndef CONFIG_PCI_NOSCAN
387 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8);
389 /* Programming Interface (PCI_CLASS_PROG)
390 * 0 == pci host or pcie root-complex,
391 * 1 == pci agent or pcie end-point
394 printf(" Scanning PCI bus %02x\n",
395 hose->current_busno);
396 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
398 debug(" Not scanning PCI bus %02x. PI=%x\n",
399 hose->current_busno, temp8);
400 hose->last_busno = hose->current_busno;
403 /* if we are PCIe - update limit regs and subordinate busno
404 * for the virtual P2P bridge
406 if (pcie_cap == PCI_CAP_ID_EXP) {
407 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
410 hose->last_busno = hose->current_busno;
413 /* Clear all error indications */
414 if (pcie_cap == PCI_CAP_ID_EXP)
415 out_be32(&pci->pme_msg_det, 0xffffffff);
416 out_be32(&pci->pedr, 0xffffffff);
418 pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
420 pci_hose_write_config_word(hose, dev, PCI_DSR, 0xffff);
423 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
425 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
429 int fsl_is_pci_agent(struct pci_controller *hose)
432 pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
434 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prog_if);
436 return (prog_if == FSL_PROG_IF_AGENT);
439 int fsl_pci_init_port(struct fsl_pci_info *pci_info,
440 struct pci_controller *hose, int busno)
442 volatile ccsr_fsl_pci_t *pci;
443 struct pci_region *r;
445 pci = (ccsr_fsl_pci_t *) pci_info->regs;
447 /* on non-PCIe controllers we don't have pme_msg_det so this code
448 * should do nothing since the read will return 0
450 if (in_be32(&pci->pme_msg_det)) {
451 out_be32(&pci->pme_msg_det, 0xffffffff);
452 debug (" with errors. Clearing. Now 0x%08x",
456 r = hose->regions + hose->region_count;
458 /* outbound memory */
472 hose->region_count = r - hose->regions;
473 hose->first_busno = busno;
475 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
477 if (fsl_is_pci_agent(hose)) {
478 fsl_pci_config_unlock(hose);
479 hose->last_busno = hose->first_busno;
482 printf(" PCIE%x on bus %02x - %02x\n", pci_info->pci_num,
483 hose->first_busno, hose->last_busno);
485 return(hose->last_busno + 1);
488 /* Enable inbound PCI config cycles for agent/endpoint interface */
489 void fsl_pci_config_unlock(struct pci_controller *hose)
491 pci_dev_t dev = PCI_BDF(hose->first_busno,0,0);
496 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &agent);
500 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
501 if (pcie_cap != 0x0) {
502 /* PCIe - set CFG_READY bit of Configuration Ready Register */
503 pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
505 /* PCI - clear ACL bit of PBFR */
506 pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
508 pci_hose_write_config_word(hose, dev, FSL_PCI_PBFR, pbfr);
512 #ifdef CONFIG_OF_BOARD_SETUP
514 #include <fdt_support.h>
516 void ft_fsl_pci_setup(void *blob, const char *pci_compat,
517 struct pci_controller *hose, unsigned long ctrl_addr)
521 phys_addr_t p_ctrl_addr = (phys_addr_t)ctrl_addr;
523 /* convert ctrl_addr to true physical address */
524 p_ctrl_addr = (phys_addr_t)ctrl_addr - CONFIG_SYS_CCSRBAR;
525 p_ctrl_addr += CONFIG_SYS_CCSRBAR_PHYS;
527 off = fdt_node_offset_by_compat_reg(blob, pci_compat, p_ctrl_addr);
532 /* We assume a cfg_addr not being set means we didn't setup the controller */
533 if ((hose == NULL) || (hose->cfg_addr == NULL)) {
534 fdt_del_node(blob, off);
537 bus_range[1] = hose->last_busno - hose->first_busno;
538 fdt_setprop(blob, off, "bus-range", &bus_range[0], 2*4);
539 fdt_pci_dma_ranges(blob, off, hose);