2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 DECLARE_GLOBAL_DATA_PTR;
24 * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
26 * Initialize controller and call the common driver/pci pci_hose_scan to
27 * scan for bridges and devices.
29 * Hose fields which need to be pre-initialized by board specific code:
38 #include <asm/immap_fsl_pci.h>
40 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
41 pci_dev_t dev, int sub_bus);
42 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
43 pci_dev_t dev, int sub_bus);
44 void pciauto_config_init(struct pci_controller *hose);
46 #ifndef CONFIG_SYS_PCI_MEMORY_BUS
47 #define CONFIG_SYS_PCI_MEMORY_BUS 0
50 #ifndef CONFIG_SYS_PCI_MEMORY_PHYS
51 #define CONFIG_SYS_PCI_MEMORY_PHYS 0
54 #if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
55 #define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
58 int fsl_pci_setup_inbound_windows(struct pci_region *r)
60 struct pci_region *rgn_base = r;
61 u64 sz = min((u64)gd->ram_size, 1ull << 32);
63 phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
64 pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
65 pci_size_t pci_sz = 1ull << __ilog2_u64(sz);
67 debug ("R0 bus_start: %llx phys_start: %llx size: %llx\n",
68 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
69 pci_set_region(r++, bus_start, phys_start, pci_sz,
70 PCI_REGION_MEM | PCI_REGION_MEMORY | \
77 pci_sz = 1ull << __ilog2_u64(sz);
79 debug ("R1 bus_start: %llx phys_start: %llx size: %llx\n",
80 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
81 pci_set_region(r++, bus_start, phys_start, pci_sz,
82 PCI_REGION_MEM | PCI_REGION_MEMORY | \
89 #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
90 pci_sz = 1ull << __ilog2_u64(gd->ram_size);
91 /* round up to the next largest power of two */
92 if (gd->ram_size > pci_sz)
93 sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
94 debug ("R64 bus_start: %llx phys_start: %llx size: %llx\n",
95 (u64)CONFIG_SYS_PCI_MEMORY_BUS,
96 (u64)CONFIG_SYS_PCI_MEMORY_PHYS,
99 CONFIG_SYS_PCI_MEMORY_BUS,
100 CONFIG_SYS_PCI_MEMORY_PHYS,
102 PCI_REGION_MEM | PCI_REGION_MEMORY | \
103 PCI_REGION_PREFETCH);
105 pci_sz = 1ull << __ilog2_u64(sz);
107 debug ("R2 bus_start: %llx phys_start: %llx size: %llx\n",
108 (u64)bus_start, (u64)phys_start, (u64)pci_sz);
109 pci_set_region(r++, bus_start, phys_start, pci_sz,
110 PCI_REGION_MEM | PCI_REGION_MEMORY | \
111 PCI_REGION_PREFETCH);
114 phys_start += pci_sz;
118 if (sz && (((u64)gd->ram_size) < (1ull << 32)))
119 printf("Was not able to map all of memory via "
120 "inbound windows -- %lld remaining\n", sz);
125 void fsl_pci_init(struct pci_controller *hose)
129 int busno = hose->first_busno;
136 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr;
137 pci_dev_t dev = PCI_BDF(busno,0,0);
139 /* Initialize ATMU registers based on hose regions and flags */
140 volatile pot_t *po = &pci->pot[1]; /* skip 0 */
141 volatile pit_t *pi = &pci->pit[0]; /* ranges from: 3 to 1 */
147 for (r=0; r<hose->region_count; r++) {
148 u32 sz = (__ilog2_u64((u64)hose->regions[r].size) - 1);
149 if (hose->regions[r].flags & PCI_REGION_MEMORY) { /* inbound */
150 u32 flag = PIWAR_EN | PIWAR_LOCAL | \
151 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
152 pi->pitar = (hose->regions[r].phys_start >> 12);
153 pi->piwbar = (hose->regions[r].bus_start >> 12);
154 #ifdef CONFIG_SYS_PCI_64BIT
155 pi->piwbear = (hose->regions[r].bus_start >> 44);
159 if (hose->regions[r].flags & PCI_REGION_PREFETCH)
161 pi->piwar = flag | sz;
163 inbound = hose->regions[r].size > 0;
164 } else { /* Outbound */
165 po->powbar = (hose->regions[r].phys_start >> 12);
166 po->potar = (hose->regions[r].bus_start >> 12);
167 #ifdef CONFIG_SYS_PCI_64BIT
168 po->potear = (hose->regions[r].bus_start >> 44);
172 if (hose->regions[r].flags & PCI_REGION_IO)
173 po->powar = POWAR_EN | sz | \
174 POWAR_IO_READ | POWAR_IO_WRITE;
176 po->powar = POWAR_EN | sz | \
177 POWAR_MEM_READ | POWAR_MEM_WRITE;
182 pci_register_hose(hose);
183 pciauto_config_init(hose); /* grab pci_{mem,prefetch,io} */
184 hose->current_busno = hose->first_busno;
186 pci->pedr = 0xffffffff; /* Clear any errors */
187 pci->peer = ~0x20140; /* Enable All Error Interupts except
188 * - Master abort (pci)
189 * - Master PERR (pci)
192 pci_hose_read_config_dword (hose, dev, PCI_DCR, &temp32);
193 temp32 |= 0xf000e; /* set URR, FER, NFER (but not CER) */
194 pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
196 pci_hose_read_config_byte (hose, dev, PCI_HEADER_TYPE, &temp8);
197 bridge = temp8 & PCI_HEADER_TYPE_BRIDGE; /* Bridge, such as pcie */
201 pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
202 enabled = ltssm >= PCI_LTSSM_L0;
204 #ifdef CONFIG_FSL_PCIE_RESET
207 debug("....PCIe link error. "
208 "LTSSM=0x%02x.", ltssm);
209 pci->pdb_stat |= 0x08000000; /* assert PCIe reset */
210 temp32 = pci->pdb_stat;
212 debug(" Asserting PCIe reset @%x = %x\n",
213 &pci->pdb_stat, pci->pdb_stat);
214 pci->pdb_stat &= ~0x08000000; /* clear reset */
216 for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
217 pci_hose_read_config_word(hose, dev, PCI_LTSSM,
220 debug("....PCIe link error. "
221 "LTSSM=0x%02x.\n", ltssm);
223 enabled = ltssm >= PCI_LTSSM_L0;
228 debug("....PCIE link error. Skipping scan."
229 "LTSSM=0x%02x\n", ltssm);
230 hose->last_busno = hose->first_busno;
234 pci->pme_msg_det = 0xffffffff;
235 pci->pme_msg_int_en = 0xffffffff;
237 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
238 neg_link_w = (temp16 & 0x3f0 ) >> 4;
239 printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n",
242 hose->current_busno++; /* Start scan with secondary */
243 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
247 /* Use generic setup_device to initialize standard pci regs,
248 * but do not allocate any windows since any BAR found (such
249 * as PCSRBAR) is not in this cpu's memory space.
252 pciauto_setup_device(hose, dev, 0, hose->pci_mem,
253 hose->pci_prefetch, hose->pci_io);
256 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &temp16);
257 pci_hose_write_config_word(hose, dev, PCI_COMMAND,
258 temp16 | PCI_COMMAND_MEMORY);
261 #ifndef CONFIG_PCI_NOSCAN
262 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &temp8);
264 /* Programming Interface (PCI_CLASS_PROG)
265 * 0 == pci host or pcie root-complex,
266 * 1 == pci agent or pcie end-point
269 printf(" Scanning PCI bus %02x\n",
270 hose->current_busno);
271 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
273 debug(" Not scanning PCI bus %02x. PI=%x\n",
274 hose->current_busno, temp8);
275 hose->last_busno = hose->current_busno;
278 if ( bridge ) { /* update limit regs and subordinate busno */
279 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
282 hose->last_busno = hose->current_busno;
285 /* Clear all error indications */
288 pci->pme_msg_det = 0xffffffff;
289 pci->pedr = 0xffffffff;
291 pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
293 pci_hose_write_config_word(hose, dev,
297 pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
299 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);