drivers/pci/dwc/pci-dra7xx.c

   1 /*
   2  * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
   3  *
   4  * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Kishon Vijay Abraham I <kishon@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/err.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16 #include <linux/irqdomain.h>
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/of_pci.h>
  21 #include <linux/pci.h>
  22 #include <linux/phy/phy.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/resource.h>
  26 #include <linux/types.h>
  27
  28 #include "pcie-designware.h"
  29
  30 /* PCIe controller wrapper DRA7XX configuration registers */
  31
  32 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN             0x0024
  33 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN         0x0028
  34 #define ERR_SYS                                         BIT(0)
  35 #define ERR_FATAL                                       BIT(1)
  36 #define ERR_NONFATAL                                    BIT(2)
  37 #define ERR_COR                                         BIT(3)
  38 #define ERR_AXI                                         BIT(4)
  39 #define ERR_ECRC                                        BIT(5)
  40 #define PME_TURN_OFF                                    BIT(8)
  41 #define PME_TO_ACK                                      BIT(9)
  42 #define PM_PME                                          BIT(10)
  43 #define LINK_REQ_RST                                    BIT(11)
  44 #define LINK_UP_EVT                                     BIT(12)
  45 #define CFG_BME_EVT                                     BIT(13)
  46 #define CFG_MSE_EVT                                     BIT(14)
  47 #define INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \
  48                         ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \
  49                         LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT)
  50
  51 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI              0x0034
  52 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI          0x0038
  53 #define INTA                                            BIT(0)
  54 #define INTB                                            BIT(1)
  55 #define INTC                                            BIT(2)
  56 #define INTD                                            BIT(3)
  57 #define MSI                                             BIT(4)
  58 #define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)
  59
  60 #define PCIECTRL_DRA7XX_CONF_DEVICE_CMD                 0x0104
  61 #define LTSSM_EN                                        0x1
  62
  63 #define PCIECTRL_DRA7XX_CONF_PHY_CS                     0x010C
  64 #define LINK_UP                                         BIT(16)
  65 #define DRA7XX_CPU_TO_BUS_ADDR                          0x0FFFFFFF
  66
  67 #define EXP_CAP_ID_OFFSET                               0x70
  68
  69 struct dra7xx_pcie {
  70         struct pcie_port        pp;
  71         void __iomem            *base;          /* DT ti_conf */
  72         int                     phy_count;      /* DT phy-names count */
  73         struct phy              **phy;
  74         int                     link_gen;
  75         struct irq_domain       *irq_domain;
  76 };
  77
  78 #define to_dra7xx_pcie(x)       container_of((x), struct dra7xx_pcie, pp)
  79
  80 static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
  81 {
  82         return readl(pcie->base + offset);
  83 }
  84
  85 static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
  86                                       u32 value)
  87 {
  88         writel(value, pcie->base + offset);
  89 }
  90
  91 static int dra7xx_pcie_link_up(struct pcie_port *pp)
  92 {
  93         struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
  94         u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
  95
  96         return !!(reg & LINK_UP);
  97 }
  98
  99 static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx)
 100 {
 101         struct pcie_port *pp = &dra7xx->pp;
 102         struct device *dev = pp->dev;
 103         u32 reg;
 104         u32 exp_cap_off = EXP_CAP_ID_OFFSET;
 105
 106         if (dw_pcie_link_up(pp)) {
 107                 dev_err(dev, "link is already up\n");
 108                 return 0;
 109         }
 110
 111         if (dra7xx->link_gen == 1) {
 112                 dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
 113                                  4, &reg);
 114                 if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
 115                         reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
 116                         reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
 117                         dw_pcie_cfg_write(pp->dbi_base + exp_cap_off +
 118                                           PCI_EXP_LNKCAP, 4, reg);
 119                 }
 120
 121                 dw_pcie_cfg_read(pp->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
 122                                  2, &reg);
 123                 if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
 124                         reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
 125                         reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
 126                         dw_pcie_cfg_write(pp->dbi_base + exp_cap_off +
 127                                           PCI_EXP_LNKCTL2, 2, reg);
 128                 }
 129         }
 130
 131         reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
 132         reg |= LTSSM_EN;
 133         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
 134
 135         return dw_pcie_wait_for_link(pp);
 136 }
 137
 138 static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
 139 {
 140         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
 141                            ~INTERRUPTS);
 142         dra7xx_pcie_writel(dra7xx,
 143                            PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, INTERRUPTS);
 144         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
 145                            ~LEG_EP_INTERRUPTS & ~MSI);
 146         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
 147                            MSI | LEG_EP_INTERRUPTS);
 148 }
 149
 150 static void dra7xx_pcie_host_init(struct pcie_port *pp)
 151 {
 152         struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
 153
 154         pp->io_base &= DRA7XX_CPU_TO_BUS_ADDR;
 155         pp->mem_base &= DRA7XX_CPU_TO_BUS_ADDR;
 156         pp->cfg0_base &= DRA7XX_CPU_TO_BUS_ADDR;
 157         pp->cfg1_base &= DRA7XX_CPU_TO_BUS_ADDR;
 158
 159         dw_pcie_setup_rc(pp);
 160
 161         dra7xx_pcie_establish_link(dra7xx);
 162         dw_pcie_msi_init(pp);
 163         dra7xx_pcie_enable_interrupts(dra7xx);
 164 }
 165
 166 static struct pcie_host_ops dra7xx_pcie_host_ops = {
 167         .link_up = dra7xx_pcie_link_up,
 168         .host_init = dra7xx_pcie_host_init,
 169 };
 170
 171 static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
 172                                 irq_hw_number_t hwirq)
 173 {
 174         irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
 175         irq_set_chip_data(irq, domain->host_data);
 176
 177         return 0;
 178 }
 179
 180 static const struct irq_domain_ops intx_domain_ops = {
 181         .map = dra7xx_pcie_intx_map,
 182 };
 183
 184 static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
 185 {
 186         struct device *dev = pp->dev;
 187         struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pp);
 188         struct device_node *node = dev->of_node;
 189         struct device_node *pcie_intc_node =  of_get_next_child(node, NULL);
 190
 191         if (!pcie_intc_node) {
 192                 dev_err(dev, "No PCIe Intc node found\n");
 193                 return -ENODEV;
 194         }
 195
 196         dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
 197                                                    &intx_domain_ops, pp);
 198         if (!dra7xx->irq_domain) {
 199                 dev_err(dev, "Failed to get a INTx IRQ domain\n");
 200                 return -ENODEV;
 201         }
 202
 203         return 0;
 204 }
 205
 206 static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
 207 {
 208         struct dra7xx_pcie *dra7xx = arg;
 209         struct pcie_port *pp = &dra7xx->pp;
 210         u32 reg;
 211
 212         reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
 213
 214         switch (reg) {
 215         case MSI:
 216                 dw_handle_msi_irq(pp);
 217                 break;
 218         case INTA:
 219         case INTB:
 220         case INTC:
 221         case INTD:
 222                 generic_handle_irq(irq_find_mapping(dra7xx->irq_domain,
 223                                                     ffs(reg)));
 224                 break;
 225         }
 226
 227         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
 228
 229         return IRQ_HANDLED;
 230 }
 231
 232
 233 static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
 234 {
 235         struct dra7xx_pcie *dra7xx = arg;
 236         struct device *dev = dra7xx->pp.dev;
 237         u32 reg;
 238
 239         reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
 240
 241         if (reg & ERR_SYS)
 242                 dev_dbg(dev, "System Error\n");
 243
 244         if (reg & ERR_FATAL)
 245                 dev_dbg(dev, "Fatal Error\n");
 246
 247         if (reg & ERR_NONFATAL)
 248                 dev_dbg(dev, "Non Fatal Error\n");
 249
 250         if (reg & ERR_COR)
 251                 dev_dbg(dev, "Correctable Error\n");
 252
 253         if (reg & ERR_AXI)
 254                 dev_dbg(dev, "AXI tag lookup fatal Error\n");
 255
 256         if (reg & ERR_ECRC)
 257                 dev_dbg(dev, "ECRC Error\n");
 258
 259         if (reg & PME_TURN_OFF)
 260                 dev_dbg(dev,
 261                         "Power Management Event Turn-Off message received\n");
 262
 263         if (reg & PME_TO_ACK)
 264                 dev_dbg(dev,
 265                         "Power Management Turn-Off Ack message received\n");
 266
 267         if (reg & PM_PME)
 268                 dev_dbg(dev, "PM Power Management Event message received\n");
 269
 270         if (reg & LINK_REQ_RST)
 271                 dev_dbg(dev, "Link Request Reset\n");
 272
 273         if (reg & LINK_UP_EVT)
 274                 dev_dbg(dev, "Link-up state change\n");
 275
 276         if (reg & CFG_BME_EVT)
 277                 dev_dbg(dev, "CFG 'Bus Master Enable' change\n");
 278
 279         if (reg & CFG_MSE_EVT)
 280                 dev_dbg(dev, "CFG 'Memory Space Enable' change\n");
 281
 282         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
 283
 284         return IRQ_HANDLED;
 285 }
 286
 287 static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
 288                                        struct platform_device *pdev)
 289 {
 290         int ret;
 291         struct pcie_port *pp = &dra7xx->pp;
 292         struct device *dev = pp->dev;
 293         struct resource *res;
 294
 295         pp->irq = platform_get_irq(pdev, 1);
 296         if (pp->irq < 0) {
 297                 dev_err(dev, "missing IRQ resource\n");
 298                 return -EINVAL;
 299         }
 300
 301         ret = devm_request_irq(dev, pp->irq, dra7xx_pcie_msi_irq_handler,
 302                                IRQF_SHARED | IRQF_NO_THREAD,
 303                                "dra7-pcie-msi", dra7xx);
 304         if (ret) {
 305                 dev_err(dev, "failed to request irq\n");
 306                 return ret;
 307         }
 308
 309         ret = dra7xx_pcie_init_irq_domain(pp);
 310         if (ret < 0)
 311                 return ret;
 312
 313         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
 314         pp->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
 315         if (!pp->dbi_base)
 316                 return -ENOMEM;
 317
 318         ret = dw_pcie_host_init(pp);
 319         if (ret) {
 320                 dev_err(dev, "failed to initialize host\n");
 321                 return ret;
 322         }
 323
 324         return 0;
 325 }
 326
 327 static void dra7xx_pcie_disable_phy(struct dra7xx_pcie *dra7xx)
 328 {
 329         int phy_count = dra7xx->phy_count;
 330
 331         while (phy_count--) {
 332                 phy_power_off(dra7xx->phy[phy_count]);
 333                 phy_exit(dra7xx->phy[phy_count]);
 334         }
 335 }
 336
 337 static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx)
 338 {
 339         int phy_count = dra7xx->phy_count;
 340         int ret;
 341         int i;
 342
 343         for (i = 0; i < phy_count; i++) {
 344                 ret = phy_init(dra7xx->phy[i]);
 345                 if (ret < 0)
 346                         goto err_phy;
 347
 348                 ret = phy_power_on(dra7xx->phy[i]);
 349                 if (ret < 0) {
 350                         phy_exit(dra7xx->phy[i]);
 351                         goto err_phy;
 352                 }
 353         }
 354
 355         return 0;
 356
 357 err_phy:
 358         while (--i >= 0) {
 359                 phy_power_off(dra7xx->phy[i]);
 360                 phy_exit(dra7xx->phy[i]);
 361         }
 362
 363         return ret;
 364 }
 365
 366 static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 367 {
 368         u32 reg;
 369         int ret;
 370         int irq;
 371         int i;
 372         int phy_count;
 373         struct phy **phy;
 374         void __iomem *base;
 375         struct resource *res;
 376         struct dra7xx_pcie *dra7xx;
 377         struct pcie_port *pp;
 378         struct device *dev = &pdev->dev;
 379         struct device_node *np = dev->of_node;
 380         char name[10];
 381         struct gpio_desc *reset;
 382
 383         dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
 384         if (!dra7xx)
 385                 return -ENOMEM;
 386
 387         pp = &dra7xx->pp;
 388         pp->dev = dev;
 389         pp->ops = &dra7xx_pcie_host_ops;
 390
 391         irq = platform_get_irq(pdev, 0);
 392         if (irq < 0) {
 393                 dev_err(dev, "missing IRQ resource\n");
 394                 return -EINVAL;
 395         }
 396
 397         ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
 398                                IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
 399         if (ret) {
 400                 dev_err(dev, "failed to request irq\n");
 401                 return ret;
 402         }
 403
 404         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
 405         base = devm_ioremap_nocache(dev, res->start, resource_size(res));
 406         if (!base)
 407                 return -ENOMEM;
 408
 409         phy_count = of_property_count_strings(np, "phy-names");
 410         if (phy_count < 0) {
 411                 dev_err(dev, "unable to find the strings\n");
 412                 return phy_count;
 413         }
 414
 415         phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL);
 416         if (!phy)
 417                 return -ENOMEM;
 418
 419         for (i = 0; i < phy_count; i++) {
 420                 snprintf(name, sizeof(name), "pcie-phy%d", i);
 421                 phy[i] = devm_phy_get(dev, name);
 422                 if (IS_ERR(phy[i]))
 423                         return PTR_ERR(phy[i]);
 424         }
 425
 426         dra7xx->base = base;
 427         dra7xx->phy = phy;
 428         dra7xx->phy_count = phy_count;
 429
 430         ret = dra7xx_pcie_enable_phy(dra7xx);
 431         if (ret) {
 432                 dev_err(dev, "failed to enable phy\n");
 433                 return ret;
 434         }
 435
 436         platform_set_drvdata(pdev, dra7xx);
 437
 438         pm_runtime_enable(dev);
 439         ret = pm_runtime_get_sync(dev);
 440         if (ret < 0) {
 441                 dev_err(dev, "pm_runtime_get_sync failed\n");
 442                 goto err_get_sync;
 443         }
 444
 445         reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
 446         if (IS_ERR(reset)) {
 447                 ret = PTR_ERR(reset);
 448                 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
 449                 goto err_gpio;
 450         }
 451
 452         reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
 453         reg &= ~LTSSM_EN;
 454         dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
 455
 456         dra7xx->link_gen = of_pci_get_max_link_speed(np);
 457         if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2)
 458                 dra7xx->link_gen = 2;
 459
 460         ret = dra7xx_add_pcie_port(dra7xx, pdev);
 461         if (ret < 0)
 462                 goto err_gpio;
 463
 464         return 0;
 465
 466 err_gpio:
 467         pm_runtime_put(dev);
 468
 469 err_get_sync:
 470         pm_runtime_disable(dev);
 471         dra7xx_pcie_disable_phy(dra7xx);
 472
 473         return ret;
 474 }
 475
 476 #ifdef CONFIG_PM_SLEEP
 477 static int dra7xx_pcie_suspend(struct device *dev)
 478 {
 479         struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
 480         struct pcie_port *pp = &dra7xx->pp;
 481         u32 val;
 482
 483         /* clear MSE */
 484         val = dw_pcie_readl_rc(pp, PCI_COMMAND);
 485         val &= ~PCI_COMMAND_MEMORY;
 486         dw_pcie_writel_rc(pp, PCI_COMMAND, val);
 487
 488         return 0;
 489 }
 490
 491 static int dra7xx_pcie_resume(struct device *dev)
 492 {
 493         struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
 494         struct pcie_port *pp = &dra7xx->pp;
 495         u32 val;
 496
 497         /* set MSE */
 498         val = dw_pcie_readl_rc(pp, PCI_COMMAND);
 499         val |= PCI_COMMAND_MEMORY;
 500         dw_pcie_writel_rc(pp, PCI_COMMAND, val);
 501
 502         return 0;
 503 }
 504
 505 static int dra7xx_pcie_suspend_noirq(struct device *dev)
 506 {
 507         struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
 508
 509         dra7xx_pcie_disable_phy(dra7xx);
 510
 511         return 0;
 512 }
 513
 514 static int dra7xx_pcie_resume_noirq(struct device *dev)
 515 {
 516         struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
 517         int ret;
 518
 519         ret = dra7xx_pcie_enable_phy(dra7xx);
 520         if (ret) {
 521                 dev_err(dev, "failed to enable phy\n");
 522                 return ret;
 523         }
 524
 525         return 0;
 526 }
 527 #endif
 528
 529 static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
 530         SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
 531         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
 532                                       dra7xx_pcie_resume_noirq)
 533 };
 534
 535 static const struct of_device_id of_dra7xx_pcie_match[] = {
 536         { .compatible = "ti,dra7-pcie", },
 537         {},
 538 };
 539
 540 static struct platform_driver dra7xx_pcie_driver = {
 541         .driver = {
 542                 .name   = "dra7-pcie",
 543                 .of_match_table = of_dra7xx_pcie_match,
 544                 .suppress_bind_attrs = true,
 545                 .pm     = &dra7xx_pcie_pm_ops,
 546         },
 547 };
 548 builtin_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe);