2 * pcie-dra7xx - PCIe controller driver for TI DRA7xx SoCs
4 * Copyright (C) 2013-2014 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Kishon Vijay Abraham I <kishon@ti.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/err.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/irqdomain.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/of_device.h>
22 #include <linux/of_gpio.h>
23 #include <linux/of_pci.h>
24 #include <linux/pci.h>
25 #include <linux/phy/phy.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm_runtime.h>
28 #include <linux/resource.h>
29 #include <linux/types.h>
30 #include <linux/mfd/syscon.h>
31 #include <linux/regmap.h>
33 #include "pcie-designware.h"
35 /* PCIe controller wrapper DRA7XX configuration registers */
37 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN 0x0024
38 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN 0x0028
39 #define ERR_SYS BIT(0)
40 #define ERR_FATAL BIT(1)
41 #define ERR_NONFATAL BIT(2)
42 #define ERR_COR BIT(3)
43 #define ERR_AXI BIT(4)
44 #define ERR_ECRC BIT(5)
45 #define PME_TURN_OFF BIT(8)
46 #define PME_TO_ACK BIT(9)
47 #define PM_PME BIT(10)
48 #define LINK_REQ_RST BIT(11)
49 #define LINK_UP_EVT BIT(12)
50 #define CFG_BME_EVT BIT(13)
51 #define CFG_MSE_EVT BIT(14)
52 #define INTERRUPTS (ERR_SYS | ERR_FATAL | ERR_NONFATAL | ERR_COR | ERR_AXI | \
53 ERR_ECRC | PME_TURN_OFF | PME_TO_ACK | PM_PME | \
54 LINK_REQ_RST | LINK_UP_EVT | CFG_BME_EVT | CFG_MSE_EVT)
56 #define PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI 0x0034
57 #define PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI 0x0038
63 #define LEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)
65 #define PCIECTRL_TI_CONF_DEVICE_TYPE 0x0100
66 #define DEVICE_TYPE_EP 0x0
67 #define DEVICE_TYPE_LEG_EP 0x1
68 #define DEVICE_TYPE_RC 0x4
70 #define PCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104
73 #define PCIECTRL_DRA7XX_CONF_PHY_CS 0x010C
74 #define LINK_UP BIT(16)
75 #define DRA7XX_CPU_TO_BUS_ADDR 0x0FFFFFFF
77 #define EXP_CAP_ID_OFFSET 0x70
79 #define PCIECTRL_TI_CONF_INTX_ASSERT 0x0124
80 #define PCIECTRL_TI_CONF_INTX_DEASSERT 0x0128
82 #define PCIECTRL_TI_CONF_MSI_XMT 0x012c
83 #define MSI_REQ_GRANT BIT(0)
84 #define MSI_VECTOR_SHIFT 7
88 void __iomem *base; /* DT ti_conf */
89 int phy_count; /* DT phy-names count */
92 struct irq_domain *irq_domain;
93 enum dw_pcie_device_mode mode;
96 struct dra7xx_pcie_of_data {
97 enum dw_pcie_device_mode mode;
100 #define to_dra7xx_pcie(x) dev_get_drvdata((x)->dev)
102 static inline u32 dra7xx_pcie_readl(struct dra7xx_pcie *pcie, u32 offset)
104 return readl(pcie->base + offset);
107 static inline void dra7xx_pcie_writel(struct dra7xx_pcie *pcie, u32 offset,
110 writel(value, pcie->base + offset);
113 static u64 dra7xx_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr)
115 return pci_addr & DRA7XX_CPU_TO_BUS_ADDR;
118 static int dra7xx_pcie_link_up(struct dw_pcie *pci)
120 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
121 u32 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_PHY_CS);
123 return !!(reg & LINK_UP);
126 static void dra7xx_pcie_stop_link(struct dw_pcie *pci)
128 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
131 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
133 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
136 static int dra7xx_pcie_establish_link(struct dw_pcie *pci)
138 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
139 struct device *dev = pci->dev;
141 u32 exp_cap_off = EXP_CAP_ID_OFFSET;
143 if (dw_pcie_link_up(pci)) {
144 dev_err(dev, "link is already up\n");
148 if (dra7xx->link_gen == 1) {
149 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
151 if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
152 reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
153 reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
154 dw_pcie_write(pci->dbi_base + exp_cap_off +
155 PCI_EXP_LNKCAP, 4, reg);
158 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
160 if ((reg & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
161 reg &= ~((u32)PCI_EXP_LNKCAP_SLS);
162 reg |= PCI_EXP_LNKCAP_SLS_2_5GB;
163 dw_pcie_write(pci->dbi_base + exp_cap_off +
164 PCI_EXP_LNKCTL2, 2, reg);
168 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
170 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
175 static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx)
177 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
178 LEG_EP_INTERRUPTS | MSI);
180 dra7xx_pcie_writel(dra7xx,
181 PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
182 MSI | LEG_EP_INTERRUPTS);
185 static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx)
187 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
189 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN,
193 static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
195 dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
196 dra7xx_pcie_enable_msi_interrupts(dra7xx);
199 static int dra7xx_pcie_host_init(struct pcie_port *pp)
201 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
202 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
204 dw_pcie_setup_rc(pp);
206 dra7xx_pcie_establish_link(pci);
207 dw_pcie_wait_for_link(pci);
208 dw_pcie_msi_init(pp);
209 dra7xx_pcie_enable_interrupts(dra7xx);
214 static const struct dw_pcie_host_ops dra7xx_pcie_host_ops = {
215 .host_init = dra7xx_pcie_host_init,
218 static int dra7xx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
219 irq_hw_number_t hwirq)
221 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
222 irq_set_chip_data(irq, domain->host_data);
227 static const struct irq_domain_ops intx_domain_ops = {
228 .map = dra7xx_pcie_intx_map,
231 static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
233 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
234 struct device *dev = pci->dev;
235 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
236 struct device_node *node = dev->of_node;
237 struct device_node *pcie_intc_node = of_get_next_child(node, NULL);
239 if (!pcie_intc_node) {
240 dev_err(dev, "No PCIe Intc node found\n");
244 dra7xx->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
245 &intx_domain_ops, pp);
246 if (!dra7xx->irq_domain) {
247 dev_err(dev, "Failed to get a INTx IRQ domain\n");
254 static irqreturn_t dra7xx_pcie_msi_irq_handler(int irq, void *arg)
256 struct dra7xx_pcie *dra7xx = arg;
257 struct dw_pcie *pci = dra7xx->pci;
258 struct pcie_port *pp = &pci->pp;
261 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI);
265 dw_handle_msi_irq(pp);
271 generic_handle_irq(irq_find_mapping(dra7xx->irq_domain,
276 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI, reg);
281 static irqreturn_t dra7xx_pcie_irq_handler(int irq, void *arg)
283 struct dra7xx_pcie *dra7xx = arg;
284 struct dw_pcie *pci = dra7xx->pci;
285 struct device *dev = pci->dev;
286 struct dw_pcie_ep *ep = &pci->ep;
289 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN);
292 dev_dbg(dev, "System Error\n");
295 dev_dbg(dev, "Fatal Error\n");
297 if (reg & ERR_NONFATAL)
298 dev_dbg(dev, "Non Fatal Error\n");
301 dev_dbg(dev, "Correctable Error\n");
304 dev_dbg(dev, "AXI tag lookup fatal Error\n");
307 dev_dbg(dev, "ECRC Error\n");
309 if (reg & PME_TURN_OFF)
311 "Power Management Event Turn-Off message received\n");
313 if (reg & PME_TO_ACK)
315 "Power Management Turn-Off Ack message received\n");
318 dev_dbg(dev, "PM Power Management Event message received\n");
320 if (reg & LINK_REQ_RST)
321 dev_dbg(dev, "Link Request Reset\n");
323 if (reg & LINK_UP_EVT) {
324 if (dra7xx->mode == DW_PCIE_EP_TYPE)
325 dw_pcie_ep_linkup(ep);
326 dev_dbg(dev, "Link-up state change\n");
329 if (reg & CFG_BME_EVT)
330 dev_dbg(dev, "CFG 'Bus Master Enable' change\n");
332 if (reg & CFG_MSE_EVT)
333 dev_dbg(dev, "CFG 'Memory Space Enable' change\n");
335 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN, reg);
340 static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
342 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
343 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
346 for (bar = BAR_0; bar <= BAR_5; bar++)
347 dw_pcie_ep_reset_bar(pci, bar);
349 dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
352 static void dra7xx_pcie_raise_legacy_irq(struct dra7xx_pcie *dra7xx)
354 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_ASSERT, 0x1);
356 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_INTX_DEASSERT, 0x1);
359 static void dra7xx_pcie_raise_msi_irq(struct dra7xx_pcie *dra7xx,
364 reg = (interrupt_num - 1) << MSI_VECTOR_SHIFT;
365 reg |= MSI_REQ_GRANT;
366 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_MSI_XMT, reg);
369 static int dra7xx_pcie_raise_irq(struct dw_pcie_ep *ep,
370 enum pci_epc_irq_type type, u8 interrupt_num)
372 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
373 struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
376 case PCI_EPC_IRQ_LEGACY:
377 dra7xx_pcie_raise_legacy_irq(dra7xx);
379 case PCI_EPC_IRQ_MSI:
380 dra7xx_pcie_raise_msi_irq(dra7xx, interrupt_num);
383 dev_err(pci->dev, "UNKNOWN IRQ type\n");
389 static struct dw_pcie_ep_ops pcie_ep_ops = {
390 .ep_init = dra7xx_pcie_ep_init,
391 .raise_irq = dra7xx_pcie_raise_irq,
394 static int __init dra7xx_add_pcie_ep(struct dra7xx_pcie *dra7xx,
395 struct platform_device *pdev)
398 struct dw_pcie_ep *ep;
399 struct resource *res;
400 struct device *dev = &pdev->dev;
401 struct dw_pcie *pci = dra7xx->pci;
404 ep->ops = &pcie_ep_ops;
406 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics");
407 pci->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
411 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ep_dbics2");
412 pci->dbi_base2 = devm_ioremap(dev, res->start, resource_size(res));
416 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
420 ep->phys_base = res->start;
421 ep->addr_size = resource_size(res);
423 ret = dw_pcie_ep_init(ep);
425 dev_err(dev, "failed to initialize endpoint\n");
432 static int __init dra7xx_add_pcie_port(struct dra7xx_pcie *dra7xx,
433 struct platform_device *pdev)
436 struct dw_pcie *pci = dra7xx->pci;
437 struct pcie_port *pp = &pci->pp;
438 struct device *dev = pci->dev;
439 struct resource *res;
441 pp->irq = platform_get_irq(pdev, 1);
443 dev_err(dev, "missing IRQ resource\n");
447 ret = devm_request_irq(dev, pp->irq, dra7xx_pcie_msi_irq_handler,
448 IRQF_SHARED | IRQF_NO_THREAD,
449 "dra7-pcie-msi", dra7xx);
451 dev_err(dev, "failed to request irq\n");
455 ret = dra7xx_pcie_init_irq_domain(pp);
459 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rc_dbics");
460 pci->dbi_base = devm_ioremap(dev, res->start, resource_size(res));
464 pp->ops = &dra7xx_pcie_host_ops;
466 ret = dw_pcie_host_init(pp);
468 dev_err(dev, "failed to initialize host\n");
475 static const struct dw_pcie_ops dw_pcie_ops = {
476 .cpu_addr_fixup = dra7xx_pcie_cpu_addr_fixup,
477 .start_link = dra7xx_pcie_establish_link,
478 .stop_link = dra7xx_pcie_stop_link,
479 .link_up = dra7xx_pcie_link_up,
482 static void dra7xx_pcie_disable_phy(struct dra7xx_pcie *dra7xx)
484 int phy_count = dra7xx->phy_count;
486 while (phy_count--) {
487 phy_power_off(dra7xx->phy[phy_count]);
488 phy_exit(dra7xx->phy[phy_count]);
492 static int dra7xx_pcie_enable_phy(struct dra7xx_pcie *dra7xx)
494 int phy_count = dra7xx->phy_count;
498 for (i = 0; i < phy_count; i++) {
499 ret = phy_init(dra7xx->phy[i]);
503 ret = phy_power_on(dra7xx->phy[i]);
505 phy_exit(dra7xx->phy[i]);
514 phy_power_off(dra7xx->phy[i]);
515 phy_exit(dra7xx->phy[i]);
521 static const struct dra7xx_pcie_of_data dra7xx_pcie_rc_of_data = {
522 .mode = DW_PCIE_RC_TYPE,
525 static const struct dra7xx_pcie_of_data dra7xx_pcie_ep_of_data = {
526 .mode = DW_PCIE_EP_TYPE,
529 static const struct of_device_id of_dra7xx_pcie_match[] = {
531 .compatible = "ti,dra7-pcie",
532 .data = &dra7xx_pcie_rc_of_data,
535 .compatible = "ti,dra7-pcie-ep",
536 .data = &dra7xx_pcie_ep_of_data,
542 * dra7xx_pcie_ep_unaligned_memaccess: workaround for AM572x/AM571x Errata i870
543 * @dra7xx: the dra7xx device where the workaround should be applied
545 * Access to the PCIe slave port that are not 32-bit aligned will result
546 * in incorrect mapping to TLP Address and Byte enable fields. Therefore,
547 * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or
550 * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
552 static int dra7xx_pcie_ep_unaligned_memaccess(struct device *dev)
555 struct device_node *np = dev->of_node;
556 struct of_phandle_args args;
557 struct regmap *regmap;
559 regmap = syscon_regmap_lookup_by_phandle(np,
560 "ti,syscon-unaligned-access");
561 if (IS_ERR(regmap)) {
562 dev_dbg(dev, "can't get ti,syscon-unaligned-access\n");
566 ret = of_parse_phandle_with_fixed_args(np, "ti,syscon-unaligned-access",
569 dev_err(dev, "failed to parse ti,syscon-unaligned-access\n");
573 ret = regmap_update_bits(regmap, args.args[0], args.args[1],
576 dev_err(dev, "failed to enable unaligned access\n");
578 of_node_put(args.np);
583 static int __init dra7xx_pcie_probe(struct platform_device *pdev)
591 struct device_link **link;
593 struct resource *res;
595 struct dra7xx_pcie *dra7xx;
596 struct device *dev = &pdev->dev;
597 struct device_node *np = dev->of_node;
599 struct gpio_desc *reset;
600 const struct of_device_id *match;
601 const struct dra7xx_pcie_of_data *data;
602 enum dw_pcie_device_mode mode;
604 match = of_match_device(of_match_ptr(of_dra7xx_pcie_match), dev);
608 data = (struct dra7xx_pcie_of_data *)match->data;
609 mode = (enum dw_pcie_device_mode)data->mode;
611 dra7xx = devm_kzalloc(dev, sizeof(*dra7xx), GFP_KERNEL);
615 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
620 pci->ops = &dw_pcie_ops;
622 irq = platform_get_irq(pdev, 0);
624 dev_err(dev, "missing IRQ resource: %d\n", irq);
628 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ti_conf");
629 base = devm_ioremap_nocache(dev, res->start, resource_size(res));
633 phy_count = of_property_count_strings(np, "phy-names");
635 dev_err(dev, "unable to find the strings\n");
639 phy = devm_kzalloc(dev, sizeof(*phy) * phy_count, GFP_KERNEL);
643 link = devm_kzalloc(dev, sizeof(*link) * phy_count, GFP_KERNEL);
647 for (i = 0; i < phy_count; i++) {
648 snprintf(name, sizeof(name), "pcie-phy%d", i);
649 phy[i] = devm_phy_get(dev, name);
651 return PTR_ERR(phy[i]);
653 link[i] = device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS);
663 dra7xx->phy_count = phy_count;
665 ret = dra7xx_pcie_enable_phy(dra7xx);
667 dev_err(dev, "failed to enable phy\n");
671 platform_set_drvdata(pdev, dra7xx);
673 pm_runtime_enable(dev);
674 ret = pm_runtime_get_sync(dev);
676 dev_err(dev, "pm_runtime_get_sync failed\n");
680 reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
682 ret = PTR_ERR(reset);
683 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
687 reg = dra7xx_pcie_readl(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD);
689 dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_DEVICE_CMD, reg);
691 dra7xx->link_gen = of_pci_get_max_link_speed(np);
692 if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2)
693 dra7xx->link_gen = 2;
696 case DW_PCIE_RC_TYPE:
697 if (!IS_ENABLED(CONFIG_PCI_DRA7XX_HOST)) {
702 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
704 ret = dra7xx_add_pcie_port(dra7xx, pdev);
708 case DW_PCIE_EP_TYPE:
709 if (!IS_ENABLED(CONFIG_PCI_DRA7XX_EP)) {
714 dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
717 ret = dra7xx_pcie_ep_unaligned_memaccess(dev);
721 ret = dra7xx_add_pcie_ep(dra7xx, pdev);
726 dev_err(dev, "INVALID device type %d\n", mode);
730 ret = devm_request_irq(dev, irq, dra7xx_pcie_irq_handler,
731 IRQF_SHARED, "dra7xx-pcie-main", dra7xx);
733 dev_err(dev, "failed to request irq\n");
743 pm_runtime_disable(dev);
744 dra7xx_pcie_disable_phy(dra7xx);
748 device_link_del(link[i]);
753 #ifdef CONFIG_PM_SLEEP
754 static int dra7xx_pcie_suspend(struct device *dev)
756 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
757 struct dw_pcie *pci = dra7xx->pci;
760 if (dra7xx->mode != DW_PCIE_RC_TYPE)
764 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
765 val &= ~PCI_COMMAND_MEMORY;
766 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
771 static int dra7xx_pcie_resume(struct device *dev)
773 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
774 struct dw_pcie *pci = dra7xx->pci;
777 if (dra7xx->mode != DW_PCIE_RC_TYPE)
781 val = dw_pcie_readl_dbi(pci, PCI_COMMAND);
782 val |= PCI_COMMAND_MEMORY;
783 dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
788 static int dra7xx_pcie_suspend_noirq(struct device *dev)
790 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
792 dra7xx_pcie_disable_phy(dra7xx);
797 static int dra7xx_pcie_resume_noirq(struct device *dev)
799 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
802 ret = dra7xx_pcie_enable_phy(dra7xx);
804 dev_err(dev, "failed to enable phy\n");
812 static void dra7xx_pcie_shutdown(struct platform_device *pdev)
814 struct device *dev = &pdev->dev;
815 struct dra7xx_pcie *dra7xx = dev_get_drvdata(dev);
818 dra7xx_pcie_stop_link(dra7xx->pci);
820 ret = pm_runtime_put_sync(dev);
822 dev_dbg(dev, "pm_runtime_put_sync failed\n");
824 pm_runtime_disable(dev);
825 dra7xx_pcie_disable_phy(dra7xx);
828 static const struct dev_pm_ops dra7xx_pcie_pm_ops = {
829 SET_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend, dra7xx_pcie_resume)
830 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(dra7xx_pcie_suspend_noirq,
831 dra7xx_pcie_resume_noirq)
834 static struct platform_driver dra7xx_pcie_driver = {
837 .of_match_table = of_dra7xx_pcie_match,
838 .suppress_bind_attrs = true,
839 .pm = &dra7xx_pcie_pm_ops,
841 .shutdown = dra7xx_pcie_shutdown,
843 builtin_platform_driver_probe(dra7xx_pcie_driver, dra7xx_pcie_probe);