2 * PCIe host controller driver for Starfive JH7110 Soc.
4 * Based on pcie-altera.c, pcie-altera-msi.c.
6 * Copyright (C) Shanghai StarFive Technology Co., Ltd.
8 * Author: ke.zhu@starfivetech.com
10 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
11 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
12 * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
13 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
14 * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
15 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/interrupt.h>
21 #include <linux/irqchip/chained_irq.h>
22 #include <linux/mfd/syscon.h>
23 #include <linux/module.h>
24 #include <linux/msi.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_pci.h>
28 #include <linux/pci.h>
29 #include <linux/pinctrl/pinctrl.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/regmap.h>
33 #include <linux/reset.h>
34 #include <linux/slab.h>
37 #define PCIE_BASIC_STATUS 0x018
38 #define PCIE_CFGNUM 0x140
39 #define IMASK_LOCAL 0x180
40 #define ISTATUS_LOCAL 0x184
41 #define IMSI_ADDR 0x190
42 #define ISTATUS_MSI 0x194
43 #define CFG_SPACE 0x1000
44 #define GEN_SETTINGS 0x80
45 #define PCIE_PCI_IDS 0x9C
46 #define PCIE_WINROM 0xFC
47 #define PMSG_SUPPORT_RX 0x3F0
51 #define PLDA_EP_ENABLE 0
52 #define PLDA_RP_ENABLE 1
54 #define PLDA_LINK_UP 1
55 #define PLDA_LINK_DOWN 0
57 #define IDS_REVISION_ID 0x02
58 #define IDS_PCI_TO_PCI_BRIDGE 0x060400
59 #define IDS_CLASS_CODE_SHIFT 8
61 #define PLDA_DATA_LINK_ACTIVE BIT(5)
62 #define PREF_MEM_WIN_64_SUPPORT BIT(3)
63 #define PMSG_LTR_SUPPORT BIT(2)
64 #define PDLA_LINK_SPEED_GEN2 BIT(12)
65 #define PLDA_FUNCTION_DIS BIT(15)
66 #define PLDA_FUNC_NUM 4
67 #define PLDA_PHY_FUNC_SHIFT 9
69 #define XR3PCI_ATR_AXI4_SLV0 0x800
70 #define XR3PCI_ATR_SRC_ADDR_LOW 0x0
71 #define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
72 #define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
73 #define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
74 #define XR3PCI_ATR_TRSL_PARAM 0x10
75 #define XR3PCI_ATR_TABLE_OFFSET 0x20
76 #define XR3PCI_ATR_MAX_TABLE_NUM 8
78 #define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1
79 #define XR3PCI_ATR_SRC_ADDR_MASK 0xfffff000
80 #define XR3PCI_ATR_TRSL_ADDR_MASK 0xfffff000
81 #define XR3_PCI_ECAM_SIZE 28
82 #define XR3PCI_ATR_TRSL_DIR BIT(22)
83 /* IDs used in the XR3PCI_ATR_TRSL_PARAM */
84 #define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0
85 #define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1
87 #define CFGNUM_DEVFN_SHIFT 0
88 #define CFGNUM_BUS_SHIFT 8
89 #define CFGNUM_BE_SHIFT 16
90 #define CFGNUM_FBE_SHIFT 20
92 #define ECAM_BUS_SHIFT 20
93 #define ECAM_DEV_SHIFT 15
94 #define ECAM_FUNC_SHIFT 12
96 #define INT_AXI_POST_ERROR BIT(16)
97 #define INT_AXI_FETCH_ERROR BIT(17)
98 #define INT_AXI_DISCARD_ERROR BIT(18)
99 #define INT_PCIE_POST_ERROR BIT(20)
100 #define INT_PCIE_FETCH_ERROR BIT(21)
101 #define INT_PCIE_DISCARD_ERROR BIT(22)
102 #define INT_ERRORS (INT_AXI_POST_ERROR | INT_AXI_FETCH_ERROR | \
103 INT_AXI_DISCARD_ERROR | INT_PCIE_POST_ERROR | \
104 INT_PCIE_FETCH_ERROR | INT_PCIE_DISCARD_ERROR)
106 #define INTA_OFFSET 24
111 #define INT_MSI BIT(28)
112 #define INT_INTX_MASK (INTA | INTB | INTC | INTD)
113 #define INT_MASK (INT_INTX_MASK | INT_MSI | INT_ERRORS)
115 #define INT_PCI_MSI_NR 32
116 #define LINK_UP_MASK 0xff
118 #define PERST_DELAY_US 1000
121 #define STG_SYSCON_K_RP_NEP_SHIFT 0x8
122 #define STG_SYSCON_K_RP_NEP_MASK 0x100
123 #define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK 0x7FFF00
124 #define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 0x8
125 #define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK 0x7FFF
126 #define STG_SYSCON_AXI4_SLVL_AWFUNC_SHIFT 0x0
127 #define STG_SYSCON_CLKREQ_SHIFT 0x16
128 #define STG_SYSCON_CLKREQ_MASK 0x400000
129 #define STG_SYSCON_CKREF_SRC_SHIFT 0x12
130 #define STG_SYSCON_CKREF_SRC_MASK 0xC0000
132 #define PCI_DEV(d) (((d) >> 3) & 0x1f)
134 /* MSI information */
136 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
137 struct irq_domain *msi_domain;
138 struct irq_domain *inner_domain;
139 /* Protect bitmap variable */
144 struct platform_device *pdev;
145 void __iomem *reg_base;
146 void __iomem *config_base;
147 struct resource *cfg_res;
148 struct regmap *reg_syscon;
154 struct irq_domain *legacy_irq_domain;
155 struct pci_host_bridge *bridge;
157 struct reset_control *resets;
158 struct clk_bulk_data *clks;
161 struct pinctrl *pinctrl;
162 struct pinctrl_state *perst_state_def;
163 struct pinctrl_state *perst_state_active;
164 struct pinctrl_state *power_state_def;
165 struct pinctrl_state *power_state_active;
168 static inline void plda_writel(struct plda_pcie *pcie, const u32 value,
171 writel_relaxed(value, pcie->reg_base + reg);
174 static inline u32 plda_readl(struct plda_pcie *pcie, const u32 reg)
176 return readl_relaxed(pcie->reg_base + reg);
179 static bool plda_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn,
182 if (pci_is_root_bus(bus) && (devfn == 0) &&
183 (offset == PCI_BASE_ADDRESS_0))
189 static int _plda_pcie_config_read(struct plda_pcie *pcie, unsigned char busno,
190 unsigned int devfn, int where, int size,
195 addr = pcie->config_base;
196 addr += (busno << ECAM_BUS_SHIFT);
197 addr += (PCI_DEV(devfn) << ECAM_DEV_SHIFT);
198 addr += (PCI_FUNC(devfn) << ECAM_FUNC_SHIFT);
202 return PCIBIOS_DEVICE_NOT_FOUND;
206 *(unsigned char *)value = readb(addr);
209 *(unsigned short *)value = readw(addr);
212 *(unsigned int *)value = readl(addr);
215 return PCIBIOS_SET_FAILED;
218 return PCIBIOS_SUCCESSFUL;
221 int _plda_pcie_config_write(struct plda_pcie *pcie, unsigned char busno,
222 unsigned int devfn, int where, int size, u32 value)
226 addr = pcie->config_base;
227 addr += (busno << ECAM_BUS_SHIFT);
228 addr += (PCI_DEV(devfn) << ECAM_DEV_SHIFT);
229 addr += (PCI_FUNC(devfn) << ECAM_FUNC_SHIFT);
233 return PCIBIOS_DEVICE_NOT_FOUND;
246 return PCIBIOS_SET_FAILED;
249 return PCIBIOS_SUCCESSFUL;
252 static int plda_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
253 int where, int size, u32 *value)
255 struct plda_pcie *pcie = bus->sysdata;
257 return _plda_pcie_config_read(pcie, bus->number, devfn, where, size,
261 int plda_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
262 int where, int size, u32 value)
264 struct plda_pcie *pcie = bus->sysdata;
266 if (plda_pcie_hide_rc_bar(bus, devfn, where))
267 return PCIBIOS_BAD_REGISTER_NUMBER;
269 return _plda_pcie_config_write(pcie, bus->number, devfn, where, size,
273 static void plda_pcie_handle_msi_irq(struct plda_pcie *pcie)
275 struct plda_msi *msi = &pcie->msi;
278 unsigned long status = plda_readl(pcie, ISTATUS_MSI);
280 for_each_set_bit(bit, &status, INT_PCI_MSI_NR) {
281 /* Clear interrupts */
282 plda_writel(pcie, 1 << bit, ISTATUS_MSI);
284 virq = irq_find_mapping(msi->inner_domain, bit);
286 if (test_bit(bit, msi->used))
287 generic_handle_irq(virq);
289 dev_err(&pcie->pdev->dev,
290 "Unhandled MSI, MSI%d virq %d\n", bit,
293 dev_err(&pcie->pdev->dev, "Unexpected MSI, MSI%d\n",
297 plda_writel(pcie, INT_MSI, ISTATUS_LOCAL);
300 static void plda_pcie_handle_intx_irq(struct plda_pcie *pcie,
301 unsigned long status)
306 status >>= INTA_OFFSET;
308 for_each_set_bit(bit, &status, PCI_NUM_INTX) {
309 /* Clear interrupts */
310 plda_writel(pcie, 1 << (bit + INTA_OFFSET), ISTATUS_LOCAL);
312 virq = irq_find_mapping(pcie->legacy_irq_domain, bit);
314 generic_handle_irq(virq);
316 dev_err(&pcie->pdev->dev,
317 "plda_pcie_handle_intx_irq unexpected IRQ, INT%d\n", bit);
321 static void plda_pcie_handle_errors_irq(struct plda_pcie *pcie, u32 status)
323 if (status & INT_AXI_POST_ERROR)
324 dev_err(&pcie->pdev->dev, "AXI post error\n");
325 if (status & INT_AXI_FETCH_ERROR)
326 dev_err(&pcie->pdev->dev, "AXI fetch error\n");
327 if (status & INT_AXI_DISCARD_ERROR)
328 dev_err(&pcie->pdev->dev, "AXI discard error\n");
329 if (status & INT_PCIE_POST_ERROR)
330 dev_err(&pcie->pdev->dev, "PCIe post error\n");
331 if (status & INT_PCIE_FETCH_ERROR)
332 dev_err(&pcie->pdev->dev, "PCIe fetch error\n");
333 if (status & INT_PCIE_DISCARD_ERROR)
334 dev_err(&pcie->pdev->dev, "PCIe discard error\n");
336 plda_writel(pcie, INT_ERRORS, ISTATUS_LOCAL);
339 static void plda_pcie_isr(struct irq_desc *desc)
341 struct irq_chip *chip = irq_desc_get_chip(desc);
342 struct plda_pcie *pcie;
345 chained_irq_enter(chip, desc);
346 pcie = irq_desc_get_handler_data(desc);
348 status = plda_readl(pcie, ISTATUS_LOCAL);
349 while ((status = (plda_readl(pcie, ISTATUS_LOCAL) & INT_MASK))) {
350 if (status & INT_INTX_MASK)
351 plda_pcie_handle_intx_irq(pcie, status);
353 if (status & INT_MSI)
354 plda_pcie_handle_msi_irq(pcie);
356 if (status & INT_ERRORS)
357 plda_pcie_handle_errors_irq(pcie, status);
360 chained_irq_exit(chip, desc);
363 #ifdef CONFIG_PCI_MSI
364 static struct irq_chip plda_msi_irq_chip = {
365 .name = "PLDA PCIe MSI",
366 .irq_mask = pci_msi_mask_irq,
367 .irq_unmask = pci_msi_unmask_irq,
370 static struct msi_domain_info plda_msi_domain_info = {
371 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
373 .chip = &plda_msi_irq_chip,
377 static void plda_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
379 struct plda_pcie *pcie = irq_data_get_irq_chip_data(data);
380 phys_addr_t msi_addr = plda_readl(pcie, IMSI_ADDR);
382 msg->address_lo = lower_32_bits(msi_addr);
383 msg->address_hi = upper_32_bits(msi_addr);
384 msg->data = data->hwirq;
386 dev_info(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n",
387 (int)data->hwirq, msg->address_hi, msg->address_lo);
390 static int plda_msi_set_affinity(struct irq_data *irq_data,
391 const struct cpumask *mask, bool force)
396 static struct irq_chip plda_irq_chip = {
398 .irq_compose_msi_msg = plda_compose_msi_msg,
399 .irq_set_affinity = plda_msi_set_affinity,
402 static int plda_msi_alloc(struct irq_domain *domain, unsigned int virq,
403 unsigned int nr_irqs, void *args)
405 struct plda_pcie *pcie = domain->host_data;
406 struct plda_msi *msi = &pcie->msi;
409 WARN_ON(nr_irqs != 1);
410 mutex_lock(&msi->lock);
412 bit = find_first_zero_bit(msi->used, INT_PCI_MSI_NR);
413 if (bit >= INT_PCI_MSI_NR) {
414 mutex_unlock(&msi->lock);
418 set_bit(bit, msi->used);
420 irq_domain_set_info(domain, virq, bit, &plda_irq_chip,
421 domain->host_data, handle_simple_irq,
423 mutex_unlock(&msi->lock);
428 static void plda_msi_free(struct irq_domain *domain, unsigned int virq,
429 unsigned int nr_irqs)
431 struct irq_data *data = irq_domain_get_irq_data(domain, virq);
432 struct plda_pcie *pcie = irq_data_get_irq_chip_data(data);
433 struct plda_msi *msi = &pcie->msi;
435 mutex_lock(&msi->lock);
437 if (!test_bit(data->hwirq, msi->used))
438 dev_err(&pcie->pdev->dev, "Trying to free unused MSI#%lu\n",
441 __clear_bit(data->hwirq, msi->used);
443 mutex_unlock(&msi->lock);
446 static const struct irq_domain_ops dev_msi_domain_ops = {
447 .alloc = plda_msi_alloc,
448 .free = plda_msi_free,
451 static void plda_msi_free_irq_domain(struct plda_pcie *pcie)
453 #ifdef CONFIG_PCI_MSI
454 struct plda_msi *msi = &pcie->msi;
458 for (i = 0; i < INT_PCI_MSI_NR; i++) {
459 irq = irq_find_mapping(msi->inner_domain, i);
461 irq_dispose_mapping(irq);
465 irq_domain_remove(msi->msi_domain);
467 if (msi->inner_domain)
468 irq_domain_remove(msi->inner_domain);
472 static void plda_pcie_free_irq_domain(struct plda_pcie *pcie)
477 /* Disable all interrupts */
478 plda_writel(pcie, 0, IMASK_LOCAL);
480 if (pcie->legacy_irq_domain) {
481 for (i = 0; i < PCI_NUM_INTX; i++) {
482 irq = irq_find_mapping(pcie->legacy_irq_domain, i);
484 irq_dispose_mapping(irq);
486 irq_domain_remove(pcie->legacy_irq_domain);
489 if (pci_msi_enabled())
490 plda_msi_free_irq_domain(pcie);
491 irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
494 static int plda_pcie_init_msi_irq_domain(struct plda_pcie *pcie)
496 #ifdef CONFIG_PCI_MSI
497 struct fwnode_handle *fwn = of_node_to_fwnode(pcie->pdev->dev.of_node);
498 struct plda_msi *msi = &pcie->msi;
500 msi->inner_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR,
501 &dev_msi_domain_ops, pcie);
502 if (!msi->inner_domain) {
503 dev_err(&pcie->pdev->dev, "Failed to create dev IRQ domain\n");
506 msi->msi_domain = pci_msi_create_irq_domain(fwn, &plda_msi_domain_info,
508 if (!msi->msi_domain) {
509 dev_err(&pcie->pdev->dev, "Failed to create msi IRQ domain\n");
510 irq_domain_remove(msi->inner_domain);
517 static int plda_pcie_enable_msi(struct plda_pcie *pcie, struct pci_bus *bus)
519 struct plda_msi *msi = &pcie->msi;
522 mutex_init(&msi->lock);
525 reg = plda_readl(pcie, IMASK_LOCAL);
527 plda_writel(pcie, reg, IMASK_LOCAL);
531 static int plda_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
532 irq_hw_number_t hwirq)
534 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
535 irq_set_chip_data(irq, domain->host_data);
540 static const struct irq_domain_ops intx_domain_ops = {
541 .map = plda_pcie_intx_map,
542 .xlate = pci_irqd_intx_xlate,
545 static int plda_pcie_init_irq_domain(struct plda_pcie *pcie)
547 struct device *dev = &pcie->pdev->dev;
548 struct device_node *node = dev->of_node;
551 if (pci_msi_enabled()) {
552 ret = plda_pcie_init_msi_irq_domain(pcie);
558 pcie->legacy_irq_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
559 &intx_domain_ops, pcie);
561 if (!pcie->legacy_irq_domain) {
562 dev_err(dev, "Failed to get a INTx IRQ domain\n");
566 irq_set_chained_handler_and_data(pcie->irq, plda_pcie_isr, pcie);
570 static int plda_pcie_parse_dt(struct plda_pcie *pcie)
572 struct resource *reg_res;
573 struct platform_device *pdev = pcie->pdev;
574 struct of_phandle_args args;
577 reg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
579 dev_err(&pdev->dev, "Missing required reg address range\n");
583 pcie->reg_base = devm_ioremap_resource(&pdev->dev, reg_res);
584 if (IS_ERR(pcie->reg_base)) {
585 dev_err(&pdev->dev, "Failed to map reg memory\n");
586 return PTR_ERR(pcie->reg_base);
589 pcie->cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
590 if (!pcie->cfg_res) {
591 dev_err(&pdev->dev, "Missing required config address range");
595 pcie->config_base = devm_ioremap_resource(&pdev->dev, pcie->cfg_res);
596 if (IS_ERR(pcie->config_base)){
597 dev_err(&pdev->dev, "Failed to map config memory\n");
598 return PTR_ERR(pcie->config_base);
601 pcie->irq = platform_get_irq(pdev, 0);
602 if (pcie->irq <= 0) {
603 dev_err(&pdev->dev, "Failed to get IRQ: %d\n", pcie->irq);
607 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
608 "starfive,stg-syscon", 4, 0, &args);
610 dev_err(&pdev->dev, "Failed to parse starfive,stg-syscon\n");
614 pcie->reg_syscon = syscon_node_to_regmap(args.np);
615 of_node_put(args.np);
616 if (IS_ERR(pcie->reg_syscon))
617 return PTR_ERR(pcie->reg_syscon);
619 pcie->stg_arfun = args.args[0];
620 pcie->stg_awfun = args.args[1];
621 pcie->stg_rp_nep = args.args[2];
622 pcie->stg_lnksta = args.args[3];
624 /* Clear all interrupts */
625 plda_writel(pcie, 0xffffffff, ISTATUS_LOCAL);
626 plda_writel(pcie, INT_INTX_MASK | INT_ERRORS, IMASK_LOCAL);
631 static struct pci_ops plda_pcie_ops = {
632 .read = plda_pcie_config_read,
633 .write = plda_pcie_config_write,
636 void plda_set_atr_entry(struct plda_pcie *pcie, phys_addr_t src_addr,
637 phys_addr_t trsl_addr, size_t window_size,
641 pcie->reg_base + XR3PCI_ATR_AXI4_SLV0;
643 /* Support AXI4 Slave 0 Address Translation Tables 0-7. */
644 if (pcie->atr_table_num >= XR3PCI_ATR_MAX_TABLE_NUM)
645 pcie->atr_table_num = XR3PCI_ATR_MAX_TABLE_NUM - 1;
646 base += XR3PCI_ATR_TABLE_OFFSET * pcie->atr_table_num;
647 pcie->atr_table_num++;
649 /* X3PCI_ATR_SRC_ADDR_LOW:
650 * - bit 0: enable entry,
651 * - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1)
652 * - bits 7-11: reserved
653 * - bits 12-31: start of source address
655 writel((lower_32_bits(src_addr) & XR3PCI_ATR_SRC_ADDR_MASK) |
656 (fls(window_size) - 1) << XR3PCI_ATR_SRC_WIN_SIZE_SHIFT | 1,
657 base + XR3PCI_ATR_SRC_ADDR_LOW);
658 writel(upper_32_bits(src_addr), base + XR3PCI_ATR_SRC_ADDR_HIGH);
659 writel((lower_32_bits(trsl_addr) & XR3PCI_ATR_TRSL_ADDR_MASK),
660 base + XR3PCI_ATR_TRSL_ADDR_LOW);
661 writel(upper_32_bits(trsl_addr), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
662 writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
664 pr_info("ATR entry: 0x%010llx %s 0x%010llx [0x%010llx] (param: 0x%06x)\n",
665 src_addr, (trsl_param & XR3PCI_ATR_TRSL_DIR) ? "<-" : "->",
666 trsl_addr, (u64)window_size, trsl_param);
669 static int plda_pcie_setup_windows(struct plda_pcie *pcie)
671 struct pci_host_bridge *bridge = pcie->bridge;
672 struct resource_entry *entry;
675 resource_list_for_each_entry(entry, &bridge->windows) {
676 if (resource_type(entry->res) == IORESOURCE_MEM) {
677 pci_addr = entry->res->start - entry->offset;
678 plda_set_atr_entry(pcie,
679 entry->res->start, pci_addr,
680 resource_size(entry->res),
681 XR3PCI_ATR_TRSLID_PCIE_MEMORY);
688 static int plda_clk_rst_init(struct plda_pcie *pcie)
691 struct device *dev = &pcie->pdev->dev;
693 pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks);
694 if (pcie->num_clks < 0) {
695 dev_err(dev, "Failed to get pcie clocks\n");
699 ret = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks);
701 dev_err(&pcie->pdev->dev, "Failed to enable clocks\n");
705 pcie->resets = devm_reset_control_array_get_exclusive(dev);
706 if (IS_ERR(pcie->resets)) {
707 ret = PTR_ERR(pcie->resets);
708 dev_err(dev, "Failed to get pcie resets");
711 ret = reset_control_deassert(pcie->resets);
715 clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks);
720 static void plda_clk_rst_deinit(struct plda_pcie *pcie)
722 reset_control_assert(pcie->resets);
723 clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks);
726 int plda_pinctrl_init(struct plda_pcie *pcie)
728 struct device *dev = &pcie->pdev->dev;
730 pcie->pinctrl = devm_pinctrl_get(dev);
731 if (IS_ERR_OR_NULL(pcie->pinctrl)) {
732 dev_err(dev, "Getting pinctrl handle failed\n");
736 pcie->perst_state_def
737 = pinctrl_lookup_state(pcie->pinctrl, "perst-default");
738 if (IS_ERR_OR_NULL(pcie->perst_state_def)) {
739 dev_err(dev, "Failed to get the perst-default pinctrl handle\n");
743 pcie->perst_state_active
744 = pinctrl_lookup_state(pcie->pinctrl, "perst-active");
745 if (IS_ERR_OR_NULL(pcie->perst_state_active)) {
746 dev_err(dev, "Failed to get the perst-active pinctrl handle\n");
750 pcie->power_state_def
751 = pinctrl_lookup_state(pcie->pinctrl, "power-default");
752 if (IS_ERR_OR_NULL(pcie->power_state_def)) {
753 dev_err(dev, "Failed to get the power-default pinctrl handle\n");
757 pcie->power_state_active
758 = pinctrl_lookup_state(pcie->pinctrl, "power-active");
759 if (IS_ERR_OR_NULL(pcie->power_state_active)) {
760 dev_err(dev, "Failed to get the power-active pinctrl handle\n");
767 static void plda_pcie_hw_init(struct plda_pcie *pcie)
771 struct device *dev = &pcie->pdev->dev;
773 if (pcie->power_state_active) {
774 ret = pinctrl_select_state(pcie->pinctrl, pcie->power_state_active);
776 dev_err(dev, "Cannot set power pin to high\n");
779 if (pcie->perst_state_active) {
780 ret = pinctrl_select_state(pcie->pinctrl, pcie->perst_state_active);
782 dev_err(dev, "Cannot set reset pin to low\n");
785 /* Disable physical functions except #0 */
786 for (i = 1; i < PLDA_FUNC_NUM; i++) {
787 regmap_update_bits(pcie->reg_syscon,
789 STG_SYSCON_AXI4_SLVL_ARFUNC_MASK,
790 (i << PLDA_PHY_FUNC_SHIFT) <<
791 STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT);
792 regmap_update_bits(pcie->reg_syscon,
794 STG_SYSCON_AXI4_SLVL_AWFUNC_MASK,
795 (i << PLDA_PHY_FUNC_SHIFT) <<
796 STG_SYSCON_AXI4_SLVL_AWFUNC_SHIFT);
798 value = readl(pcie->reg_base + PCI_MISC);
799 value |= PLDA_FUNCTION_DIS;
800 writel(value, pcie->reg_base + PCI_MISC);
802 regmap_update_bits(pcie->reg_syscon,
804 STG_SYSCON_AXI4_SLVL_ARFUNC_MASK,
805 0 << STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT);
806 regmap_update_bits(pcie->reg_syscon,
808 STG_SYSCON_AXI4_SLVL_AWFUNC_MASK,
809 0 << STG_SYSCON_AXI4_SLVL_AWFUNC_SHIFT);
811 /* Enable root port*/
812 value = readl(pcie->reg_base + GEN_SETTINGS);
813 value |= PLDA_RP_ENABLE;
814 writel(value, pcie->reg_base + GEN_SETTINGS);
816 /* PCIe PCI Standard Configuration Identification Settings. */
817 value = (IDS_PCI_TO_PCI_BRIDGE << IDS_CLASS_CODE_SHIFT) | IDS_REVISION_ID;
818 writel(value, pcie->reg_base + PCIE_PCI_IDS);
820 /* The LTR message forwarding of PCIe Message Reception was set by core
821 * as default, but the forward id & addr are also need to be reset.
822 * If we do not disable LTR message forwarding here, or set a legal
823 * forwarding address, the kernel will get stuck after this driver probe.
824 * To workaround, disable the LTR message forwarding support on
825 * PCIe Message Reception.
827 value = readl(pcie->reg_base + PMSG_SUPPORT_RX);
828 value &= ~PMSG_LTR_SUPPORT;
829 writel(value, pcie->reg_base + PMSG_SUPPORT_RX);
831 /* Prefetchable memory window 64-bit addressing support */
832 value = readl(pcie->reg_base + PCIE_WINROM);
833 value |= PREF_MEM_WIN_64_SUPPORT;
834 writel(value, pcie->reg_base + PCIE_WINROM);
836 /* As the two host bridges in JH7110 soc have the same default
837 * address translation table, this cause the second root port can't
838 * access it's host bridge config space correctly.
839 * To workaround, config the ATR of host bridge config space by SW.
841 plda_set_atr_entry(pcie,
842 pcie->cfg_res->start, 0,
843 1 << XR3_PCI_ECAM_SIZE,
844 XR3PCI_ATR_TRSLID_PCIE_CONFIG);
846 plda_pcie_setup_windows(pcie);
848 /* Ensure that PERST has been asserted for at least 100 ms */
850 if (pcie->perst_state_def) {
851 ret = pinctrl_select_state(pcie->pinctrl, pcie->perst_state_def);
853 dev_err(dev, "Cannot set reset pin to high\n");
857 static int plda_pcie_is_link_up(struct plda_pcie *pcie)
859 struct device *dev = &pcie->pdev->dev;
863 /* 100ms timeout value should be enough for Gen1/2 training */
864 ret = regmap_read_poll_timeout(pcie->reg_syscon,
867 stg_reg_val & PLDA_DATA_LINK_ACTIVE,
868 10 * 1000, 100 * 1000);
870 /* If the link is down (no device in slot), then exit. */
871 if (ret == -ETIMEDOUT) {
872 dev_info(dev, "Port link down, exit.\n");
873 return PLDA_LINK_DOWN;
874 } else if (ret == 0) {
875 dev_info(dev, "Port link up.\n");
879 dev_warn(dev, "Read stg_linksta failed.\n");
883 static int plda_pcie_probe(struct platform_device *pdev)
885 struct device *dev = &pdev->dev;
886 struct plda_pcie *pcie;
888 struct pci_host_bridge *bridge;
891 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
896 pcie->atr_table_num = 0;
898 ret = plda_pcie_parse_dt(pcie);
900 dev_err(&pdev->dev, "Parsing DT failed\n");
904 platform_set_drvdata(pdev, pcie);
906 plda_pinctrl_init(pcie);
908 dev_err(&pdev->dev, "Init pinctrl failed\n");
912 regmap_update_bits(pcie->reg_syscon,
914 STG_SYSCON_K_RP_NEP_MASK,
915 1 << STG_SYSCON_K_RP_NEP_SHIFT);
917 regmap_update_bits(pcie->reg_syscon,
919 STG_SYSCON_CKREF_SRC_MASK,
920 2 << STG_SYSCON_CKREF_SRC_SHIFT);
922 regmap_update_bits(pcie->reg_syscon,
924 STG_SYSCON_CLKREQ_MASK,
925 1 << STG_SYSCON_CLKREQ_SHIFT);
927 ret = plda_clk_rst_init(pcie);
929 dev_err(&pdev->dev, "Failed to init pcie clk reset: %d\n", ret);
933 ret = plda_pcie_init_irq_domain(pcie);
935 dev_err(&pdev->dev, "Failed creating IRQ Domain\n");
939 bridge = devm_pci_alloc_host_bridge(dev, 0);
945 pm_runtime_enable(&pdev->dev);
946 pm_runtime_get_sync(&pdev->dev);
948 /* Set default bus ops */
949 bridge->ops = &plda_pcie_ops;
950 bridge->sysdata = pcie;
951 pcie->bridge = bridge;
953 plda_pcie_hw_init(pcie);
955 if (plda_pcie_is_link_up(pcie) == PLDA_LINK_DOWN)
958 ret = pci_host_probe(bridge);
960 dev_err(&pdev->dev, "Failed to pci host probe: %d\n", ret);
964 if (IS_ENABLED(CONFIG_PCI_MSI)) {
965 ret = plda_pcie_enable_msi(pcie, bus);
967 dev_err(&pdev->dev, "Failed to enable MSI support: %d\n", ret);
976 if (pcie->power_state_def &&
977 pinctrl_select_state(pcie->pinctrl, pcie->power_state_def))
978 dev_err(dev, "Cannot set power pin to low\n");
979 plda_clk_rst_deinit(pcie);
981 pm_runtime_put_sync(&pdev->dev);
982 pm_runtime_disable(&pdev->dev);
984 pci_free_host_bridge(pcie->bridge);
985 devm_kfree(&pdev->dev, pcie);
986 platform_set_drvdata(pdev, NULL);
991 static int plda_pcie_remove(struct platform_device *pdev)
993 struct plda_pcie *pcie = platform_get_drvdata(pdev);
995 plda_pcie_free_irq_domain(pcie);
996 plda_clk_rst_deinit(pcie);
997 platform_set_drvdata(pdev, NULL);
1002 #ifdef CONFIG_PM_SLEEP
1003 static int __maybe_unused plda_pcie_suspend_noirq(struct device *dev)
1005 struct plda_pcie *pcie = dev_get_drvdata(dev);
1010 clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks);
1015 static int __maybe_unused plda_pcie_resume_noirq(struct device *dev)
1017 struct plda_pcie *pcie = dev_get_drvdata(dev);
1023 ret = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks);
1025 dev_err(dev, "Failed to enable clocks\n");
1030 static const struct dev_pm_ops plda_pcie_pm_ops = {
1031 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(plda_pcie_suspend_noirq,
1032 plda_pcie_resume_noirq)
1036 static const struct of_device_id plda_pcie_of_match[] = {
1037 { .compatible = "plda,pci-xpressrich3-axi"},
1038 { .compatible = "starfive,jh7110-pcie"},
1041 MODULE_DEVICE_TABLE(of, plda_pcie_of_match);
1043 static struct platform_driver plda_pcie_driver = {
1045 .name = KBUILD_MODNAME,
1046 .of_match_table = of_match_ptr(plda_pcie_of_match),
1047 #ifdef CONFIG_PM_SLEEP
1048 .pm = &plda_pcie_pm_ops,
1051 .probe = plda_pcie_probe,
1052 .remove = plda_pcie_remove,
1054 module_platform_driver(plda_pcie_driver);
1056 MODULE_DESCRIPTION("StarFive JH7110 PCIe host driver");
1057 MODULE_AUTHOR("ke.zhu <ke.zhu@starfivetech.com>");
1058 MODULE_AUTHOR("Mason Huo <mason.huo@starfivetech.com>");
1059 MODULE_LICENSE("GPL v2");