2 * PCIe host controller driver for Starfive JH7110 Soc.
4 * Based on pcie-altera.c, pcie-altera-msi.c.
6 * Copyright (C) Shanghai StarFive Technology Co., Ltd.
8 * Author: ke.zhu@starfivetech.com
10 * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
11 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
12 * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
13 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
14 * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
15 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/interrupt.h>
21 #include <linux/irqchip/chained_irq.h>
22 #include <linux/mfd/syscon.h>
23 #include <linux/module.h>
24 #include <linux/msi.h>
25 #include <linux/of_address.h>
26 #include <linux/of_irq.h>
27 #include <linux/of_pci.h>
28 #include <linux/pci.h>
29 #include <linux/pinctrl/pinctrl.h>
30 #include <linux/platform_device.h>
31 #include <linux/regmap.h>
32 #include <linux/reset.h>
33 #include <linux/slab.h>
36 #define PCIE_BASIC_STATUS 0x018
37 #define PCIE_CFGNUM 0x140
38 #define IMASK_LOCAL 0x180
39 #define ISTATUS_LOCAL 0x184
40 #define IMSI_ADDR 0x190
41 #define ISTATUS_MSI 0x194
42 #define CFG_SPACE 0x1000
43 #define GEN_SETTINGS 0x80
44 #define PMSG_SUPPORT_RX 0x3F0
48 #define PLDA_EP_ENABLE 0
49 #define PLDA_RP_ENABLE 1
51 #define PMSG_LTR_SUPPORT BIT(2)
52 #define PDLA_LINK_SPEED_GEN2 BIT(12)
53 #define PLDA_FUNCTION_DIS BIT(15)
54 #define PLDA_FUNC_NUM 4
55 #define PLDA_PHY_FUNC_SHIFT 9
57 #define XR3PCI_ATR_AXI4_SLV0 0x800
58 #define XR3PCI_ATR_SRC_ADDR_LOW 0x0
59 #define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
60 #define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
61 #define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
62 #define XR3PCI_ATR_TRSL_PARAM 0x10
63 #define XR3PCI_ATR_TABLE_OFFSET 0x20
64 #define XR3PCI_ATR_MAX_TABLE_NUM 8
66 #define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1
67 #define XR3PCI_ATR_SRC_ADDR_MASK 0xfffff000
68 #define XR3PCI_ATR_TRSL_ADDR_MASK 0xfffff000
69 #define XR3_PCI_ECAM_SIZE 28
70 #define XR3PCI_ATR_TRSL_DIR BIT(22)
71 /* IDs used in the XR3PCI_ATR_TRSL_PARAM */
72 #define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0
73 #define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1
75 #define CFGNUM_DEVFN_SHIFT 0
76 #define CFGNUM_BUS_SHIFT 8
77 #define CFGNUM_BE_SHIFT 16
78 #define CFGNUM_FBE_SHIFT 20
80 #define ECAM_BUS_SHIFT 20
81 #define ECAM_DEV_SHIFT 15
82 #define ECAM_FUNC_SHIFT 12
84 #define INT_AXI_POST_ERROR BIT(16)
85 #define INT_AXI_FETCH_ERROR BIT(17)
86 #define INT_AXI_DISCARD_ERROR BIT(18)
87 #define INT_PCIE_POST_ERROR BIT(20)
88 #define INT_PCIE_FETCH_ERROR BIT(21)
89 #define INT_PCIE_DISCARD_ERROR BIT(22)
90 #define INT_ERRORS (INT_AXI_POST_ERROR | INT_AXI_FETCH_ERROR | \
91 INT_AXI_DISCARD_ERROR | INT_PCIE_POST_ERROR | \
92 INT_PCIE_FETCH_ERROR | INT_PCIE_DISCARD_ERROR)
94 #define INTA_OFFSET 24
99 #define INT_MSI BIT(28)
100 #define INT_INTX_MASK (INTA | INTB | INTC | INTD)
101 #define INT_MASK (INT_INTX_MASK | INT_MSI | INT_ERRORS)
103 #define INT_PCI_MSI_NR 32
104 #define LINK_UP_MASK 0xff
106 #define PERST_DELAY_US 1000
109 #define STG_SYSCON_K_RP_NEP_SHIFT 0x8
110 #define STG_SYSCON_K_RP_NEP_MASK 0x100
111 #define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK 0x7FFF00
112 #define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 0x8
113 #define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK 0x7FFF
114 #define STG_SYSCON_AXI4_SLVL_AWFUNC_SHIFT 0x0
115 #define STG_SYSCON_CLKREQ_SHIFT 0x16
116 #define STG_SYSCON_CLKREQ_MASK 0x400000
117 #define STG_SYSCON_CKREF_SRC_SHIFT 0x12
118 #define STG_SYSCON_CKREF_SRC_MASK 0xC0000
120 #define PCI_DEV(d) (((d) >> 3) & 0x1f)
122 /* MSI information */
124 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
125 struct irq_domain *msi_domain;
126 struct irq_domain *inner_domain;
127 /* Protect bitmap variable */
132 struct platform_device *pdev;
133 void __iomem *reg_base;
134 void __iomem *config_base;
135 struct resource *cfg_res;
136 struct regmap *reg_syscon;
141 struct irq_domain *legacy_irq_domain;
142 struct pci_host_bridge *bridge;
144 struct reset_control *resets;
145 struct clk_bulk_data *clks;
148 struct pinctrl *pinctrl;
149 struct pinctrl_state *perst_state_def;
150 struct pinctrl_state *perst_state_active;
151 struct pinctrl_state *power_state_active;
154 static inline void plda_writel(struct plda_pcie *pcie, const u32 value,
157 writel_relaxed(value, pcie->reg_base + reg);
160 static inline u32 plda_readl(struct plda_pcie *pcie, const u32 reg)
162 return readl_relaxed(pcie->reg_base + reg);
165 static bool plda_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn,
168 if (pci_is_root_bus(bus) && (devfn == 0) &&
169 (offset == PCI_BASE_ADDRESS_0))
175 static int _plda_pcie_config_read(struct plda_pcie *pcie, unsigned char busno,
176 unsigned int devfn, int where, int size,
181 addr = pcie->config_base;
182 addr += (busno << ECAM_BUS_SHIFT);
183 addr += (PCI_DEV(devfn) << ECAM_DEV_SHIFT);
184 addr += (PCI_FUNC(devfn) << ECAM_FUNC_SHIFT);
188 return PCIBIOS_DEVICE_NOT_FOUND;
192 *(unsigned char *)value = readb(addr);
195 *(unsigned short *)value = readw(addr);
198 *(unsigned int *)value = readl(addr);
201 return PCIBIOS_SET_FAILED;
204 return PCIBIOS_SUCCESSFUL;
207 int _plda_pcie_config_write(struct plda_pcie *pcie, unsigned char busno,
208 unsigned int devfn, int where, int size, u32 value)
212 addr = pcie->config_base;
213 addr += (busno << ECAM_BUS_SHIFT);
214 addr += (PCI_DEV(devfn) << ECAM_DEV_SHIFT);
215 addr += (PCI_FUNC(devfn) << ECAM_FUNC_SHIFT);
219 return PCIBIOS_DEVICE_NOT_FOUND;
232 return PCIBIOS_SET_FAILED;
235 return PCIBIOS_SUCCESSFUL;
238 static int plda_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
239 int where, int size, u32 *value)
241 struct plda_pcie *pcie = bus->sysdata;
243 return _plda_pcie_config_read(pcie, bus->number, devfn, where, size,
247 int plda_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
248 int where, int size, u32 value)
250 struct plda_pcie *pcie = bus->sysdata;
252 if (plda_pcie_hide_rc_bar(bus, devfn, where))
253 return PCIBIOS_BAD_REGISTER_NUMBER;
255 return _plda_pcie_config_write(pcie, bus->number, devfn, where, size,
259 static void plda_pcie_handle_msi_irq(struct plda_pcie *pcie)
261 struct plda_msi *msi = &pcie->msi;
264 unsigned long status = plda_readl(pcie, ISTATUS_MSI);
266 for_each_set_bit(bit, &status, INT_PCI_MSI_NR) {
267 /* Clear interrupts */
268 plda_writel(pcie, 1 << bit, ISTATUS_MSI);
270 virq = irq_find_mapping(msi->inner_domain, bit);
272 if (test_bit(bit, msi->used))
273 generic_handle_irq(virq);
275 dev_err(&pcie->pdev->dev,
276 "Unhandled MSI, MSI%d virq %d\n", bit,
279 dev_err(&pcie->pdev->dev, "Unexpected MSI, MSI%d\n",
283 plda_writel(pcie, INT_MSI, ISTATUS_LOCAL);
286 static void plda_pcie_handle_intx_irq(struct plda_pcie *pcie,
287 unsigned long status)
292 status >>= INTA_OFFSET;
294 for_each_set_bit(bit, &status, PCI_NUM_INTX) {
295 /* Clear interrupts */
296 plda_writel(pcie, 1 << (bit + INTA_OFFSET), ISTATUS_LOCAL);
298 virq = irq_find_mapping(pcie->legacy_irq_domain, bit);
300 generic_handle_irq(virq);
302 dev_err(&pcie->pdev->dev,
303 "plda_pcie_handle_intx_irq unexpected IRQ, INT%d\n", bit);
307 static void plda_pcie_handle_errors_irq(struct plda_pcie *pcie, u32 status)
309 if (status & INT_AXI_POST_ERROR)
310 dev_err(&pcie->pdev->dev, "AXI post error\n");
311 if (status & INT_AXI_FETCH_ERROR)
312 dev_err(&pcie->pdev->dev, "AXI fetch error\n");
313 if (status & INT_AXI_DISCARD_ERROR)
314 dev_err(&pcie->pdev->dev, "AXI discard error\n");
315 if (status & INT_PCIE_POST_ERROR)
316 dev_err(&pcie->pdev->dev, "PCIe post error\n");
317 if (status & INT_PCIE_FETCH_ERROR)
318 dev_err(&pcie->pdev->dev, "PCIe fetch error\n");
319 if (status & INT_PCIE_DISCARD_ERROR)
320 dev_err(&pcie->pdev->dev, "PCIe discard error\n");
322 plda_writel(pcie, INT_ERRORS, ISTATUS_LOCAL);
325 static void plda_pcie_isr(struct irq_desc *desc)
327 struct irq_chip *chip = irq_desc_get_chip(desc);
328 struct plda_pcie *pcie;
331 chained_irq_enter(chip, desc);
332 pcie = irq_desc_get_handler_data(desc);
334 status = plda_readl(pcie, ISTATUS_LOCAL);
335 while ((status = (plda_readl(pcie, ISTATUS_LOCAL) & INT_MASK))) {
336 if (status & INT_INTX_MASK)
337 plda_pcie_handle_intx_irq(pcie, status);
339 if (status & INT_MSI)
340 plda_pcie_handle_msi_irq(pcie);
342 if (status & INT_ERRORS)
343 plda_pcie_handle_errors_irq(pcie, status);
346 chained_irq_exit(chip, desc);
349 #ifdef CONFIG_PCI_MSI
350 static struct irq_chip plda_msi_irq_chip = {
351 .name = "PLDA PCIe MSI",
352 .irq_mask = pci_msi_mask_irq,
353 .irq_unmask = pci_msi_unmask_irq,
356 static struct msi_domain_info plda_msi_domain_info = {
357 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
359 .chip = &plda_msi_irq_chip,
363 static void plda_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
365 struct plda_pcie *pcie = irq_data_get_irq_chip_data(data);
366 phys_addr_t msi_addr = plda_readl(pcie, IMSI_ADDR);
368 msg->address_lo = lower_32_bits(msi_addr);
369 msg->address_hi = upper_32_bits(msi_addr);
370 msg->data = data->hwirq;
372 dev_info(&pcie->pdev->dev, "msi#%d address_hi %#x address_lo %#x\n",
373 (int)data->hwirq, msg->address_hi, msg->address_lo);
376 static int plda_msi_set_affinity(struct irq_data *irq_data,
377 const struct cpumask *mask, bool force)
382 static struct irq_chip plda_irq_chip = {
384 .irq_compose_msi_msg = plda_compose_msi_msg,
385 .irq_set_affinity = plda_msi_set_affinity,
388 static int plda_msi_alloc(struct irq_domain *domain, unsigned int virq,
389 unsigned int nr_irqs, void *args)
391 struct plda_pcie *pcie = domain->host_data;
392 struct plda_msi *msi = &pcie->msi;
395 WARN_ON(nr_irqs != 1);
396 mutex_lock(&msi->lock);
398 bit = find_first_zero_bit(msi->used, INT_PCI_MSI_NR);
399 if (bit >= INT_PCI_MSI_NR) {
400 mutex_unlock(&msi->lock);
404 set_bit(bit, msi->used);
406 irq_domain_set_info(domain, virq, bit, &plda_irq_chip,
407 domain->host_data, handle_simple_irq,
409 mutex_unlock(&msi->lock);
414 static void plda_msi_free(struct irq_domain *domain, unsigned int virq,
415 unsigned int nr_irqs)
417 struct irq_data *data = irq_domain_get_irq_data(domain, virq);
418 struct plda_pcie *pcie = irq_data_get_irq_chip_data(data);
419 struct plda_msi *msi = &pcie->msi;
421 mutex_lock(&msi->lock);
423 if (!test_bit(data->hwirq, msi->used))
424 dev_err(&pcie->pdev->dev, "Trying to free unused MSI#%lu\n",
427 __clear_bit(data->hwirq, msi->used);
429 mutex_unlock(&msi->lock);
432 static const struct irq_domain_ops dev_msi_domain_ops = {
433 .alloc = plda_msi_alloc,
434 .free = plda_msi_free,
437 static void plda_msi_free_irq_domain(struct plda_pcie *pcie)
439 #ifdef CONFIG_PCI_MSI
440 struct plda_msi *msi = &pcie->msi;
444 for (i = 0; i < INT_PCI_MSI_NR; i++) {
445 irq = irq_find_mapping(msi->inner_domain, i);
447 irq_dispose_mapping(irq);
451 irq_domain_remove(msi->msi_domain);
453 if (msi->inner_domain)
454 irq_domain_remove(msi->inner_domain);
458 static void plda_pcie_free_irq_domain(struct plda_pcie *pcie)
463 /* Disable all interrupts */
464 plda_writel(pcie, 0, IMASK_LOCAL);
466 if (pcie->legacy_irq_domain) {
467 for (i = 0; i < PCI_NUM_INTX; i++) {
468 irq = irq_find_mapping(pcie->legacy_irq_domain, i);
470 irq_dispose_mapping(irq);
472 irq_domain_remove(pcie->legacy_irq_domain);
475 if (pci_msi_enabled())
476 plda_msi_free_irq_domain(pcie);
477 irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);
480 static int plda_pcie_init_msi_irq_domain(struct plda_pcie *pcie)
482 #ifdef CONFIG_PCI_MSI
483 struct fwnode_handle *fwn = of_node_to_fwnode(pcie->pdev->dev.of_node);
484 struct plda_msi *msi = &pcie->msi;
486 msi->inner_domain = irq_domain_add_linear(NULL, INT_PCI_MSI_NR,
487 &dev_msi_domain_ops, pcie);
488 if (!msi->inner_domain) {
489 dev_err(&pcie->pdev->dev, "Failed to create dev IRQ domain\n");
492 msi->msi_domain = pci_msi_create_irq_domain(fwn, &plda_msi_domain_info,
494 if (!msi->msi_domain) {
495 dev_err(&pcie->pdev->dev, "Failed to create msi IRQ domain\n");
496 irq_domain_remove(msi->inner_domain);
503 static int plda_pcie_enable_msi(struct plda_pcie *pcie, struct pci_bus *bus)
505 struct plda_msi *msi = &pcie->msi;
508 mutex_init(&msi->lock);
511 reg = plda_readl(pcie, IMASK_LOCAL);
513 plda_writel(pcie, reg, IMASK_LOCAL);
517 static int plda_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
518 irq_hw_number_t hwirq)
520 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
521 irq_set_chip_data(irq, domain->host_data);
526 static const struct irq_domain_ops intx_domain_ops = {
527 .map = plda_pcie_intx_map,
528 .xlate = pci_irqd_intx_xlate,
531 static int plda_pcie_init_irq_domain(struct plda_pcie *pcie)
533 struct device *dev = &pcie->pdev->dev;
534 struct device_node *node = dev->of_node;
537 if (pci_msi_enabled()) {
538 ret = plda_pcie_init_msi_irq_domain(pcie);
544 pcie->legacy_irq_domain = irq_domain_add_linear(node, PCI_NUM_INTX,
545 &intx_domain_ops, pcie);
547 if (!pcie->legacy_irq_domain) {
548 dev_err(dev, "Failed to get a INTx IRQ domain\n");
552 irq_set_chained_handler_and_data(pcie->irq, plda_pcie_isr, pcie);
556 static int plda_pcie_parse_dt(struct plda_pcie *pcie)
558 struct resource *reg_res;
559 struct platform_device *pdev = pcie->pdev;
560 struct of_phandle_args args;
563 reg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
565 dev_err(&pdev->dev, "Missing required reg address range\n");
569 pcie->reg_base = devm_ioremap_resource(&pdev->dev, reg_res);
570 if (IS_ERR(pcie->reg_base)) {
571 dev_err(&pdev->dev, "Failed to map reg memory\n");
572 return PTR_ERR(pcie->reg_base);
575 pcie->cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
576 if (!pcie->cfg_res) {
577 dev_err(&pdev->dev, "Missing required config address range");
581 pcie->config_base = devm_ioremap_resource(&pdev->dev, pcie->cfg_res);
582 if (IS_ERR(pcie->config_base)){
583 dev_err(&pdev->dev, "Failed to map config memory\n");
584 return PTR_ERR(pcie->config_base);
587 pcie->irq = platform_get_irq(pdev, 0);
588 if (pcie->irq <= 0) {
589 dev_err(&pdev->dev, "Failed to get IRQ: %d\n", pcie->irq);
593 ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
594 "starfive,stg-syscon", 3, 0, &args);
596 dev_err(&pdev->dev, "Failed to parse starfive,stg-syscon\n");
600 pcie->reg_syscon = syscon_node_to_regmap(args.np);
601 of_node_put(args.np);
602 if (IS_ERR(pcie->reg_syscon))
603 return PTR_ERR(pcie->reg_syscon);
605 pcie->stg_arfun = args.args[0];
606 pcie->stg_awfun = args.args[1];
607 pcie->stg_rp_nep = args.args[2];
609 /* Clear all interrupts */
610 plda_writel(pcie, 0xffffffff, ISTATUS_LOCAL);
611 plda_writel(pcie, INT_INTX_MASK | INT_ERRORS, IMASK_LOCAL);
616 static struct pci_ops plda_pcie_ops = {
617 .read = plda_pcie_config_read,
618 .write = plda_pcie_config_write,
621 void plda_set_atr_entry(struct plda_pcie *pcie, phys_addr_t src_addr,
622 phys_addr_t trsl_addr, size_t window_size,
626 pcie->reg_base + XR3PCI_ATR_AXI4_SLV0;
628 /* Support AXI4 Slave 0 Address Translation Tables 0-7. */
629 if (pcie->atr_table_num >= XR3PCI_ATR_MAX_TABLE_NUM)
630 pcie->atr_table_num = XR3PCI_ATR_MAX_TABLE_NUM - 1;
631 base += XR3PCI_ATR_TABLE_OFFSET * pcie->atr_table_num;
632 pcie->atr_table_num++;
634 /* X3PCI_ATR_SRC_ADDR_LOW:
635 * - bit 0: enable entry,
636 * - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1)
637 * - bits 7-11: reserved
638 * - bits 12-31: start of source address
640 writel((lower_32_bits(src_addr) & XR3PCI_ATR_SRC_ADDR_MASK) |
641 (fls(window_size) - 1) << XR3PCI_ATR_SRC_WIN_SIZE_SHIFT | 1,
642 base + XR3PCI_ATR_SRC_ADDR_LOW);
643 writel(upper_32_bits(src_addr), base + XR3PCI_ATR_SRC_ADDR_HIGH);
644 writel((lower_32_bits(trsl_addr) & XR3PCI_ATR_TRSL_ADDR_MASK),
645 base + XR3PCI_ATR_TRSL_ADDR_LOW);
646 writel(upper_32_bits(trsl_addr), base + XR3PCI_ATR_TRSL_ADDR_HIGH);
647 writel(trsl_param, base + XR3PCI_ATR_TRSL_PARAM);
649 pr_info("ATR entry: 0x%010llx %s 0x%010llx [0x%010llx] (param: 0x%06x)\n",
650 src_addr, (trsl_param & XR3PCI_ATR_TRSL_DIR) ? "<-" : "->",
651 trsl_addr, (u64)window_size, trsl_param);
654 static int plda_pcie_setup_windows(struct plda_pcie *pcie)
656 struct pci_host_bridge *bridge = pcie->bridge;
657 struct resource_entry *entry;
660 resource_list_for_each_entry(entry, &bridge->windows) {
661 if (resource_type(entry->res) == IORESOURCE_MEM) {
662 pci_addr = entry->res->start - entry->offset;
663 plda_set_atr_entry(pcie,
664 entry->res->start, pci_addr,
665 resource_size(entry->res),
666 XR3PCI_ATR_TRSLID_PCIE_MEMORY);
673 static int plda_clk_rst_init(struct plda_pcie *pcie)
676 struct device *dev = &pcie->pdev->dev;
678 pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks);
679 if (pcie->num_clks < 0) {
680 dev_err(dev, "Failed to get pcie clocks\n");
684 ret = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks);
686 dev_err(&pcie->pdev->dev, "Failed to enable clocks\n");
690 pcie->resets = devm_reset_control_array_get_exclusive(dev);
691 if (IS_ERR(pcie->resets)) {
692 ret = PTR_ERR(pcie->resets);
693 dev_err(dev, "Failed to get pcie resets");
696 ret = reset_control_deassert(pcie->resets);
700 clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks);
705 static void plda_clk_rst_deinit(struct plda_pcie *pcie)
707 reset_control_assert(pcie->resets);
708 clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks);
711 int plda_pinctrl_init(struct plda_pcie *pcie)
713 struct device *dev = &pcie->pdev->dev;
715 pcie->pinctrl = devm_pinctrl_get(dev);
716 if (IS_ERR_OR_NULL(pcie->pinctrl)) {
717 dev_err(dev, "Getting pinctrl handle failed\n");
721 pcie->perst_state_def
722 = pinctrl_lookup_state(pcie->pinctrl, "perst-default");
723 if (IS_ERR_OR_NULL(pcie->perst_state_def)) {
724 dev_err(dev, "Failed to get the perst-default pinctrl handle\n");
728 pcie->perst_state_active
729 = pinctrl_lookup_state(pcie->pinctrl, "perst-active");
730 if (IS_ERR_OR_NULL(pcie->perst_state_active)) {
731 dev_err(dev, "Failed to get the perst-active pinctrl handle\n");
735 pcie->power_state_active
736 = pinctrl_lookup_state(pcie->pinctrl, "power-active");
737 if (IS_ERR_OR_NULL(pcie->power_state_active)) {
738 dev_err(dev, "Failed to get the power-default pinctrl handle\n");
745 static void plda_pcie_hw_init(struct plda_pcie *pcie)
749 struct device *dev = &pcie->pdev->dev;
751 if (pcie->power_state_active) {
752 ret = pinctrl_select_state(pcie->pinctrl, pcie->power_state_active);
754 dev_err(dev, "Cannot set power pin to high\n");
757 if (pcie->perst_state_active) {
758 ret = pinctrl_select_state(pcie->pinctrl, pcie->perst_state_active);
760 dev_err(dev, "Cannot set reset pin to low\n");
763 /* Disable physical functions except #0 */
764 for (i = 1; i < PLDA_FUNC_NUM; i++) {
765 regmap_update_bits(pcie->reg_syscon,
767 STG_SYSCON_AXI4_SLVL_ARFUNC_MASK,
768 (i << PLDA_PHY_FUNC_SHIFT) <<
769 STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT);
770 regmap_update_bits(pcie->reg_syscon,
772 STG_SYSCON_AXI4_SLVL_AWFUNC_MASK,
773 (i << PLDA_PHY_FUNC_SHIFT) <<
774 STG_SYSCON_AXI4_SLVL_AWFUNC_SHIFT);
776 value = readl(pcie->reg_base + PCI_MISC);
777 value |= PLDA_FUNCTION_DIS;
778 writel(value, pcie->reg_base + PCI_MISC);
780 regmap_update_bits(pcie->reg_syscon,
782 STG_SYSCON_AXI4_SLVL_ARFUNC_MASK,
783 0 << STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT);
784 regmap_update_bits(pcie->reg_syscon,
786 STG_SYSCON_AXI4_SLVL_AWFUNC_MASK,
787 0 << STG_SYSCON_AXI4_SLVL_AWFUNC_SHIFT);
789 /* Enable root port*/
790 value = readl(pcie->reg_base + GEN_SETTINGS);
791 value |= PLDA_RP_ENABLE;
792 writel(value, pcie->reg_base + GEN_SETTINGS);
794 /* The LTR message forwarding of PCIe Message Reception was set by core
795 * as default, but the forward id & addr are also need to be reset.
796 * If we do not disable LTR message forwarding here, or set a legal
797 * forwarding address, the kernel will get stuck after this driver probe.
798 * To workaround, disable the LTR message forwarding support on
799 * PCIe Message Reception.
801 value = readl(pcie->reg_base + PMSG_SUPPORT_RX);
802 value &= ~PMSG_LTR_SUPPORT;
803 writel(value, pcie->reg_base + PMSG_SUPPORT_RX);
805 /* As the two host bridges in JH7110 soc have the same default
806 * address translation table, this cause the second root port can't
807 * access it's host bridge config space correctly.
808 * To workaround, config the ATR of host bridge config space by SW.
810 plda_set_atr_entry(pcie,
811 pcie->cfg_res->start, 0,
812 1 << XR3_PCI_ECAM_SIZE,
813 XR3PCI_ATR_TRSLID_PCIE_CONFIG);
815 plda_pcie_setup_windows(pcie);
817 /* Ensure that PERST has been asserted for at least 100 ms */
819 if (pcie->perst_state_def) {
820 ret = pinctrl_select_state(pcie->pinctrl, pcie->perst_state_def);
822 dev_err(dev, "Cannot set reset pin to high\n");
827 static int plda_pcie_probe(struct platform_device *pdev)
829 struct device *dev = &pdev->dev;
830 struct plda_pcie *pcie;
832 struct pci_host_bridge *bridge;
835 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
840 pcie->atr_table_num = 0;
842 ret = plda_pcie_parse_dt(pcie);
844 dev_err(&pdev->dev, "Parsing DT failed\n");
848 platform_set_drvdata(pdev, pcie);
850 plda_pinctrl_init(pcie);
852 dev_err(&pdev->dev, "Init pinctrl failed\n");
856 regmap_update_bits(pcie->reg_syscon,
858 STG_SYSCON_K_RP_NEP_MASK,
859 1 << STG_SYSCON_K_RP_NEP_SHIFT);
861 regmap_update_bits(pcie->reg_syscon,
863 STG_SYSCON_CKREF_SRC_MASK,
864 2 << STG_SYSCON_CKREF_SRC_SHIFT);
866 regmap_update_bits(pcie->reg_syscon,
868 STG_SYSCON_CLKREQ_MASK,
869 1 << STG_SYSCON_CLKREQ_SHIFT);
871 ret = plda_clk_rst_init(pcie);
873 dev_err(&pdev->dev, "Failed to init pcie clk reset: %d\n", ret);
877 ret = plda_pcie_init_irq_domain(pcie);
879 dev_err(&pdev->dev, "Failed creating IRQ Domain\n");
883 bridge = devm_pci_alloc_host_bridge(dev, 0);
889 /* Set default bus ops */
890 bridge->ops = &plda_pcie_ops;
891 bridge->sysdata = pcie;
892 pcie->bridge = bridge;
894 plda_pcie_hw_init(pcie);
896 ret = pci_host_probe(bridge);
898 dev_err(&pdev->dev, "Failed to pci host probe: %d\n", ret);
902 if (IS_ENABLED(CONFIG_PCI_MSI)) {
903 ret = plda_pcie_enable_msi(pcie, bus);
905 dev_err(&pdev->dev, "Failed to enable MSI support: %d\n", ret);
912 static int plda_pcie_remove(struct platform_device *pdev)
914 struct plda_pcie *pcie = platform_get_drvdata(pdev);
916 plda_pcie_free_irq_domain(pcie);
917 plda_clk_rst_deinit(pcie);
918 platform_set_drvdata(pdev, NULL);
924 static const struct of_device_id plda_pcie_of_match[] = {
925 { .compatible = "plda,pci-xpressrich3-axi"},
928 MODULE_DEVICE_TABLE(of, plda_pcie_of_match);
930 static struct platform_driver plda_pcie_driver = {
932 .name = KBUILD_MODNAME,
933 .of_match_table = of_match_ptr(plda_pcie_of_match),
935 .probe = plda_pcie_probe,
936 .remove = plda_pcie_remove,
938 module_platform_driver(plda_pcie_driver);
940 MODULE_DESCRIPTION("StarFive JH7110 PCIe host driver");
941 MODULE_AUTHOR("ke.zhu <ke.zhu@starfivetech.com>");
942 MODULE_AUTHOR("Mason Huo <mason.huo@starfivetech.com>");
943 MODULE_LICENSE("GPL v2");