1 // SPDX-License-Identifier: GPL-2.0+
3 * BRIEF MODULE DESCRIPTION
4 * PCI init for Ralink RT2880 solution
6 * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
11 * May 2009 Bruce Chang
12 * support RT2880/RT3883 PCIe
14 * May 2011 Bruce Chang
15 * support RT6855/MT7620 PCIe
18 #include <linux/bitops.h>
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/module.h>
24 #include <linux/of_address.h>
25 #include <linux/of_pci.h>
26 #include <linux/of_platform.h>
27 #include <linux/pci.h>
28 #include <linux/phy/phy.h>
29 #include <linux/platform_device.h>
30 #include <linux/reset.h>
31 #include <linux/sys_soc.h>
33 /* MediaTek-specific configuration registers */
34 #define PCIE_FTS_NUM 0x70c
35 #define PCIE_FTS_NUM_MASK GENMASK(15, 8)
36 #define PCIE_FTS_NUM_L0(x) (((x) & 0xff) << 8)
38 /* Host-PCI bridge registers */
39 #define RALINK_PCI_PCICFG_ADDR 0x0000
40 #define RALINK_PCI_PCIMSK_ADDR 0x000c
41 #define RALINK_PCI_CONFIG_ADDR 0x0020
42 #define RALINK_PCI_CONFIG_DATA 0x0024
43 #define RALINK_PCI_MEMBASE 0x0028
44 #define RALINK_PCI_IOBASE 0x002c
46 /* PCIe RC control registers */
47 #define RALINK_PCI_ID 0x0030
48 #define RALINK_PCI_CLASS 0x0034
49 #define RALINK_PCI_SUBID 0x0038
50 #define RALINK_PCI_STATUS 0x0050
52 /* Some definition values */
53 #define PCIE_REVISION_ID BIT(0)
54 #define PCIE_CLASS_CODE (0x60400 << 8)
55 #define PCIE_BAR_MAP_MAX GENMASK(30, 16)
56 #define PCIE_BAR_ENABLE BIT(0)
57 #define PCIE_PORT_INT_EN(x) BIT(20 + (x))
58 #define PCIE_PORT_LINKUP BIT(0)
59 #define PCIE_PORT_CNT 3
61 #define PERST_DELAY_MS 100
64 * struct mt7621_pcie_port - PCIe port information
65 * @base: I/O mapped register base
67 * @pcie: pointer to PCIe host info
68 * @clk: pointer to the port clock gate
69 * @phy: pointer to PHY control block
70 * @pcie_rst: pointer to port reset control
71 * @gpio_rst: gpio reset
73 * @enabled: indicates if port is enabled
75 struct mt7621_pcie_port {
77 struct list_head list;
78 struct mt7621_pcie *pcie;
81 struct reset_control *pcie_rst;
82 struct gpio_desc *gpio_rst;
88 * struct mt7621_pcie - PCIe host information
89 * @base: IO Mapped Register Base
90 * @dev: Pointer to PCIe device
91 * @ports: pointer to PCIe port information
92 * @resets_inverted: depends on chip revision
93 * reset lines are inverted.
98 struct list_head ports;
102 static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
104 return readl_relaxed(pcie->base + reg);
107 static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
109 writel_relaxed(val, pcie->base + reg);
112 static inline void pcie_rmw(struct mt7621_pcie *pcie, u32 reg, u32 clr, u32 set)
114 u32 val = readl_relaxed(pcie->base + reg);
118 writel_relaxed(val, pcie->base + reg);
121 static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)
123 return readl_relaxed(port->base + reg);
126 static inline void pcie_port_write(struct mt7621_pcie_port *port,
129 writel_relaxed(val, port->base + reg);
132 static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
133 unsigned int func, unsigned int where)
135 return (((where & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) |
136 (func << 8) | (where & 0xfc) | 0x80000000;
139 static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
140 unsigned int devfn, int where)
142 struct mt7621_pcie *pcie = bus->sysdata;
143 u32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
144 PCI_FUNC(devfn), where);
146 writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
148 return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
151 struct pci_ops mt7621_pci_ops = {
152 .map_bus = mt7621_pcie_map_bus,
153 .read = pci_generic_config_read,
154 .write = pci_generic_config_write,
157 static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
159 u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
161 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
162 return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
165 static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
168 u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
170 pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
171 pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
174 static inline void mt7621_rst_gpio_pcie_assert(struct mt7621_pcie_port *port)
177 gpiod_set_value(port->gpio_rst, 1);
180 static inline void mt7621_rst_gpio_pcie_deassert(struct mt7621_pcie_port *port)
183 gpiod_set_value(port->gpio_rst, 0);
186 static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port)
188 return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0;
191 static inline void mt7621_control_assert(struct mt7621_pcie_port *port)
193 struct mt7621_pcie *pcie = port->pcie;
195 if (pcie->resets_inverted)
196 reset_control_assert(port->pcie_rst);
198 reset_control_deassert(port->pcie_rst);
201 static inline void mt7621_control_deassert(struct mt7621_pcie_port *port)
203 struct mt7621_pcie *pcie = port->pcie;
205 if (pcie->resets_inverted)
206 reset_control_deassert(port->pcie_rst);
208 reset_control_assert(port->pcie_rst);
211 static int setup_cm_memory_region(struct pci_host_bridge *host)
213 struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
214 struct device *dev = pcie->dev;
215 struct resource_entry *entry;
216 resource_size_t mask;
218 entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
220 dev_err(dev, "cannot get memory resource\n");
224 if (mips_cps_numiocu(0)) {
226 * FIXME: hardware doesn't accept mask values with 1s after
227 * 0s (e.g. 0xffef), so it would be great to warn if that's
230 mask = ~(entry->res->end - entry->res->start);
232 write_gcr_reg1_base(entry->res->start);
233 write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
234 dev_info(dev, "PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
235 (unsigned long long)read_gcr_reg1_base(),
236 (unsigned long long)read_gcr_reg1_mask());
242 static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
243 struct device_node *node,
246 struct mt7621_pcie_port *port;
247 struct device *dev = pcie->dev;
248 struct platform_device *pdev = to_platform_device(dev);
252 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
256 port->base = devm_platform_ioremap_resource(pdev, slot + 1);
257 if (IS_ERR(port->base))
258 return PTR_ERR(port->base);
260 port->clk = devm_get_clk_from_child(dev, node, NULL);
261 if (IS_ERR(port->clk)) {
262 dev_err(dev, "failed to get pcie%d clock\n", slot);
263 return PTR_ERR(port->clk);
266 port->pcie_rst = of_reset_control_get_exclusive(node, NULL);
267 if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) {
268 dev_err(dev, "failed to get pcie%d reset control\n", slot);
269 return PTR_ERR(port->pcie_rst);
272 snprintf(name, sizeof(name), "pcie-phy%d", slot);
273 port->phy = devm_of_phy_get(dev, node, name);
274 if (IS_ERR(port->phy)) {
275 dev_err(dev, "failed to get pcie-phy%d\n", slot);
276 err = PTR_ERR(port->phy);
280 port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot,
282 if (IS_ERR(port->gpio_rst)) {
283 dev_err(dev, "failed to get GPIO for PCIe%d\n", slot);
284 err = PTR_ERR(port->gpio_rst);
291 INIT_LIST_HEAD(&port->list);
292 list_add_tail(&port->list, &pcie->ports);
297 reset_control_put(port->pcie_rst);
301 static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
303 struct device *dev = pcie->dev;
304 struct platform_device *pdev = to_platform_device(dev);
305 struct device_node *node = dev->of_node, *child;
308 pcie->base = devm_platform_ioremap_resource(pdev, 0);
309 if (IS_ERR(pcie->base))
310 return PTR_ERR(pcie->base);
312 for_each_available_child_of_node(node, child) {
315 err = of_pci_get_devfn(child);
318 dev_err(dev, "failed to parse devfn: %d\n", err);
322 slot = PCI_SLOT(err);
324 err = mt7621_pcie_parse_port(pcie, child, slot);
334 static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
336 struct mt7621_pcie *pcie = port->pcie;
337 struct device *dev = pcie->dev;
338 u32 slot = port->slot;
341 err = phy_init(port->phy);
343 dev_err(dev, "failed to initialize port%d phy\n", slot);
347 err = phy_power_on(port->phy);
349 dev_err(dev, "failed to power on port%d phy\n", slot);
354 port->enabled = true;
359 static void mt7621_pcie_reset_assert(struct mt7621_pcie *pcie)
361 struct mt7621_pcie_port *port;
363 list_for_each_entry(port, &pcie->ports, list) {
364 /* PCIe RC reset assert */
365 mt7621_control_assert(port);
367 /* PCIe EP reset assert */
368 mt7621_rst_gpio_pcie_assert(port);
371 msleep(PERST_DELAY_MS);
374 static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie)
376 struct mt7621_pcie_port *port;
378 list_for_each_entry(port, &pcie->ports, list)
379 mt7621_control_deassert(port);
382 static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie)
384 struct mt7621_pcie_port *port;
386 list_for_each_entry(port, &pcie->ports, list)
387 mt7621_rst_gpio_pcie_deassert(port);
389 msleep(PERST_DELAY_MS);
392 static int mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
394 struct device *dev = pcie->dev;
395 struct mt7621_pcie_port *port, *tmp;
399 mt7621_pcie_reset_assert(pcie);
400 mt7621_pcie_reset_rc_deassert(pcie);
402 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
403 u32 slot = port->slot;
406 port->enabled = true;
410 err = mt7621_pcie_init_port(port);
412 dev_err(dev, "initializing port %d failed\n", slot);
413 list_del(&port->list);
417 mt7621_pcie_reset_ep_deassert(pcie);
420 list_for_each_entry(port, &pcie->ports, list) {
421 u32 slot = port->slot;
423 if (!mt7621_pcie_port_is_linkup(port)) {
424 dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n",
426 mt7621_control_assert(port);
427 port->enabled = false;
435 if (slot == 1 && tmp && !tmp->enabled)
436 phy_power_off(tmp->phy);
440 return (num_disabled != PCIE_PORT_CNT) ? 0 : -ENODEV;
443 static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
445 struct mt7621_pcie *pcie = port->pcie;
446 u32 slot = port->slot;
449 /* enable pcie interrupt */
450 val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
451 val |= PCIE_PORT_INT_EN(slot);
452 pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
454 /* map 2G DDR region */
455 pcie_port_write(port, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
458 /* configure class code and revision ID */
459 pcie_port_write(port, PCIE_CLASS_CODE | PCIE_REVISION_ID,
462 /* configure RC FTS number to 250 when it leaves L0s */
463 val = read_config(pcie, slot, PCIE_FTS_NUM);
464 val &= ~PCIE_FTS_NUM_MASK;
465 val |= PCIE_FTS_NUM_L0(0x50);
466 write_config(pcie, slot, PCIE_FTS_NUM, val);
469 static int mt7621_pcie_enable_ports(struct pci_host_bridge *host)
471 struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
472 struct device *dev = pcie->dev;
473 struct mt7621_pcie_port *port;
474 struct resource_entry *entry;
477 entry = resource_list_first_type(&host->windows, IORESOURCE_IO);
479 dev_err(dev, "cannot get io resource\n");
483 /* Setup MEMWIN and IOWIN */
484 pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
485 pcie_write(pcie, entry->res->start - entry->offset, RALINK_PCI_IOBASE);
487 list_for_each_entry(port, &pcie->ports, list) {
489 err = clk_prepare_enable(port->clk);
491 dev_err(dev, "enabling clk pcie%d\n",
496 mt7621_pcie_enable_port(port);
497 dev_info(dev, "PCIE%d enabled\n", port->slot);
504 static int mt7621_pcie_register_host(struct pci_host_bridge *host)
506 struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
508 host->ops = &mt7621_pci_ops;
509 host->sysdata = pcie;
510 return pci_host_probe(host);
513 static const struct soc_device_attribute mt7621_pci_quirks_match[] = {
514 { .soc_id = "mt7621", .revision = "E2" }
517 static int mt7621_pci_probe(struct platform_device *pdev)
519 struct device *dev = &pdev->dev;
520 const struct soc_device_attribute *attr;
521 struct mt7621_pcie_port *port;
522 struct mt7621_pcie *pcie;
523 struct pci_host_bridge *bridge;
529 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
533 pcie = pci_host_bridge_priv(bridge);
535 platform_set_drvdata(pdev, pcie);
536 INIT_LIST_HEAD(&pcie->ports);
538 attr = soc_device_match(mt7621_pci_quirks_match);
540 pcie->resets_inverted = true;
542 err = mt7621_pcie_parse_dt(pcie);
544 dev_err(dev, "parsing DT failed\n");
548 err = mt7621_pcie_init_ports(pcie);
550 dev_err(dev, "nothing connected in virtual bridges\n");
554 err = mt7621_pcie_enable_ports(bridge);
556 dev_err(dev, "error enabling pcie ports\n");
560 err = setup_cm_memory_region(bridge);
562 dev_err(dev, "error setting up iocu mem regions\n");
566 return mt7621_pcie_register_host(bridge);
569 list_for_each_entry(port, &pcie->ports, list)
570 reset_control_put(port->pcie_rst);
575 static int mt7621_pci_remove(struct platform_device *pdev)
577 struct mt7621_pcie *pcie = platform_get_drvdata(pdev);
578 struct mt7621_pcie_port *port;
580 list_for_each_entry(port, &pcie->ports, list)
581 reset_control_put(port->pcie_rst);
586 static const struct of_device_id mt7621_pci_ids[] = {
587 { .compatible = "mediatek,mt7621-pci" },
590 MODULE_DEVICE_TABLE(of, mt7621_pci_ids);
592 static struct platform_driver mt7621_pci_driver = {
593 .probe = mt7621_pci_probe,
594 .remove = mt7621_pci_remove,
596 .name = "mt7621-pci",
597 .of_match_table = of_match_ptr(mt7621_pci_ids),
600 builtin_platform_driver(mt7621_pci_driver);