1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
4 #include <linux/bitfield.h>
5 #include <linux/bitops.h>
7 #include <linux/compiler.h>
8 #include <linux/delay.h>
9 #include <linux/init.h>
10 #include <linux/interrupt.h>
12 #include <linux/ioport.h>
13 #include <linux/irqchip/chained_irq.h>
14 #include <linux/irqdomain.h>
15 #include <linux/kernel.h>
16 #include <linux/list.h>
17 #include <linux/log2.h>
18 #include <linux/module.h>
19 #include <linux/msi.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_pci.h>
23 #include <linux/of_platform.h>
24 #include <linux/pci.h>
25 #include <linux/pci-ecam.h>
26 #include <linux/printk.h>
27 #include <linux/reset.h>
28 #include <linux/sizes.h>
29 #include <linux/slab.h>
30 #include <linux/string.h>
31 #include <linux/types.h>
35 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
36 #define BRCM_PCIE_CAP_REGS 0x00ac
38 /* Broadcom STB PCIe Register Offsets */
39 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
40 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
41 #define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0
43 #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
44 #define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
46 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
47 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
49 #define PCIE_RC_DL_MDIO_ADDR 0x1100
50 #define PCIE_RC_DL_MDIO_WR_DATA 0x1104
51 #define PCIE_RC_DL_MDIO_RD_DATA 0x1108
53 #define PCIE_MISC_MISC_CTRL 0x4008
54 #define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
55 #define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
56 #define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
58 #define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
59 #define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x07c00000
60 #define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x0000001f
61 #define SCB_SIZE_MASK(x) PCIE_MISC_MISC_CTRL_SCB ## x ## _SIZE_MASK
63 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
64 #define PCIE_MEM_WIN0_LO(win) \
65 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 8)
67 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
68 #define PCIE_MEM_WIN0_HI(win) \
69 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8)
71 #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
72 #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
74 #define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
75 #define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
76 #define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
78 #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
79 #define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
81 #define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044
82 #define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048
84 #define PCIE_MISC_MSI_DATA_CONFIG 0x404c
85 #define PCIE_MISC_MSI_DATA_CONFIG_VAL_32 0xffe06540
86 #define PCIE_MISC_MSI_DATA_CONFIG_VAL_8 0xfff86540
88 #define PCIE_MISC_PCIE_CTRL 0x4064
89 #define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
90 #define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
92 #define PCIE_MISC_PCIE_STATUS 0x4068
93 #define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
94 #define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
95 #define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
96 #define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
98 #define PCIE_MISC_REVISION 0x406c
99 #define BRCM_PCIE_HW_REV_33 0x0303
100 #define BRCM_PCIE_HW_REV_3_20 0x0320
102 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
103 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
104 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
105 #define PCIE_MEM_WIN0_BASE_LIMIT(win) \
106 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)
108 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
109 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
110 #define PCIE_MEM_WIN0_BASE_HI(win) \
111 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)
113 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
114 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
115 #define PCIE_MEM_WIN0_LIMIT_HI(win) \
116 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
118 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
119 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK BIT(1)
120 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK BIT(21)
121 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK BIT(27)
124 #define PCIE_INTR2_CPU_BASE 0x4300
125 #define PCIE_MSI_INTR2_BASE 0x4500
126 /* Offsets from PCIE_INTR2_CPU_BASE and PCIE_MSI_INTR2_BASE */
127 #define MSI_INT_STATUS 0x0
128 #define MSI_INT_CLR 0x8
129 #define MSI_INT_MASK_SET 0x10
130 #define MSI_INT_MASK_CLR 0x14
132 #define PCIE_EXT_CFG_DATA 0x8000
133 #define PCIE_EXT_CFG_INDEX 0x9000
135 #define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
136 #define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
138 #define RGR1_SW_INIT_1_INIT_GENERIC_MASK 0x2
139 #define RGR1_SW_INIT_1_INIT_GENERIC_SHIFT 0x1
140 #define RGR1_SW_INIT_1_INIT_7278_MASK 0x1
141 #define RGR1_SW_INIT_1_INIT_7278_SHIFT 0x0
143 /* PCIe parameters */
144 #define BRCM_NUM_PCIE_OUT_WINS 0x4
145 #define BRCM_INT_PCI_MSI_NR 32
146 #define BRCM_INT_PCI_MSI_LEGACY_NR 8
147 #define BRCM_INT_PCI_MSI_SHIFT 0
149 /* MSI target adresses */
150 #define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
151 #define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
154 #define MDIO_PORT0 0x0
155 #define MDIO_DATA_MASK 0x7fffffff
156 #define MDIO_PORT_MASK 0xf0000
157 #define MDIO_REGAD_MASK 0xffff
158 #define MDIO_CMD_MASK 0xfff00000
159 #define MDIO_CMD_READ 0x1
160 #define MDIO_CMD_WRITE 0x0
161 #define MDIO_DATA_DONE_MASK 0x80000000
162 #define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
163 #define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
164 #define SSC_REGS_ADDR 0x1100
165 #define SET_ADDR_OFFSET 0x1f
166 #define SSC_CNTL_OFFSET 0x2
167 #define SSC_CNTL_OVRD_EN_MASK 0x8000
168 #define SSC_CNTL_OVRD_VAL_MASK 0x4000
169 #define SSC_STATUS_OFFSET 0x1
170 #define SSC_STATUS_SSC_MASK 0x400
171 #define SSC_STATUS_PLL_LOCK_MASK 0x800
172 #define PCIE_BRCM_MAX_MEMC 3
174 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
175 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
176 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
178 /* Rescal registers */
179 #define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700
180 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS 0x3
181 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK 0x4
182 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT 0x2
183 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK 0x2
184 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT 0x1
185 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK 0x1
186 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT 0x0
188 /* Forward declarations */
190 static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val);
191 static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val);
192 static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val);
193 static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val);
194 static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val);
203 RGR1_SW_INIT_1_INIT_MASK,
204 RGR1_SW_INIT_1_INIT_SHIFT,
214 struct pcie_cfg_data {
216 const enum pcie_type type;
217 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
218 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
221 static const int pcie_offsets[] = {
222 [RGR1_SW_INIT_1] = 0x9210,
223 [EXT_CFG_INDEX] = 0x9000,
224 [EXT_CFG_DATA] = 0x9004,
227 static const struct pcie_cfg_data generic_cfg = {
228 .offsets = pcie_offsets,
230 .perst_set = brcm_pcie_perst_set_generic,
231 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
234 static const struct pcie_cfg_data bcm4908_cfg = {
235 .offsets = pcie_offsets,
237 .perst_set = brcm_pcie_perst_set_4908,
238 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
241 static const int pcie_offset_bcm7278[] = {
242 [RGR1_SW_INIT_1] = 0xc010,
243 [EXT_CFG_INDEX] = 0x9000,
244 [EXT_CFG_DATA] = 0x9004,
247 static const struct pcie_cfg_data bcm7278_cfg = {
248 .offsets = pcie_offset_bcm7278,
250 .perst_set = brcm_pcie_perst_set_7278,
251 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278,
254 static const struct pcie_cfg_data bcm2711_cfg = {
255 .offsets = pcie_offsets,
257 .perst_set = brcm_pcie_perst_set_generic,
258 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
264 struct device_node *np;
265 struct irq_domain *msi_domain;
266 struct irq_domain *inner_domain;
267 struct mutex lock; /* guards the alloc/free operations */
270 /* used indicates which MSI interrupts have been alloc'd */
273 /* Some chips have MSIs in bits [31..24] of a shared register. */
275 int nr; /* No. of MSI available, depends on chip */
276 /* This is the base pointer for interrupt status/set/clr regs */
277 void __iomem *intr_base;
280 /* Internal PCIe Host Controller Information.*/
285 struct device_node *np;
290 struct brcm_msi *msi;
291 const int *reg_offsets;
293 struct reset_control *rescal;
294 struct reset_control *perst_reset;
296 u64 memc_size[PCIE_BRCM_MAX_MEMC];
298 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
299 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
303 * This is to convert the size of the inbound "BAR" region to the
304 * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
306 static int brcm_pcie_encode_ibar_size(u64 size)
308 int log2_in = ilog2(size);
310 if (log2_in >= 12 && log2_in <= 15)
311 /* Covers 4KB to 32KB (inclusive) */
312 return (log2_in - 12) + 0x1c;
313 else if (log2_in >= 16 && log2_in <= 35)
314 /* Covers 64KB to 32GB, (inclusive) */
316 /* Something is awry so disable */
320 static u32 brcm_pcie_mdio_form_pkt(int port, int regad, int cmd)
324 pkt |= FIELD_PREP(MDIO_PORT_MASK, port);
325 pkt |= FIELD_PREP(MDIO_REGAD_MASK, regad);
326 pkt |= FIELD_PREP(MDIO_CMD_MASK, cmd);
331 /* negative return value indicates error */
332 static int brcm_pcie_mdio_read(void __iomem *base, u8 port, u8 regad, u32 *val)
337 writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ),
338 base + PCIE_RC_DL_MDIO_ADDR);
339 readl(base + PCIE_RC_DL_MDIO_ADDR);
341 data = readl(base + PCIE_RC_DL_MDIO_RD_DATA);
342 for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
344 data = readl(base + PCIE_RC_DL_MDIO_RD_DATA);
347 *val = FIELD_GET(MDIO_DATA_MASK, data);
348 return MDIO_RD_DONE(data) ? 0 : -EIO;
351 /* negative return value indicates error */
352 static int brcm_pcie_mdio_write(void __iomem *base, u8 port,
353 u8 regad, u16 wrdata)
358 writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
359 base + PCIE_RC_DL_MDIO_ADDR);
360 readl(base + PCIE_RC_DL_MDIO_ADDR);
361 writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA);
363 data = readl(base + PCIE_RC_DL_MDIO_WR_DATA);
364 for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
366 data = readl(base + PCIE_RC_DL_MDIO_WR_DATA);
369 return MDIO_WT_DONE(data) ? 0 : -EIO;
373 * Configures device for Spread Spectrum Clocking (SSC) mode; a negative
374 * return value indicates error.
376 static int brcm_pcie_set_ssc(struct brcm_pcie *pcie)
382 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET,
387 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0,
388 SSC_CNTL_OFFSET, &tmp);
392 u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_EN_MASK);
393 u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_VAL_MASK);
394 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0,
395 SSC_CNTL_OFFSET, tmp);
399 usleep_range(1000, 2000);
400 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0,
401 SSC_STATUS_OFFSET, &tmp);
405 ssc = FIELD_GET(SSC_STATUS_SSC_MASK, tmp);
406 pll = FIELD_GET(SSC_STATUS_PLL_LOCK_MASK, tmp);
408 return ssc && pll ? 0 : -EIO;
411 /* Limits operation to a specific generation (1, 2, or 3) */
412 static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen)
414 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
415 u32 lnkcap = readl(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
417 lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
418 writel(lnkcap, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
420 lnkctl2 = (lnkctl2 & ~0xf) | gen;
421 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
424 static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
425 unsigned int win, u64 cpu_addr,
426 u64 pcie_addr, u64 size)
428 u32 cpu_addr_mb_high, limit_addr_mb_high;
429 phys_addr_t cpu_addr_mb, limit_addr_mb;
433 /* Set the base of the pcie_addr window */
434 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win));
435 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win));
437 /* Write the addr base & limit lower bits (in MBs) */
438 cpu_addr_mb = cpu_addr / SZ_1M;
439 limit_addr_mb = (cpu_addr + size - 1) / SZ_1M;
441 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
442 u32p_replace_bits(&tmp, cpu_addr_mb,
443 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK);
444 u32p_replace_bits(&tmp, limit_addr_mb,
445 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK);
446 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
448 /* Write the cpu & limit addr upper bits */
450 HWEIGHT32(PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK);
452 cpu_addr_mb_high = cpu_addr_mb >> high_addr_shift;
453 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win));
454 u32p_replace_bits(&tmp, cpu_addr_mb_high,
455 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK);
456 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win));
458 limit_addr_mb_high = limit_addr_mb >> high_addr_shift;
459 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
460 u32p_replace_bits(&tmp, limit_addr_mb_high,
461 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK);
462 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
465 static struct irq_chip brcm_msi_irq_chip = {
466 .name = "BRCM STB PCIe MSI",
467 .irq_ack = irq_chip_ack_parent,
468 .irq_mask = pci_msi_mask_irq,
469 .irq_unmask = pci_msi_unmask_irq,
472 static struct msi_domain_info brcm_msi_domain_info = {
473 /* Multi MSI is supported by the controller, but not by this driver */
474 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
475 .chip = &brcm_msi_irq_chip,
478 static void brcm_pcie_msi_isr(struct irq_desc *desc)
480 struct irq_chip *chip = irq_desc_get_chip(desc);
481 unsigned long status;
482 struct brcm_msi *msi;
486 chained_irq_enter(chip, desc);
487 msi = irq_desc_get_handler_data(desc);
490 status = readl(msi->intr_base + MSI_INT_STATUS);
491 status >>= msi->legacy_shift;
493 for_each_set_bit(bit, &status, msi->nr) {
495 ret = generic_handle_domain_irq(msi->inner_domain, bit);
497 dev_dbg(dev, "unexpected MSI\n");
500 chained_irq_exit(chip, desc);
503 static void brcm_msi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
505 struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
507 msg->address_lo = lower_32_bits(msi->target_addr);
508 msg->address_hi = upper_32_bits(msi->target_addr);
509 msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL_32) | data->hwirq;
512 static int brcm_msi_set_affinity(struct irq_data *irq_data,
513 const struct cpumask *mask, bool force)
518 static void brcm_msi_ack_irq(struct irq_data *data)
520 struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
521 const int shift_amt = data->hwirq + msi->legacy_shift;
523 writel(1 << shift_amt, msi->intr_base + MSI_INT_CLR);
527 static struct irq_chip brcm_msi_bottom_irq_chip = {
528 .name = "BRCM STB MSI",
529 .irq_compose_msi_msg = brcm_msi_compose_msi_msg,
530 .irq_set_affinity = brcm_msi_set_affinity,
531 .irq_ack = brcm_msi_ack_irq,
534 static int brcm_msi_alloc(struct brcm_msi *msi)
538 mutex_lock(&msi->lock);
539 hwirq = bitmap_find_free_region(&msi->used, msi->nr, 0);
540 mutex_unlock(&msi->lock);
545 static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq)
547 mutex_lock(&msi->lock);
548 bitmap_release_region(&msi->used, hwirq, 0);
549 mutex_unlock(&msi->lock);
552 static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
553 unsigned int nr_irqs, void *args)
555 struct brcm_msi *msi = domain->host_data;
558 hwirq = brcm_msi_alloc(msi);
563 irq_domain_set_info(domain, virq, (irq_hw_number_t)hwirq,
564 &brcm_msi_bottom_irq_chip, domain->host_data,
565 handle_edge_irq, NULL, NULL);
569 static void brcm_irq_domain_free(struct irq_domain *domain,
570 unsigned int virq, unsigned int nr_irqs)
572 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
573 struct brcm_msi *msi = irq_data_get_irq_chip_data(d);
575 brcm_msi_free(msi, d->hwirq);
578 static const struct irq_domain_ops msi_domain_ops = {
579 .alloc = brcm_irq_domain_alloc,
580 .free = brcm_irq_domain_free,
583 static int brcm_allocate_domains(struct brcm_msi *msi)
585 struct fwnode_handle *fwnode = of_node_to_fwnode(msi->np);
586 struct device *dev = msi->dev;
588 msi->inner_domain = irq_domain_add_linear(NULL, msi->nr, &msi_domain_ops, msi);
589 if (!msi->inner_domain) {
590 dev_err(dev, "failed to create IRQ domain\n");
594 msi->msi_domain = pci_msi_create_irq_domain(fwnode,
595 &brcm_msi_domain_info,
597 if (!msi->msi_domain) {
598 dev_err(dev, "failed to create MSI domain\n");
599 irq_domain_remove(msi->inner_domain);
606 static void brcm_free_domains(struct brcm_msi *msi)
608 irq_domain_remove(msi->msi_domain);
609 irq_domain_remove(msi->inner_domain);
612 static void brcm_msi_remove(struct brcm_pcie *pcie)
614 struct brcm_msi *msi = pcie->msi;
618 irq_set_chained_handler_and_data(msi->irq, NULL, NULL);
619 brcm_free_domains(msi);
622 static void brcm_msi_set_regs(struct brcm_msi *msi)
624 u32 val = __GENMASK(31, msi->legacy_shift);
626 writel(val, msi->intr_base + MSI_INT_MASK_CLR);
627 writel(val, msi->intr_base + MSI_INT_CLR);
630 * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI
631 * enable, which we set to 1.
633 writel(lower_32_bits(msi->target_addr) | 0x1,
634 msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO);
635 writel(upper_32_bits(msi->target_addr),
636 msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI);
638 val = msi->legacy ? PCIE_MISC_MSI_DATA_CONFIG_VAL_8 : PCIE_MISC_MSI_DATA_CONFIG_VAL_32;
639 writel(val, msi->base + PCIE_MISC_MSI_DATA_CONFIG);
642 static int brcm_pcie_enable_msi(struct brcm_pcie *pcie)
644 struct brcm_msi *msi;
646 struct device *dev = pcie->dev;
648 irq = irq_of_parse_and_map(dev->of_node, 1);
650 dev_err(dev, "cannot map MSI interrupt\n");
654 msi = devm_kzalloc(dev, sizeof(struct brcm_msi), GFP_KERNEL);
658 mutex_init(&msi->lock);
660 msi->base = pcie->base;
662 msi->target_addr = pcie->msi_target_addr;
664 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33;
667 msi->intr_base = msi->base + PCIE_INTR2_CPU_BASE;
668 msi->nr = BRCM_INT_PCI_MSI_LEGACY_NR;
669 msi->legacy_shift = 24;
671 msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE;
672 msi->nr = BRCM_INT_PCI_MSI_NR;
673 msi->legacy_shift = 0;
676 ret = brcm_allocate_domains(msi);
680 irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi);
682 brcm_msi_set_regs(msi);
688 /* The controller is capable of serving in both RC and EP roles */
689 static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
691 void __iomem *base = pcie->base;
692 u32 val = readl(base + PCIE_MISC_PCIE_STATUS);
694 return !!FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK, val);
697 static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
699 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
700 u32 dla = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK, val);
701 u32 plu = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK, val);
706 static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
709 struct brcm_pcie *pcie = bus->sysdata;
710 void __iomem *base = pcie->base;
713 /* Accesses to the RC go right to the RC registers if slot==0 */
714 if (pci_is_root_bus(bus))
715 return PCI_SLOT(devfn) ? NULL : base + where;
717 /* For devices, write to the config space index register */
718 idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0);
719 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
720 return base + PCIE_EXT_CFG_DATA + where;
723 static struct pci_ops brcm_pcie_ops = {
724 .map_bus = brcm_pcie_map_conf,
725 .read = pci_generic_config_read,
726 .write = pci_generic_config_write,
729 static inline void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val)
731 u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK;
732 u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT;
734 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
735 tmp = (tmp & ~mask) | ((val << shift) & mask);
736 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
739 static inline void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val)
741 u32 tmp, mask = RGR1_SW_INIT_1_INIT_7278_MASK;
742 u32 shift = RGR1_SW_INIT_1_INIT_7278_SHIFT;
744 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
745 tmp = (tmp & ~mask) | ((val << shift) & mask);
746 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
749 static inline void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val)
751 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n"))
755 reset_control_assert(pcie->perst_reset);
757 reset_control_deassert(pcie->perst_reset);
760 static inline void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val)
764 /* Perst bit has moved and assert value is 0 */
765 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL);
766 u32p_replace_bits(&tmp, !val, PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK);
767 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL);
770 static inline void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val)
774 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
775 u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK);
776 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
779 static inline int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
783 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
784 struct resource_entry *entry;
785 struct device *dev = pcie->dev;
786 u64 lowest_pcie_addr = ~(u64)0;
790 resource_list_for_each_entry(entry, &bridge->dma_ranges) {
791 u64 pcie_beg = entry->res->start - entry->offset;
793 size += entry->res->end - entry->res->start + 1;
794 if (pcie_beg < lowest_pcie_addr)
795 lowest_pcie_addr = pcie_beg;
798 if (lowest_pcie_addr == ~(u64)0) {
799 dev_err(dev, "DT node has no dma-ranges\n");
803 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1,
807 /* Make an educated guess */
809 pcie->memc_size[0] = 1ULL << fls64(size - 1);
811 pcie->num_memc = ret;
814 /* Each memc is viewed through a "port" that is a power of 2 */
815 for (i = 0, size = 0; i < pcie->num_memc; i++)
816 size += pcie->memc_size[i];
818 /* System memory starts at this address in PCIe-space */
819 *rc_bar2_offset = lowest_pcie_addr;
820 /* The sum of all memc views must also be a power of 2 */
821 *rc_bar2_size = 1ULL << fls64(size - 1);
824 * We validate the inbound memory view even though we should trust
825 * whatever the device-tree provides. This is because of an HW issue on
826 * early Raspberry Pi 4's revisions (bcm2711). It turns out its
827 * firmware has to dynamically edit dma-ranges due to a bug on the
828 * PCIe controller integration, which prohibits any access above the
829 * lower 3GB of memory. Given this, we decided to keep the dma-ranges
830 * in check, avoiding hard to debug device-tree related issues in the
833 * The PCIe host controller by design must set the inbound viewport to
834 * be a contiguous arrangement of all of the system's memory. In
835 * addition, its size mut be a power of two. To further complicate
836 * matters, the viewport must start on a pcie-address that is aligned
837 * on a multiple of its size. If a portion of the viewport does not
838 * represent system memory -- e.g. 3GB of memory requires a 4GB
839 * viewport -- we can map the outbound memory in or after 3GB and even
840 * though the viewport will overlap the outbound memory the controller
841 * will know to send outbound memory downstream and everything else
846 * - The best-case scenario, memory up to 3GB, is to place the inbound
847 * region in the first 4GB of pcie-space, as some legacy devices can
848 * only address 32bits. We would also like to put the MSI under 4GB
849 * as well, since some devices require a 32bit MSI target address.
851 * - If the system memory is 4GB or larger we cannot start the inbound
852 * region at location 0 (since we have to allow some space for
853 * outbound memory @ 3GB). So instead it will start at the 1x
854 * multiple of its size
856 if (!*rc_bar2_size || (*rc_bar2_offset & (*rc_bar2_size - 1)) ||
857 (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) {
858 dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n",
859 *rc_bar2_size, *rc_bar2_offset);
866 static int brcm_pcie_setup(struct brcm_pcie *pcie)
868 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
869 u64 rc_bar2_offset, rc_bar2_size;
870 void __iomem *base = pcie->base;
871 struct device *dev = pcie->dev;
872 struct resource_entry *entry;
873 bool ssc_good = false;
874 struct resource *res;
875 int num_out_wins = 0;
876 u16 nlw, cls, lnksta;
878 u32 tmp, burst, aspm_support;
880 /* Reset the bridge */
881 pcie->bridge_sw_init_set(pcie, 1);
882 usleep_range(100, 200);
884 /* Take the bridge out of reset */
885 pcie->bridge_sw_init_set(pcie, 0);
887 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
888 tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
889 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
890 /* Wait for SerDes to be stable */
891 usleep_range(100, 200);
894 * SCB_MAX_BURST_SIZE is a two bit field. For GENERIC chips it
895 * is encoded as 0=128, 1=256, 2=512, 3=Rsvd, for BCM7278 it
896 * is encoded as 0=Rsvd, 1=128, 2=256, 3=512.
898 if (pcie->type == BCM2711)
899 burst = 0x0; /* 128B */
900 else if (pcie->type == BCM7278)
901 burst = 0x3; /* 512 bytes */
903 burst = 0x2; /* 512 bytes */
905 /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
906 tmp = readl(base + PCIE_MISC_MISC_CTRL);
907 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK);
908 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK);
909 u32p_replace_bits(&tmp, burst, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK);
910 writel(tmp, base + PCIE_MISC_MISC_CTRL);
912 ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,
917 tmp = lower_32_bits(rc_bar2_offset);
918 u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size),
919 PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK);
920 writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
921 writel(upper_32_bits(rc_bar2_offset),
922 base + PCIE_MISC_RC_BAR2_CONFIG_HI);
924 tmp = readl(base + PCIE_MISC_MISC_CTRL);
925 for (memc = 0; memc < pcie->num_memc; memc++) {
926 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15;
929 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(0));
931 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(1));
933 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(2));
935 writel(tmp, base + PCIE_MISC_MISC_CTRL);
938 * We ideally want the MSI target address to be located in the 32bit
939 * addressable memory area. Some devices might depend on it. This is
940 * possible either when the inbound window is located above the lower
941 * 4GB or when the inbound area is smaller than 4GB (taking into
942 * account the rounding-up we're forced to perform).
944 if (rc_bar2_offset >= SZ_4G || (rc_bar2_size + rc_bar2_offset) < SZ_4G)
945 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB;
947 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB;
949 /* disable the PCIe->GISB memory window (RC_BAR1) */
950 tmp = readl(base + PCIE_MISC_RC_BAR1_CONFIG_LO);
951 tmp &= ~PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK;
952 writel(tmp, base + PCIE_MISC_RC_BAR1_CONFIG_LO);
954 /* disable the PCIe->SCB memory window (RC_BAR3) */
955 tmp = readl(base + PCIE_MISC_RC_BAR3_CONFIG_LO);
956 tmp &= ~PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK;
957 writel(tmp, base + PCIE_MISC_RC_BAR3_CONFIG_LO);
960 brcm_pcie_set_gen(pcie, pcie->gen);
962 /* Unassert the fundamental reset */
963 pcie->perst_set(pcie, 0);
966 * Give the RC/EP time to wake up, before trying to configure RC.
967 * Intermittently check status for link-up, up to a total of 100ms.
969 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
972 if (!brcm_pcie_link_up(pcie)) {
973 dev_err(dev, "link down\n");
977 if (!brcm_pcie_rc_mode(pcie)) {
978 dev_err(dev, "PCIe misconfigured; is in EP mode\n");
982 resource_list_for_each_entry(entry, &bridge->windows) {
985 if (resource_type(res) != IORESOURCE_MEM)
988 if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) {
989 dev_err(pcie->dev, "too many outbound wins\n");
993 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start,
994 res->start - entry->offset,
999 /* Don't advertise L0s capability if 'aspm-no-l0s' */
1000 aspm_support = PCIE_LINK_STATE_L1;
1001 if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
1002 aspm_support |= PCIE_LINK_STATE_L0S;
1003 tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
1004 u32p_replace_bits(&tmp, aspm_support,
1005 PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
1006 writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
1009 * For config space accesses on the RC, show the right class for
1010 * a PCIe-PCIe bridge (the default setting is to be EP mode).
1012 tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3);
1013 u32p_replace_bits(&tmp, 0x060400,
1014 PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK);
1015 writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3);
1018 ret = brcm_pcie_set_ssc(pcie);
1022 dev_err(dev, "failed attempt to enter ssc mode\n");
1025 lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
1026 cls = FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta);
1027 nlw = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);
1028 dev_info(dev, "link up, %s x%u %s\n",
1029 pci_speed_string(pcie_link_speed[cls]), nlw,
1030 ssc_good ? "(SSC)" : "(!SSC)");
1032 /* PCIe->SCB endian mode for BAR */
1033 tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
1034 u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN,
1035 PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK);
1036 writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
1038 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1041 * Enable CLKREQ# signalling include L1 Substate control of
1042 * the CLKREQ# signal and the external reference clock buffer.
1043 * meet requirement for Endpoints that require CLKREQ#
1044 * assertion to clock active within 400ns.
1046 tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
1047 tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK;
1050 * Refclk from RC should be gated with CLKREQ# input when
1051 * ASPM L0s,L1 is enabled => setting the CLKREQ_DEBUG_ENABLE
1054 tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK;
1055 tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
1057 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1062 /* L23 is a low-power PCIe link state */
1063 static void brcm_pcie_enter_l23(struct brcm_pcie *pcie)
1065 void __iomem *base = pcie->base;
1069 /* Assert request for L23 */
1070 tmp = readl(base + PCIE_MISC_PCIE_CTRL);
1071 u32p_replace_bits(&tmp, 1, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK);
1072 writel(tmp, base + PCIE_MISC_PCIE_CTRL);
1074 /* Wait up to 36 msec for L23 */
1075 tmp = readl(base + PCIE_MISC_PCIE_STATUS);
1076 l23 = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK, tmp);
1077 for (i = 0; i < 15 && !l23; i++) {
1078 usleep_range(2000, 2400);
1079 tmp = readl(base + PCIE_MISC_PCIE_STATUS);
1080 l23 = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK,
1085 dev_err(pcie->dev, "failed to enter low-power link state\n");
1088 static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start)
1090 static const u32 shifts[PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS] = {
1091 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT,
1092 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT,
1093 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT,};
1094 static const u32 masks[PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS] = {
1095 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK,
1096 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK,
1097 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK,};
1098 const int beg = start ? 0 : PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS - 1;
1099 const int end = start ? PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS : -1;
1100 u32 tmp, combined_mask = 0;
1102 void __iomem *base = pcie->base;
1105 for (i = beg; i != end; start ? i++ : i--) {
1106 val = start ? BIT_MASK(shifts[i]) : 0;
1107 tmp = readl(base + PCIE_DVT_PMU_PCIE_PHY_CTRL);
1108 tmp = (tmp & ~masks[i]) | (val & masks[i]);
1109 writel(tmp, base + PCIE_DVT_PMU_PCIE_PHY_CTRL);
1110 usleep_range(50, 200);
1111 combined_mask |= masks[i];
1114 tmp = readl(base + PCIE_DVT_PMU_PCIE_PHY_CTRL);
1115 val = start ? combined_mask : 0;
1117 ret = (tmp & combined_mask) == val ? 0 : -EIO;
1119 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop"));
1124 static inline int brcm_phy_start(struct brcm_pcie *pcie)
1126 return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0;
1129 static inline int brcm_phy_stop(struct brcm_pcie *pcie)
1131 return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0;
1134 static void brcm_pcie_turn_off(struct brcm_pcie *pcie)
1136 void __iomem *base = pcie->base;
1139 if (brcm_pcie_link_up(pcie))
1140 brcm_pcie_enter_l23(pcie);
1141 /* Assert fundamental reset */
1142 pcie->perst_set(pcie, 1);
1144 /* Deassert request for L23 in case it was asserted */
1145 tmp = readl(base + PCIE_MISC_PCIE_CTRL);
1146 u32p_replace_bits(&tmp, 0, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK);
1147 writel(tmp, base + PCIE_MISC_PCIE_CTRL);
1149 /* Turn off SerDes */
1150 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1151 u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
1152 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1154 /* Shutdown PCIe bridge */
1155 pcie->bridge_sw_init_set(pcie, 1);
1158 static int brcm_pcie_suspend(struct device *dev)
1160 struct brcm_pcie *pcie = dev_get_drvdata(dev);
1163 brcm_pcie_turn_off(pcie);
1164 ret = brcm_phy_stop(pcie);
1165 reset_control_rearm(pcie->rescal);
1166 clk_disable_unprepare(pcie->clk);
1171 static int brcm_pcie_resume(struct device *dev)
1173 struct brcm_pcie *pcie = dev_get_drvdata(dev);
1179 clk_prepare_enable(pcie->clk);
1181 ret = reset_control_reset(pcie->rescal);
1183 goto err_disable_clk;
1185 ret = brcm_phy_start(pcie);
1189 /* Take bridge out of reset so we can access the SERDES reg */
1190 pcie->bridge_sw_init_set(pcie, 0);
1192 /* SERDES_IDDQ = 0 */
1193 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1194 u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
1195 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1197 /* wait for serdes to be stable */
1200 ret = brcm_pcie_setup(pcie);
1205 brcm_msi_set_regs(pcie->msi);
1210 reset_control_rearm(pcie->rescal);
1212 clk_disable_unprepare(pcie->clk);
1216 static void __brcm_pcie_remove(struct brcm_pcie *pcie)
1218 brcm_msi_remove(pcie);
1219 brcm_pcie_turn_off(pcie);
1220 brcm_phy_stop(pcie);
1221 reset_control_rearm(pcie->rescal);
1222 clk_disable_unprepare(pcie->clk);
1225 static int brcm_pcie_remove(struct platform_device *pdev)
1227 struct brcm_pcie *pcie = platform_get_drvdata(pdev);
1228 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1230 pci_stop_root_bus(bridge->bus);
1231 pci_remove_root_bus(bridge->bus);
1232 __brcm_pcie_remove(pcie);
1237 static const struct of_device_id brcm_pcie_match[] = {
1238 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1239 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
1240 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1241 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1242 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
1243 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1247 static int brcm_pcie_probe(struct platform_device *pdev)
1249 struct device_node *np = pdev->dev.of_node, *msi_np;
1250 struct pci_host_bridge *bridge;
1251 const struct pcie_cfg_data *data;
1252 struct brcm_pcie *pcie;
1255 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
1259 data = of_device_get_match_data(&pdev->dev);
1261 pr_err("failed to look up compatible string\n");
1265 pcie = pci_host_bridge_priv(bridge);
1266 pcie->dev = &pdev->dev;
1268 pcie->reg_offsets = data->offsets;
1269 pcie->type = data->type;
1270 pcie->perst_set = data->perst_set;
1271 pcie->bridge_sw_init_set = data->bridge_sw_init_set;
1273 pcie->base = devm_platform_ioremap_resource(pdev, 0);
1274 if (IS_ERR(pcie->base))
1275 return PTR_ERR(pcie->base);
1277 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie");
1278 if (IS_ERR(pcie->clk))
1279 return PTR_ERR(pcie->clk);
1281 ret = of_pci_get_max_link_speed(np);
1282 pcie->gen = (ret < 0) ? 0 : ret;
1284 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc");
1285 pcie->l1ss = of_property_read_bool(np, "brcm,enable-l1ss");
1287 ret = clk_prepare_enable(pcie->clk);
1289 dev_err(&pdev->dev, "could not enable clock\n");
1292 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal");
1293 if (IS_ERR(pcie->rescal)) {
1294 clk_disable_unprepare(pcie->clk);
1295 return PTR_ERR(pcie->rescal);
1297 pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst");
1298 if (IS_ERR(pcie->perst_reset)) {
1299 clk_disable_unprepare(pcie->clk);
1300 return PTR_ERR(pcie->perst_reset);
1303 ret = reset_control_reset(pcie->rescal);
1305 dev_err(&pdev->dev, "failed to deassert 'rescal'\n");
1307 ret = brcm_phy_start(pcie);
1309 reset_control_rearm(pcie->rescal);
1310 clk_disable_unprepare(pcie->clk);
1314 ret = brcm_pcie_setup(pcie);
1318 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION);
1319 if (pcie->type == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) {
1320 dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n");
1325 msi_np = of_parse_phandle(pcie->np, "msi-parent", 0);
1326 if (pci_msi_enabled() && msi_np == pcie->np) {
1327 ret = brcm_pcie_enable_msi(pcie);
1329 dev_err(pcie->dev, "probe of internal MSI failed");
1334 bridge->ops = &brcm_pcie_ops;
1335 bridge->sysdata = pcie;
1337 platform_set_drvdata(pdev, pcie);
1339 return pci_host_probe(bridge);
1341 __brcm_pcie_remove(pcie);
1345 MODULE_DEVICE_TABLE(of, brcm_pcie_match);
1347 static const struct dev_pm_ops brcm_pcie_pm_ops = {
1348 .suspend = brcm_pcie_suspend,
1349 .resume = brcm_pcie_resume,
1352 static struct platform_driver brcm_pcie_driver = {
1353 .probe = brcm_pcie_probe,
1354 .remove = brcm_pcie_remove,
1356 .name = "brcm-pcie",
1357 .of_match_table = brcm_pcie_match,
1358 .pm = &brcm_pcie_pm_ops,
1361 module_platform_driver(brcm_pcie_driver);
1363 MODULE_LICENSE("GPL");
1364 MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");
1365 MODULE_AUTHOR("Broadcom");