1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
4 #include <linux/bitfield.h>
5 #include <linux/bitops.h>
7 #include <linux/compiler.h>
8 #include <linux/delay.h>
9 #include <linux/init.h>
10 #include <linux/interrupt.h>
12 #include <linux/iopoll.h>
13 #include <linux/ioport.h>
14 #include <linux/irqchip/chained_irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/kthread.h>
18 #include <linux/list.h>
19 #include <linux/log2.h>
20 #include <linux/module.h>
21 #include <linux/msi.h>
22 #include <linux/of_address.h>
23 #include <linux/of_irq.h>
24 #include <linux/of_pci.h>
25 #include <linux/of_platform.h>
26 #include <linux/pci.h>
27 #include <linux/pci-ecam.h>
28 #include <linux/printk.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/reset.h>
31 #include <linux/sizes.h>
32 #include <linux/slab.h>
33 #include <linux/string.h>
34 #include <linux/types.h>
38 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
39 #define BRCM_PCIE_CAP_REGS 0x00ac
41 /* Broadcom STB PCIe Register Offsets */
42 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
43 #define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
44 #define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0
46 #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
47 #define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
49 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc
50 #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00
52 #define PCIE_RC_TL_VDM_CTL0 0x0a20
53 #define PCIE_RC_TL_VDM_CTL0_VDM_ENABLED_MASK 0x10000
54 #define PCIE_RC_TL_VDM_CTL0_VDM_IGNORETAG_MASK 0x20000
55 #define PCIE_RC_TL_VDM_CTL0_VDM_IGNOREVNDRID_MASK 0x40000
57 #define PCIE_RC_TL_VDM_CTL1 0x0a0c
58 #define PCIE_RC_TL_VDM_CTL1_VDM_VNDRID0_MASK 0x0000ffff
59 #define PCIE_RC_TL_VDM_CTL1_VDM_VNDRID1_MASK 0xffff0000
61 #define PCIE_RC_DL_MDIO_ADDR 0x1100
62 #define PCIE_RC_DL_MDIO_WR_DATA 0x1104
63 #define PCIE_RC_DL_MDIO_RD_DATA 0x1108
65 #define PCIE_RC_PL_PHY_CTL_15 0x184c
66 #define PCIE_RC_PL_PHY_CTL_15_DIS_PLL_PD_MASK 0x400000
67 #define PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK 0xff
69 #define PCIE_MISC_MISC_CTRL 0x4008
70 #define PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK 0x80
71 #define PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK 0x400
72 #define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
73 #define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
74 #define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
76 #define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
77 #define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x07c00000
78 #define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x0000001f
79 #define SCB_SIZE_MASK(x) PCIE_MISC_MISC_CTRL_SCB ## x ## _SIZE_MASK
81 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
82 #define PCIE_MEM_WIN0_LO(win) \
83 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + ((win) * 8)
85 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
86 #define PCIE_MEM_WIN0_HI(win) \
87 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + ((win) * 8)
89 #define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
90 #define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
91 #define PCIE_MISC_RC_BAR1_CONFIG_HI 0x4030
93 #define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
94 #define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
95 #define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
97 #define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
98 #define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
99 #define PCIE_MISC_RC_BAR3_CONFIG_HI 0x4040
101 #define PCIE_MISC_MSI_BAR_CONFIG_LO 0x4044
102 #define PCIE_MISC_MSI_BAR_CONFIG_HI 0x4048
104 #define PCIE_MISC_MSI_DATA_CONFIG 0x404c
105 #define PCIE_MISC_MSI_DATA_CONFIG_VAL_32 0xffe06540
106 #define PCIE_MISC_MSI_DATA_CONFIG_VAL_8 0xfff86540
108 #define PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT 0x405c
110 #define PCIE_MISC_PCIE_CTRL 0x4064
111 #define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
112 #define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
114 #define PCIE_MISC_PCIE_STATUS 0x4068
115 #define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
116 #define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK_2712 0x40
117 #define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
118 #define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
119 #define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
121 #define PCIE_MISC_REVISION 0x406c
122 #define BRCM_PCIE_HW_REV_33 0x0303
123 #define BRCM_PCIE_HW_REV_3_20 0x0320
125 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
126 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
127 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
128 #define PCIE_MEM_WIN0_BASE_LIMIT(win) \
129 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + ((win) * 4)
131 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
132 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
133 #define PCIE_MEM_WIN0_BASE_HI(win) \
134 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + ((win) * 8)
136 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
137 #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
138 #define PCIE_MEM_WIN0_LIMIT_HI(win) \
139 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + ((win) * 8)
141 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG pcie->reg_offsets[PCIE_HARD_DEBUG]
142 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
143 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_PERST_ASSERT_MASK 0x8
144 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
145 #define PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x00800000
146 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK 0x00200000
148 #define PCIE_MISC_CTRL_1 0x40A0
149 #define PCIE_MISC_CTRL_1_OUTBOUND_TC_MASK 0xf
150 #define PCIE_MISC_CTRL_1_OUTBOUND_NO_SNOOP_MASK BIT(3)
151 #define PCIE_MISC_CTRL_1_OUTBOUND_RO_MASK BIT(4)
152 #define PCIE_MISC_CTRL_1_EN_VDM_QOS_CONTROL_MASK BIT(5)
154 #define PCIE_MISC_UBUS_CTRL 0x40a4
155 #define PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK BIT(13)
156 #define PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_DECERR_DIS_MASK BIT(19)
158 #define PCIE_MISC_UBUS_TIMEOUT 0x40A8
160 #define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP 0x40ac
161 #define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_ENABLE_MASK BIT(0)
162 #define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_HI 0x40b0
164 #define PCIE_MISC_UBUS_BAR2_CONFIG_REMAP 0x40b4
165 #define PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_ENABLE_MASK BIT(0)
167 /* Additional RC BARs */
168 #define PCIE_MISC_RC_BAR_CONFIG_LO_SIZE_MASK 0x1f
169 #define PCIE_MISC_RC_BAR4_CONFIG_LO 0x40d4
170 #define PCIE_MISC_RC_BAR4_CONFIG_HI 0x40d8
172 #define PCIE_MISC_RC_BAR10_CONFIG_LO 0x4104
173 #define PCIE_MISC_RC_BAR10_CONFIG_HI 0x4108
175 #define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE 0x1
176 #define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK 0xfffff000
177 #define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK 0xff
178 #define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_LO 0x410c
179 #define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_HI 0x4110
181 #define PCIE_MISC_UBUS_BAR10_CONFIG_REMAP_LO 0x413c
182 #define PCIE_MISC_UBUS_BAR10_CONFIG_REMAP_HI 0x4140
184 /* AXI priority forwarding - automatic level-based */
185 #define PCIE_MISC_TC_QUEUE_TO_QOS_MAP(x) (0x4160 - (x) * 4)
186 /* Defined in quarter-fullness */
187 #define QUEUE_THRESHOLD_34_TO_QOS_MAP_SHIFT 12
188 #define QUEUE_THRESHOLD_23_TO_QOS_MAP_SHIFT 8
189 #define QUEUE_THRESHOLD_12_TO_QOS_MAP_SHIFT 4
190 #define QUEUE_THRESHOLD_01_TO_QOS_MAP_SHIFT 0
191 #define QUEUE_THRESHOLD_MASK 0xf
193 /* VDM messages indexing TCs to AXI priorities */
195 #define PCIE_MISC_VDM_PRIORITY_TO_QOS_MAP_HI 0x4164
197 #define PCIE_MISC_VDM_PRIORITY_TO_QOS_MAP_LO 0x4168
198 #define VDM_PRIORITY_TO_QOS_MAP_SHIFT(x) (4 * (x))
199 #define VDM_PRIORITY_TO_QOS_MAP_MASK 0xf
201 #define PCIE_MISC_AXI_INTF_CTRL 0x416C
202 #define AXI_REQFIFO_EN_QOS_PROPAGATION BIT(7)
203 #define AXI_BRIDGE_LOW_LATENCY_MODE BIT(6)
204 #define AXI_MASTER_MAX_OUTSTANDING_REQUESTS_MASK 0x3f
206 #define PCIE_MISC_AXI_READ_ERROR_DATA 0x4170
208 #define PCIE_INTR2_CPU_BASE (pcie->reg_offsets[INTR2_CPU])
209 #define PCIE_MSI_INTR2_BASE 0x4500
210 /* Offsets from PCIE_INTR2_CPU_BASE and PCIE_MSI_INTR2_BASE */
211 #define MSI_INT_STATUS 0x0
212 #define MSI_INT_CLR 0x8
213 #define MSI_INT_MASK_SET 0x10
214 #define MSI_INT_MASK_CLR 0x14
216 #define PCIE_EXT_CFG_DATA 0x8000
217 #define PCIE_EXT_CFG_INDEX 0x9000
219 #define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
220 #define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
222 #define RGR1_SW_INIT_1_INIT_GENERIC_MASK 0x2
223 #define RGR1_SW_INIT_1_INIT_GENERIC_SHIFT 0x1
224 #define RGR1_SW_INIT_1_INIT_7278_MASK 0x1
225 #define RGR1_SW_INIT_1_INIT_7278_SHIFT 0x0
227 /* PCIe parameters */
228 #define BRCM_NUM_PCIE_OUT_WINS 0x4
229 #define BRCM_INT_PCI_MSI_NR 32
230 #define BRCM_INT_PCI_MSI_LEGACY_NR 8
231 #define BRCM_INT_PCI_MSI_SHIFT 0
232 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
233 #define BRCM_INT_PCI_MSI_LEGACY_MASK GENMASK(31, \
234 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
236 /* MSI target addresses */
237 #define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
238 #define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
241 #define MDIO_PORT0 0x0
242 #define MDIO_DATA_MASK 0x7fffffff
243 #define MDIO_PORT_MASK 0xf0000
244 #define MDIO_REGAD_MASK 0xffff
245 #define MDIO_CMD_MASK 0xfff00000
246 #define MDIO_CMD_READ 0x1
247 #define MDIO_CMD_WRITE 0x0
248 #define MDIO_DATA_DONE_MASK 0x80000000
249 #define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
250 #define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
251 #define SSC_REGS_ADDR 0x1100
252 #define SET_ADDR_OFFSET 0x1f
253 #define SSC_CNTL_OFFSET 0x2
254 #define SSC_CNTL_OVRD_EN_MASK 0x8000
255 #define SSC_CNTL_OVRD_VAL_MASK 0x4000
256 #define SSC_STATUS_OFFSET 0x1
257 #define SSC_STATUS_SSC_MASK 0x400
258 #define SSC_STATUS_PLL_LOCK_MASK 0x800
259 #define PCIE_BRCM_MAX_MEMC 3
261 #define IDX_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_INDEX])
262 #define DATA_ADDR(pcie) (pcie->reg_offsets[EXT_CFG_DATA])
263 #define PCIE_RGR1_SW_INIT_1(pcie) (pcie->reg_offsets[RGR1_SW_INIT_1])
265 /* Rescal registers */
266 #define PCIE_DVT_PMU_PCIE_PHY_CTRL 0xc700
267 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS 0x3
268 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK 0x4
269 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT 0x2
270 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK 0x2
271 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT 0x1
272 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK 0x1
273 #define PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT 0x0
275 /* Forward declarations */
287 RGR1_SW_INIT_1_INIT_MASK,
288 RGR1_SW_INIT_1_INIT_SHIFT,
301 struct pcie_cfg_data {
303 const enum pcie_type type;
304 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
305 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
306 bool (*rc_mode)(struct brcm_pcie *pcie);
309 struct subdev_regulators {
310 unsigned int num_supplies;
311 struct regulator_bulk_data supplies[];
317 struct device_node *np;
318 struct irq_domain *msi_domain;
319 struct irq_domain *inner_domain;
320 struct mutex lock; /* guards the alloc/free operations */
323 DECLARE_BITMAP(used, 64);
325 /* Some chips have MSIs in bits [31..24] of a shared register. */
327 int nr; /* No. of MSI available, depends on chip */
328 /* This is the base pointer for interrupt status/set/clr regs */
329 void __iomem *intr_base;
332 /* Internal PCIe Host Controller Information.*/
337 struct device_node *np;
343 struct brcm_msi *msi;
344 const int *reg_offsets;
346 struct reset_control *rescal;
347 struct reset_control *perst_reset;
348 struct reset_control *bridge_reset;
350 u64 memc_size[PCIE_BRCM_MAX_MEMC];
353 void (*perst_set)(struct brcm_pcie *pcie, u32 val);
354 void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
355 bool (*rc_mode)(struct brcm_pcie *pcie);
356 struct subdev_regulators *sr;
357 bool ep_wakeup_capable;
361 static inline bool is_bmips(const struct brcm_pcie *pcie)
363 return pcie->type == BCM7435 || pcie->type == BCM7425;
367 * This is to convert the size of the inbound "BAR" region to the
368 * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
370 static int brcm_pcie_encode_ibar_size(u64 size)
372 int log2_in = ilog2(size);
374 if (log2_in >= 12 && log2_in <= 15)
375 /* Covers 4KB to 32KB (inclusive) */
376 return (log2_in - 12) + 0x1c;
377 else if (log2_in >= 16 && log2_in <= 36)
378 /* Covers 64KB to 64GB, (inclusive) */
380 /* Something is awry so disable */
384 static u32 brcm_pcie_mdio_form_pkt(int port, int regad, int cmd)
388 pkt |= FIELD_PREP(MDIO_PORT_MASK, port);
389 pkt |= FIELD_PREP(MDIO_REGAD_MASK, regad);
390 pkt |= FIELD_PREP(MDIO_CMD_MASK, cmd);
395 /* negative return value indicates error */
396 static int brcm_pcie_mdio_read(void __iomem *base, u8 port, u8 regad, u32 *val)
401 writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_READ),
402 base + PCIE_RC_DL_MDIO_ADDR);
403 readl(base + PCIE_RC_DL_MDIO_ADDR);
404 err = readl_poll_timeout_atomic(base + PCIE_RC_DL_MDIO_RD_DATA, data,
405 MDIO_RD_DONE(data), 10, 100);
406 *val = FIELD_GET(MDIO_DATA_MASK, data);
411 /* negative return value indicates error */
412 static int brcm_pcie_mdio_write(void __iomem *base, u8 port,
413 u8 regad, u16 wrdata)
418 writel(brcm_pcie_mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
419 base + PCIE_RC_DL_MDIO_ADDR);
420 readl(base + PCIE_RC_DL_MDIO_ADDR);
421 writel(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA);
423 err = readw_poll_timeout_atomic(base + PCIE_RC_DL_MDIO_WR_DATA, data,
424 MDIO_WT_DONE(data), 10, 100);
429 * Configures device for Spread Spectrum Clocking (SSC) mode; a negative
430 * return value indicates error.
432 static int brcm_pcie_set_ssc(struct brcm_pcie *pcie)
438 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET,
443 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0,
444 SSC_CNTL_OFFSET, &tmp);
448 u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_EN_MASK);
449 u32p_replace_bits(&tmp, 1, SSC_CNTL_OVRD_VAL_MASK);
450 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0,
451 SSC_CNTL_OFFSET, tmp);
455 usleep_range(1000, 2000);
456 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0,
457 SSC_STATUS_OFFSET, &tmp);
461 ssc = FIELD_GET(SSC_STATUS_SSC_MASK, tmp);
462 pll = FIELD_GET(SSC_STATUS_PLL_LOCK_MASK, tmp);
464 return ssc && pll ? 0 : -EIO;
467 static void brcm_pcie_munge_pll(struct brcm_pcie *pcie)
469 //print "MDIO block 0x1600 written per Dannys instruction"
470 //tmp = pcie_mdio_write(phyad, &h16&, &h50b9&)
471 //tmp = pcie_mdio_write(phyad, &h17&, &hbd1a&)
472 //tmp = pcie_mdio_write(phyad, &h1b&, &h5030&)
473 //tmp = pcie_mdio_write(phyad, &h1e&, &h0007&)
477 u8 regs[] = { 0x16, 0x17, 0x18, 0x19, 0x1b, 0x1c, 0x1e };
478 u16 data[] = { 0x50b9, 0xbda1, 0x0094, 0x97b4, 0x5030, 0x5030, 0x0007 };
480 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET,
482 for (i = 0; i < ARRAY_SIZE(regs); i++) {
483 brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, regs[i], &tmp);
484 dev_dbg(pcie->dev, "PCIE MDIO pre_refclk 0x%02x = 0x%04x\n",
487 for (i = 0; i < ARRAY_SIZE(regs); i++) {
488 brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, regs[i], data[i]);
489 brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, regs[i], &tmp);
490 dev_dbg(pcie->dev, "PCIE MDIO post_refclk 0x%02x = 0x%04x\n",
493 usleep_range(100, 200);
496 /* Limits operation to a specific generation (1, 2, or 3) */
497 static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen)
499 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
500 u32 lnkcap = readl(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
502 lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
503 writel(lnkcap, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
505 lnkctl2 = (lnkctl2 & ~0xf) | gen;
506 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
509 static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
510 unsigned int win, u64 cpu_addr,
511 u64 pcie_addr, u64 size)
513 u32 cpu_addr_mb_high, limit_addr_mb_high;
514 phys_addr_t cpu_addr_mb, limit_addr_mb;
518 /* Set the base of the pcie_addr window */
519 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win));
520 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win));
522 /* Write the addr base & limit lower bits (in MBs) */
523 cpu_addr_mb = cpu_addr / SZ_1M;
524 limit_addr_mb = (cpu_addr + size - 1) / SZ_1M;
526 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
527 u32p_replace_bits(&tmp, cpu_addr_mb,
528 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK);
529 u32p_replace_bits(&tmp, limit_addr_mb,
530 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK);
531 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win));
536 /* Write the cpu & limit addr upper bits */
538 HWEIGHT32(PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK);
540 cpu_addr_mb_high = cpu_addr_mb >> high_addr_shift;
541 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win));
542 u32p_replace_bits(&tmp, cpu_addr_mb_high,
543 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK);
544 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win));
546 limit_addr_mb_high = limit_addr_mb >> high_addr_shift;
547 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
548 u32p_replace_bits(&tmp, limit_addr_mb_high,
549 PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK);
550 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win));
553 static void brcm_pcie_set_tc_qos(struct brcm_pcie *pcie)
558 if (pcie->type != BCM2712)
561 /* XXX: BCM2712C0 is broken, disable the forwarding search */
562 reg = readl(pcie->base + PCIE_MISC_AXI_INTF_CTRL);
563 reg &= ~AXI_REQFIFO_EN_QOS_PROPAGATION;
564 writel(reg, pcie->base + PCIE_MISC_AXI_INTF_CTRL);
566 /* Disable VDM reception by default - QoS map defaults to 0 */
567 reg = readl(pcie->base + PCIE_MISC_CTRL_1);
568 reg &= ~PCIE_MISC_CTRL_1_EN_VDM_QOS_CONTROL_MASK;
569 writel(reg, pcie->base + PCIE_MISC_CTRL_1);
571 if (!of_property_read_u32(pcie->np, "brcm,fifo-qos-map", &pcie->qos_map)) {
573 * Backpressure mode - bottom 4 nibbles are QoS for each
574 * quartile of FIFO level. Each TC gets the same map, because
575 * this mode is intended for nonrealtime EPs.
578 pcie->qos_map &= 0x0000ffff;
579 for (i = 0; i < 8; i++)
580 writel(pcie->qos_map, pcie->base + PCIE_MISC_TC_QUEUE_TO_QOS_MAP(i));
585 if (!of_property_read_u32(pcie->np, "brcm,vdm-qos-map", &pcie->qos_map)) {
587 reg = readl(pcie->base + PCIE_MISC_CTRL_1);
588 reg |= PCIE_MISC_CTRL_1_EN_VDM_QOS_CONTROL_MASK;
589 writel(reg, pcie->base + PCIE_MISC_CTRL_1);
591 /* No forwarding means no point separating panic priorities from normal */
592 writel(pcie->qos_map, pcie->base + PCIE_MISC_VDM_PRIORITY_TO_QOS_MAP_LO);
593 writel(pcie->qos_map, pcie->base + PCIE_MISC_VDM_PRIORITY_TO_QOS_MAP_HI);
595 /* Match Vendor ID of 0 */
596 writel(0, pcie->base + PCIE_RC_TL_VDM_CTL1);
597 /* Forward VDMs to priority interface - at least the rx counters work */
598 reg = readl(pcie->base + PCIE_RC_TL_VDM_CTL0);
599 reg |= PCIE_RC_TL_VDM_CTL0_VDM_ENABLED_MASK |
600 PCIE_RC_TL_VDM_CTL0_VDM_IGNORETAG_MASK |
601 PCIE_RC_TL_VDM_CTL0_VDM_IGNOREVNDRID_MASK;
602 writel(reg, pcie->base + PCIE_RC_TL_VDM_CTL0);
606 static void brcm_pcie_config_clkreq(struct brcm_pcie *pcie)
608 void __iomem *base = pcie->base;
609 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
610 int domain = pci_domain_nr(bridge->bus);
611 const struct pci_bus *bus = pci_find_bus(domain, 1);
612 struct pci_dev *pdev = (struct pci_dev *)bus->devices.next;
613 u32 tmp, link_cap = 0;
618 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
619 if ((link_cap & PCI_EXP_LNKCAP_CLKPM))
622 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &link_ctl);
623 if (!(link_ctl & PCI_EXP_LNKCTL_CLKREQ_EN))
626 if (pcie->l1ss && pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS))
629 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
630 tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
631 tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK;
634 tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_L1SS_ENABLE_MASK;
636 tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK;
638 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
640 if (substates || clkpm)
641 dev_info(pcie->dev, "clkreq control enabled\n");
644 static struct irq_chip brcm_msi_irq_chip = {
645 .name = "BRCM STB PCIe MSI",
646 .irq_ack = irq_chip_ack_parent,
647 .irq_mask = pci_msi_mask_irq,
648 .irq_unmask = pci_msi_unmask_irq,
651 static struct msi_domain_info brcm_msi_domain_info = {
652 .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
653 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
654 .chip = &brcm_msi_irq_chip,
657 static void brcm_pcie_msi_isr(struct irq_desc *desc)
659 struct irq_chip *chip = irq_desc_get_chip(desc);
660 unsigned long status, virq;
661 struct brcm_msi *msi;
665 chained_irq_enter(chip, desc);
666 msi = irq_desc_get_handler_data(desc);
669 status = readl(msi->intr_base + MSI_INT_STATUS);
670 status >>= msi->legacy_shift;
672 for_each_set_bit(bit, &status, BRCM_INT_PCI_MSI_NR/*msi->nr*/) {
675 virq = irq_find_mapping(msi->inner_domain, bit);
678 dev_dbg(dev, "MSI -> %ld\n", virq);
679 generic_handle_irq(virq);
681 virq = irq_find_mapping(msi->inner_domain, bit + 32);
684 dev_dbg(dev, "MSI -> %ld\n", virq);
685 generic_handle_irq(virq);
688 dev_dbg(dev, "unexpected MSI\n");
691 chained_irq_exit(chip, desc);
694 static void brcm_msi_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
696 struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
698 msg->address_lo = lower_32_bits(msi->target_addr);
699 msg->address_hi = upper_32_bits(msi->target_addr);
700 msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL_32) | (data->hwirq & 0x1f);
703 static int brcm_msi_set_affinity(struct irq_data *irq_data,
704 const struct cpumask *mask, bool force)
709 static void brcm_msi_ack_irq(struct irq_data *data)
711 struct brcm_msi *msi = irq_data_get_irq_chip_data(data);
712 const int shift_amt = (data->hwirq & 0x1f) + msi->legacy_shift;
714 writel(1 << shift_amt, msi->intr_base + MSI_INT_CLR);
718 static struct irq_chip brcm_msi_bottom_irq_chip = {
719 .name = "BRCM STB MSI",
720 .irq_compose_msi_msg = brcm_msi_compose_msi_msg,
721 .irq_set_affinity = brcm_msi_set_affinity,
722 .irq_ack = brcm_msi_ack_irq,
725 static int brcm_msi_alloc(struct brcm_msi *msi, unsigned int nr_irqs)
729 mutex_lock(&msi->lock);
730 hwirq = bitmap_find_free_region(msi->used, msi->nr,
731 order_base_2(nr_irqs));
732 mutex_unlock(&msi->lock);
737 static void brcm_msi_free(struct brcm_msi *msi, unsigned long hwirq,
738 unsigned int nr_irqs)
740 mutex_lock(&msi->lock);
741 bitmap_release_region(msi->used, hwirq, order_base_2(nr_irqs));
742 mutex_unlock(&msi->lock);
745 static int brcm_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
746 unsigned int nr_irqs, void *args)
748 struct brcm_msi *msi = domain->host_data;
751 hwirq = brcm_msi_alloc(msi, nr_irqs);
756 for (i = 0; i < nr_irqs; i++)
757 irq_domain_set_info(domain, virq + i, hwirq + i,
758 &brcm_msi_bottom_irq_chip, domain->host_data,
759 handle_edge_irq, NULL, NULL);
763 static void brcm_irq_domain_free(struct irq_domain *domain,
764 unsigned int virq, unsigned int nr_irqs)
766 struct irq_data *d = irq_domain_get_irq_data(domain, virq);
767 struct brcm_msi *msi = irq_data_get_irq_chip_data(d);
769 brcm_msi_free(msi, d->hwirq, nr_irqs);
772 static const struct irq_domain_ops msi_domain_ops = {
773 .alloc = brcm_irq_domain_alloc,
774 .free = brcm_irq_domain_free,
777 static int brcm_allocate_domains(struct brcm_msi *msi)
779 struct fwnode_handle *fwnode = of_node_to_fwnode(msi->np);
780 struct device *dev = msi->dev;
782 msi->inner_domain = irq_domain_add_linear(NULL, msi->nr, &msi_domain_ops, msi);
783 if (!msi->inner_domain) {
784 dev_err(dev, "failed to create IRQ domain\n");
788 msi->msi_domain = pci_msi_create_irq_domain(fwnode,
789 &brcm_msi_domain_info,
791 if (!msi->msi_domain) {
792 dev_err(dev, "failed to create MSI domain\n");
793 irq_domain_remove(msi->inner_domain);
800 static void brcm_free_domains(struct brcm_msi *msi)
802 irq_domain_remove(msi->msi_domain);
803 irq_domain_remove(msi->inner_domain);
806 static void brcm_msi_remove(struct brcm_pcie *pcie)
808 struct brcm_msi *msi = pcie->msi;
812 irq_set_chained_handler_and_data(msi->irq, NULL, NULL);
813 brcm_free_domains(msi);
816 static void brcm_msi_set_regs(struct brcm_msi *msi)
818 u32 val = msi->legacy ? BRCM_INT_PCI_MSI_LEGACY_MASK :
819 BRCM_INT_PCI_MSI_MASK;
821 writel(val, msi->intr_base + MSI_INT_MASK_CLR);
822 writel(val, msi->intr_base + MSI_INT_CLR);
825 * The 0 bit of PCIE_MISC_MSI_BAR_CONFIG_LO is repurposed to MSI
826 * enable, which we set to 1.
828 writel(lower_32_bits(msi->target_addr) | 0x1,
829 msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO);
830 writel(upper_32_bits(msi->target_addr),
831 msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI);
833 val = msi->legacy ? PCIE_MISC_MSI_DATA_CONFIG_VAL_8 : PCIE_MISC_MSI_DATA_CONFIG_VAL_32;
834 writel(val, msi->base + PCIE_MISC_MSI_DATA_CONFIG);
837 static int brcm_pcie_enable_msi(struct brcm_pcie *pcie)
839 struct brcm_msi *msi;
841 struct device *dev = pcie->dev;
843 irq = irq_of_parse_and_map(dev->of_node, 1);
845 dev_err(dev, "cannot map MSI interrupt\n");
849 msi = devm_kzalloc(dev, sizeof(struct brcm_msi), GFP_KERNEL);
853 mutex_init(&msi->lock);
855 msi->base = pcie->base;
857 msi->target_addr = pcie->msi_target_addr;
859 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33;
862 * Sanity check to make sure that the 'used' bitmap in struct brcm_msi
865 BUILD_BUG_ON(BRCM_INT_PCI_MSI_LEGACY_NR > BRCM_INT_PCI_MSI_NR);
868 msi->intr_base = msi->base + PCIE_INTR2_CPU_BASE;
869 msi->nr = BRCM_INT_PCI_MSI_LEGACY_NR;
870 msi->legacy_shift = 24;
872 msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE;
873 msi->nr = 64; //BRCM_INT_PCI_MSI_NR;
874 msi->legacy_shift = 0;
877 ret = brcm_allocate_domains(msi);
881 irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi);
883 brcm_msi_set_regs(msi);
889 /* The controller is capable of serving in both RC and EP roles */
890 static bool brcm_pcie_rc_mode_generic(struct brcm_pcie *pcie)
892 void __iomem *base = pcie->base;
893 u32 val = readl(base + PCIE_MISC_PCIE_STATUS);
895 return !!FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK, val);
898 static bool brcm_pcie_rc_mode_2712(struct brcm_pcie *pcie)
900 void __iomem *base = pcie->base;
901 u32 val = readl(base + PCIE_MISC_PCIE_STATUS);
903 return !!FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK_2712, val) | 1; //XXX
906 static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
908 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS);
909 u32 dla = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK, val);
910 u32 plu = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK, val);
915 static void __iomem *brcm_pcie_map_bus(struct pci_bus *bus,
916 unsigned int devfn, int where)
918 struct brcm_pcie *pcie = bus->sysdata;
919 void __iomem *base = pcie->base;
922 /* Accesses to the RC go right to the RC registers if !devfn */
923 if (pci_is_root_bus(bus))
924 return devfn ? NULL : base + PCIE_ECAM_REG(where);
926 /* An access to our HW w/o link-up will cause a CPU Abort */
927 if (!brcm_pcie_link_up(pcie))
930 /* For devices, write to the config space index register */
931 idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0);
932 writel(idx, pcie->base + PCIE_EXT_CFG_INDEX);
933 return base + PCIE_EXT_CFG_DATA + PCIE_ECAM_REG(where);
936 static void __iomem *brcm7425_pcie_map_bus(struct pci_bus *bus,
937 unsigned int devfn, int where)
939 struct brcm_pcie *pcie = bus->sysdata;
940 void __iomem *base = pcie->base;
943 /* Accesses to the RC go right to the RC registers if !devfn */
944 if (pci_is_root_bus(bus))
945 return devfn ? NULL : base + PCIE_ECAM_REG(where);
947 /* An access to our HW w/o link-up will cause a CPU Abort */
948 if (!brcm_pcie_link_up(pcie))
951 /* For devices, write to the config space index register */
952 idx = PCIE_ECAM_OFFSET(bus->number, devfn, where);
953 writel(idx, base + IDX_ADDR(pcie));
954 return base + DATA_ADDR(pcie);
957 static void brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val)
959 u32 tmp, mask = RGR1_SW_INIT_1_INIT_GENERIC_MASK;
960 u32 shift = RGR1_SW_INIT_1_INIT_GENERIC_SHIFT;
962 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
963 tmp = (tmp & ~mask) | ((val << shift) & mask);
964 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
967 static void brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val)
969 u32 tmp, mask = RGR1_SW_INIT_1_INIT_7278_MASK;
970 u32 shift = RGR1_SW_INIT_1_INIT_7278_SHIFT;
972 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
973 tmp = (tmp & ~mask) | ((val << shift) & mask);
974 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
977 static void brcm_pcie_bridge_sw_init_set_2712(struct brcm_pcie *pcie, u32 val)
979 if (WARN_ONCE(!pcie->bridge_reset,
980 "missing bridge reset controller\n"))
984 reset_control_assert(pcie->bridge_reset);
986 reset_control_deassert(pcie->bridge_reset);
989 static void brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val)
991 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n"))
995 reset_control_assert(pcie->perst_reset);
997 reset_control_deassert(pcie->perst_reset);
1000 static void brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val)
1004 /* Perst bit has moved and assert value is 0 */
1005 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL);
1006 u32p_replace_bits(&tmp, !val, PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK);
1007 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL);
1010 static void brcm_pcie_perst_set_2712(struct brcm_pcie *pcie, u32 val)
1014 /* Perst bit has moved and assert value is 0 */
1015 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL);
1016 u32p_replace_bits(&tmp, !val, PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK);
1017 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL);
1020 static void brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val)
1024 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
1025 u32p_replace_bits(&tmp, val, PCIE_RGR1_SW_INIT_1_PERST_MASK);
1026 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie));
1029 static int brcm_pcie_get_rc_bar2_size_and_offset(struct brcm_pcie *pcie,
1031 u64 *rc_bar2_offset)
1033 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1034 struct resource_entry *entry;
1035 struct device *dev = pcie->dev;
1036 u64 lowest_pcie_addr = ~(u64)0;
1040 resource_list_for_each_entry(entry, &bridge->dma_ranges) {
1041 u64 pcie_beg = entry->res->start - entry->offset;
1043 size += entry->res->end - entry->res->start + 1;
1044 if (pcie_beg < lowest_pcie_addr)
1045 lowest_pcie_addr = pcie_beg;
1046 if (pcie->type == BCM2711 || pcie->type == BCM2712)
1047 break; // Only consider the first entry
1050 if (lowest_pcie_addr == ~(u64)0) {
1051 dev_err(dev, "DT node has no dma-ranges\n");
1055 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1,
1056 PCIE_BRCM_MAX_MEMC);
1059 /* Make an educated guess */
1061 pcie->memc_size[0] = 1ULL << fls64(size - 1);
1063 pcie->num_memc = ret;
1066 /* Each memc is viewed through a "port" that is a power of 2 */
1067 for (i = 0, size = 0; i < pcie->num_memc; i++)
1068 size += pcie->memc_size[i];
1070 /* System memory starts at this address in PCIe-space */
1071 *rc_bar2_offset = lowest_pcie_addr;
1072 /* The sum of all memc views must also be a power of 2 */
1073 *rc_bar2_size = 1ULL << fls64(size - 1);
1076 * We validate the inbound memory view even though we should trust
1077 * whatever the device-tree provides. This is because of an HW issue on
1078 * early Raspberry Pi 4's revisions (bcm2711). It turns out its
1079 * firmware has to dynamically edit dma-ranges due to a bug on the
1080 * PCIe controller integration, which prohibits any access above the
1081 * lower 3GB of memory. Given this, we decided to keep the dma-ranges
1082 * in check, avoiding hard to debug device-tree related issues in the
1085 * The PCIe host controller by design must set the inbound viewport to
1086 * be a contiguous arrangement of all of the system's memory. In
1087 * addition, its size mut be a power of two. To further complicate
1088 * matters, the viewport must start on a pcie-address that is aligned
1089 * on a multiple of its size. If a portion of the viewport does not
1090 * represent system memory -- e.g. 3GB of memory requires a 4GB
1091 * viewport -- we can map the outbound memory in or after 3GB and even
1092 * though the viewport will overlap the outbound memory the controller
1093 * will know to send outbound memory downstream and everything else
1098 * - The best-case scenario, memory up to 3GB, is to place the inbound
1099 * region in the first 4GB of pcie-space, as some legacy devices can
1100 * only address 32bits. We would also like to put the MSI under 4GB
1101 * as well, since some devices require a 32bit MSI target address.
1103 * - If the system memory is 4GB or larger we cannot start the inbound
1104 * region at location 0 (since we have to allow some space for
1105 * outbound memory @ 3GB). So instead it will start at the 1x
1106 * multiple of its size
1108 if (!*rc_bar2_size || (*rc_bar2_offset & (*rc_bar2_size - 1)) ||
1109 (*rc_bar2_offset < SZ_4G && *rc_bar2_offset > SZ_2G)) {
1110 dev_err(dev, "Invalid rc_bar2_offset/size: size 0x%llx, off 0x%llx\n",
1111 *rc_bar2_size, *rc_bar2_offset);
1118 static int brcm_pcie_get_rc_bar_n(struct brcm_pcie *pcie,
1124 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1125 struct resource_entry *entry;
1128 resource_list_for_each_entry(entry, &bridge->dma_ranges) {
1130 *rc_bar_cpu = entry->res->start;
1131 *rc_bar_size = entry->res->end - entry->res->start + 1;
1132 *rc_bar_pci = entry->res->start - entry->offset;
1142 static int brcm_pcie_setup(struct brcm_pcie *pcie)
1144 u64 rc_bar2_offset, rc_bar2_size;
1145 void __iomem *base = pcie->base;
1146 struct pci_host_bridge *bridge;
1147 struct resource_entry *entry;
1148 u32 tmp, burst, aspm_support;
1149 int num_out_wins = 0;
1150 int ret, memc, count, i;
1152 /* Reset the bridge */
1153 pcie->bridge_sw_init_set(pcie, 1);
1155 /* Ensure that PERST# is asserted; some bootloaders may deassert it. */
1156 if (pcie->type == BCM2711)
1157 pcie->perst_set(pcie, 1);
1159 usleep_range(100, 200);
1161 /* Take the bridge out of reset */
1162 pcie->bridge_sw_init_set(pcie, 0);
1164 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1166 tmp &= ~PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
1168 tmp &= ~PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK;
1169 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1170 /* Wait for SerDes to be stable */
1171 usleep_range(100, 200);
1173 if (pcie->type == BCM2712) {
1174 /* Allow a 54MHz (xosc) refclk source */
1175 brcm_pcie_munge_pll(pcie);
1176 /* Fix for L1SS errata */
1177 tmp = readl(base + PCIE_RC_PL_PHY_CTL_15);
1178 tmp &= ~PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK;
1179 /* PM clock period is 18.52ns (round down) */
1181 writel(tmp, base + PCIE_RC_PL_PHY_CTL_15);
1185 * SCB_MAX_BURST_SIZE is a two bit field. For GENERIC chips it
1186 * is encoded as 0=128, 1=256, 2=512, 3=Rsvd, for BCM7278 it
1187 * is encoded as 0=Rsvd, 1=128, 2=256, 3=512.
1190 burst = 0x1; /* 256 bytes */
1191 else if (pcie->type == BCM2711)
1192 burst = 0x0; /* 128 bytes */
1193 else if (pcie->type == BCM2712)
1194 burst = 0x1; /* 128 bytes */
1195 else if (pcie->type == BCM7278)
1196 burst = 0x3; /* 512 bytes */
1198 burst = 0x2; /* 512 bytes */
1201 * Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN,
1204 tmp = readl(base + PCIE_MISC_MISC_CTRL);
1205 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK);
1206 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK);
1207 u32p_replace_bits(&tmp, burst, PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK);
1208 if (pcie->rcb_mps_mode)
1209 u32p_replace_bits(&tmp, 1, PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK);
1210 writel(tmp, base + PCIE_MISC_MISC_CTRL);
1212 brcm_pcie_set_tc_qos(pcie);
1214 ret = brcm_pcie_get_rc_bar2_size_and_offset(pcie, &rc_bar2_size,
1219 tmp = lower_32_bits(rc_bar2_offset);
1220 u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size),
1221 PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK);
1222 writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
1223 writel(upper_32_bits(rc_bar2_offset),
1224 base + PCIE_MISC_RC_BAR2_CONFIG_HI);
1226 tmp = readl(base + PCIE_MISC_UBUS_BAR2_CONFIG_REMAP);
1227 u32p_replace_bits(&tmp, 1, PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_ENABLE_MASK);
1228 writel(tmp, base + PCIE_MISC_UBUS_BAR2_CONFIG_REMAP);
1229 tmp = readl(base + PCIE_MISC_MISC_CTRL);
1231 for (memc = 0; memc < pcie->num_memc; memc++) {
1232 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15;
1235 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(0));
1237 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(1));
1239 u32p_replace_bits(&tmp, scb_size_val, SCB_SIZE_MASK(2));
1242 writel(tmp, base + PCIE_MISC_MISC_CTRL);
1244 if (pcie->type == BCM2712) {
1245 /* Suppress AXI error responses and return 1s for read failures */
1246 tmp = readl(base + PCIE_MISC_UBUS_CTRL);
1247 u32p_replace_bits(&tmp, 1, PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK);
1248 u32p_replace_bits(&tmp, 1, PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_DECERR_DIS_MASK);
1249 writel(tmp, base + PCIE_MISC_UBUS_CTRL);
1250 writel(0xffffffff, base + PCIE_MISC_AXI_READ_ERROR_DATA);
1253 * Adjust timeouts. The UBUS timeout also affects CRS
1254 * completion retries, as the request will get terminated if
1255 * either timeout expires, so both have to be a large value
1256 * (in clocks of 750MHz).
1257 * Set UBUS timeout to 250ms, then set RC config retry timeout
1260 * Setting CRSVis=1 will stop the core from blocking on a CRS
1261 * response, but does require the device to be well-behaved...
1263 writel(0xB2D0000, base + PCIE_MISC_UBUS_TIMEOUT);
1264 writel(0xABA0000, base + PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT);
1268 * We ideally want the MSI target address to be located in the 32bit
1269 * addressable memory area. Some devices might depend on it. This is
1270 * possible either when the inbound window is located above the lower
1271 * 4GB or when the inbound area is smaller than 4GB (taking into
1272 * account the rounding-up we're forced to perform).
1274 if (rc_bar2_offset >= SZ_4G || (rc_bar2_size + rc_bar2_offset) < SZ_4G)
1275 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB;
1277 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB;
1279 if (!pcie->rc_mode(pcie)) {
1280 dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n");
1284 /* disable the PCIe->GISB memory window (RC_BAR1) */
1285 tmp = readl(base + PCIE_MISC_RC_BAR1_CONFIG_LO);
1286 tmp &= ~PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK;
1287 writel(tmp, base + PCIE_MISC_RC_BAR1_CONFIG_LO);
1289 /* disable the PCIe->SCB memory window (RC_BAR3) */
1290 tmp = readl(base + PCIE_MISC_RC_BAR3_CONFIG_LO);
1291 tmp &= ~PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK;
1292 writel(tmp, base + PCIE_MISC_RC_BAR3_CONFIG_LO);
1294 /* Don't advertise L0s capability if 'aspm-no-l0s' */
1295 aspm_support = PCIE_LINK_STATE_L1;
1296 if (!of_property_read_bool(pcie->np, "aspm-no-l0s"))
1297 aspm_support |= PCIE_LINK_STATE_L0S;
1298 tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
1299 u32p_replace_bits(&tmp, aspm_support,
1300 PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK);
1301 writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY);
1303 /* program additional inbound windows (RC_BAR4..RC_BAR10) */
1304 count = (pcie->type == BCM2712) ? 7 : 0;
1305 for (i = 0; i < count; i++) {
1306 u64 bar_cpu, bar_size, bar_pci;
1308 ret = brcm_pcie_get_rc_bar_n(pcie, 1 + i, &bar_cpu, &bar_size,
1313 tmp = lower_32_bits(bar_pci);
1314 u32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(bar_size),
1315 PCIE_MISC_RC_BAR_CONFIG_LO_SIZE_MASK);
1316 writel(tmp, base + PCIE_MISC_RC_BAR4_CONFIG_LO + i * 8);
1317 writel(upper_32_bits(bar_pci),
1318 base + PCIE_MISC_RC_BAR4_CONFIG_HI + i * 8);
1320 tmp = upper_32_bits(bar_cpu) &
1321 PCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK;
1323 base + PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_HI + i * 8);
1324 tmp = lower_32_bits(bar_cpu) &
1325 PCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK;
1326 writel(tmp | PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE,
1327 base + PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_LO + i * 8);
1331 dev_info(pcie->dev, "Forcing gen %d\n", pcie->gen);
1332 brcm_pcie_set_gen(pcie, pcie->gen);
1336 * For config space accesses on the RC, show the right class for
1337 * a PCIe-PCIe bridge (the default setting is to be EP mode).
1339 tmp = readl(base + PCIE_RC_CFG_PRIV1_ID_VAL3);
1340 u32p_replace_bits(&tmp, 0x060400,
1341 PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK);
1342 writel(tmp, base + PCIE_RC_CFG_PRIV1_ID_VAL3);
1344 bridge = pci_host_bridge_from_priv(pcie);
1345 resource_list_for_each_entry(entry, &bridge->windows) {
1346 struct resource *res = entry->res;
1348 if (resource_type(res) != IORESOURCE_MEM)
1351 if (num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) {
1352 dev_err(pcie->dev, "too many outbound wins\n");
1356 if (is_bmips(pcie)) {
1357 u64 start = res->start;
1358 unsigned int j, nwins = resource_size(res) / SZ_128M;
1360 /* bmips PCIe outbound windows have a 128MB max size */
1361 if (nwins > BRCM_NUM_PCIE_OUT_WINS)
1362 nwins = BRCM_NUM_PCIE_OUT_WINS;
1363 for (j = 0; j < nwins; j++, start += SZ_128M)
1364 brcm_pcie_set_outbound_win(pcie, j, start,
1365 start - entry->offset,
1369 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start,
1370 res->start - entry->offset,
1371 resource_size(res));
1375 /* PCIe->SCB endian mode for BAR */
1376 tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
1377 u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN,
1378 PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK);
1379 writel(tmp, base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
1384 static int brcm_pcie_start_link(struct brcm_pcie *pcie)
1386 struct device *dev = pcie->dev;
1387 void __iomem *base = pcie->base;
1388 u16 nlw, cls, lnksta;
1389 bool ssc_good = false;
1393 /* Unassert the fundamental reset */
1394 if (pcie->tperst_clk_ms) {
1396 * Increase Tperst_clk time by forcing PERST# output low while
1397 * the internal reset is released, so the PLL generates stable
1398 * refclk output further in advance of PERST# deassertion.
1400 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1401 u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_PERST_ASSERT_MASK);
1402 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1404 pcie->perst_set(pcie, 0);
1405 msleep(pcie->tperst_clk_ms);
1407 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1408 u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_PERST_ASSERT_MASK);
1409 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1411 pcie->perst_set(pcie, 0);
1415 * Wait for 100ms after PERST# deassertion; see PCIe CEM specification
1416 * sections 2.2, PCIe r5.0, 6.6.1.
1421 * Give the RC/EP even more time to wake up, before trying to
1422 * configure RC. Intermittently check status for link-up, up to a
1425 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5)
1428 if (!brcm_pcie_link_up(pcie)) {
1429 dev_err(dev, "link down\n");
1434 brcm_pcie_set_gen(pcie, pcie->gen);
1437 ret = brcm_pcie_set_ssc(pcie);
1441 dev_err(dev, "failed attempt to enter ssc mode\n");
1445 lnksta = readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
1446 cls = FIELD_GET(PCI_EXP_LNKSTA_CLS, lnksta);
1447 nlw = FIELD_GET(PCI_EXP_LNKSTA_NLW, lnksta);
1448 dev_info(dev, "link up, %s x%u %s\n",
1449 pci_speed_string(pcie_link_speed[cls]), nlw,
1450 ssc_good ? "(SSC)" : "(!SSC)");
1455 static const char * const supplies[] = {
1461 static void *alloc_subdev_regulators(struct device *dev)
1463 const size_t size = sizeof(struct subdev_regulators) +
1464 sizeof(struct regulator_bulk_data) * ARRAY_SIZE(supplies);
1465 struct subdev_regulators *sr;
1468 sr = devm_kzalloc(dev, size, GFP_KERNEL);
1470 sr->num_supplies = ARRAY_SIZE(supplies);
1471 for (i = 0; i < ARRAY_SIZE(supplies); i++)
1472 sr->supplies[i].supply = supplies[i];
1478 static int brcm_pcie_add_bus(struct pci_bus *bus)
1480 struct brcm_pcie *pcie = bus->sysdata;
1481 struct device *dev = &bus->dev;
1482 struct subdev_regulators *sr;
1485 if (!bus->parent || !pci_is_root_bus(bus->parent))
1489 sr = alloc_subdev_regulators(dev);
1491 dev_info(dev, "Can't allocate regulators for downstream device\n");
1497 ret = regulator_bulk_get(dev, sr->num_supplies, sr->supplies);
1499 dev_info(dev, "No regulators for downstream device\n");
1503 ret = regulator_bulk_enable(sr->num_supplies, sr->supplies);
1505 dev_err(dev, "Can't enable regulators for downstream device\n");
1506 regulator_bulk_free(sr->num_supplies, sr->supplies);
1512 brcm_pcie_start_link(pcie);
1516 static void brcm_pcie_remove_bus(struct pci_bus *bus)
1518 struct brcm_pcie *pcie = bus->sysdata;
1519 struct subdev_regulators *sr = pcie->sr;
1520 struct device *dev = &bus->dev;
1525 if (regulator_bulk_disable(sr->num_supplies, sr->supplies))
1526 dev_err(dev, "Failed to disable regulators for downstream device\n");
1527 regulator_bulk_free(sr->num_supplies, sr->supplies);
1531 /* L23 is a low-power PCIe link state */
1532 static void brcm_pcie_enter_l23(struct brcm_pcie *pcie)
1534 void __iomem *base = pcie->base;
1538 /* Assert request for L23 */
1539 tmp = readl(base + PCIE_MISC_PCIE_CTRL);
1540 u32p_replace_bits(&tmp, 1, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK);
1541 writel(tmp, base + PCIE_MISC_PCIE_CTRL);
1543 /* Wait up to 36 msec for L23 */
1544 tmp = readl(base + PCIE_MISC_PCIE_STATUS);
1545 l23 = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK, tmp);
1546 for (i = 0; i < 15 && !l23; i++) {
1547 usleep_range(2000, 2400);
1548 tmp = readl(base + PCIE_MISC_PCIE_STATUS);
1549 l23 = FIELD_GET(PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK,
1554 dev_err(pcie->dev, "failed to enter low-power link state\n");
1557 static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start)
1560 static const u32 shifts[PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS] = {
1561 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_SHIFT,
1562 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_SHIFT,
1563 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_SHIFT,};
1564 static const u32 masks[PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS] = {
1565 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_PWRDN_MASK,
1566 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_RESET_MASK,
1567 PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_DIG_RESET_MASK,};
1568 const int beg = start ? 0 : PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS - 1;
1569 const int end = start ? PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS : -1;
1570 u32 tmp, combined_mask = 0;
1572 void __iomem *base = pcie->base;
1575 for (i = beg; i != end; start ? i++ : i--) {
1576 val = start ? BIT_MASK(shifts[i]) : 0;
1577 tmp = readl(base + PCIE_DVT_PMU_PCIE_PHY_CTRL);
1578 tmp = (tmp & ~masks[i]) | (val & masks[i]);
1579 writel(tmp, base + PCIE_DVT_PMU_PCIE_PHY_CTRL);
1580 usleep_range(50, 200);
1581 combined_mask |= masks[i];
1584 tmp = readl(base + PCIE_DVT_PMU_PCIE_PHY_CTRL);
1585 val = start ? combined_mask : 0;
1587 ret = (tmp & combined_mask) == val ? 0 : -EIO;
1589 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop"));
1597 static inline int brcm_phy_start(struct brcm_pcie *pcie)
1599 return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0;
1602 static inline int brcm_phy_stop(struct brcm_pcie *pcie)
1604 return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0;
1607 static void brcm_pcie_turn_off(struct brcm_pcie *pcie)
1609 void __iomem *base = pcie->base;
1612 if (brcm_pcie_link_up(pcie))
1613 brcm_pcie_enter_l23(pcie);
1614 /* Assert fundamental reset */
1615 pcie->perst_set(pcie, 1);
1617 /* Deassert request for L23 in case it was asserted */
1618 tmp = readl(base + PCIE_MISC_PCIE_CTRL);
1619 u32p_replace_bits(&tmp, 0, PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK);
1620 writel(tmp, base + PCIE_MISC_PCIE_CTRL);
1622 /* Turn off SerDes */
1623 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1624 u32p_replace_bits(&tmp, 1, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
1625 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1628 * Shutting down this bridge on pcie1 means accesses to rescal block
1629 * will hang the chip if another RC wants to assert/deassert rescal.
1631 if (pcie->type == BCM2712)
1633 /* Shutdown PCIe bridge */
1634 pcie->bridge_sw_init_set(pcie, 1);
1637 static int pci_dev_may_wakeup(struct pci_dev *dev, void *data)
1641 if (device_may_wakeup(&dev->dev)) {
1643 dev_info(&dev->dev, "Possible wake-up device; regulators will not be disabled\n");
1648 static int brcm_pcie_suspend_noirq(struct device *dev)
1650 struct brcm_pcie *pcie = dev_get_drvdata(dev);
1651 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1654 brcm_pcie_turn_off(pcie);
1656 * If brcm_phy_stop() returns an error, just dev_err(). If we
1657 * return the error it will cause the suspend to fail and this is a
1658 * forgivable offense that will probably be erased on resume.
1660 if (brcm_phy_stop(pcie))
1661 dev_err(dev, "Could not stop phy for suspend\n");
1663 ret = reset_control_assert(pcie->rescal);
1665 dev_err(dev, "Could not assert rescal reset\n");
1671 * Now turn off the regulators, but if at least one
1672 * downstream device is enabled as a wake-up source, do not
1673 * turn off regulators.
1675 pcie->ep_wakeup_capable = false;
1676 pci_walk_bus(bridge->bus, pci_dev_may_wakeup,
1677 &pcie->ep_wakeup_capable);
1678 if (!pcie->ep_wakeup_capable) {
1679 ret = regulator_bulk_disable(pcie->sr->num_supplies,
1680 pcie->sr->supplies);
1682 dev_err(dev, "Could not turn off regulators\n");
1683 reset_control_reset(pcie->rescal);
1688 clk_disable_unprepare(pcie->clk);
1693 static int brcm_pcie_resume_noirq(struct device *dev)
1695 struct brcm_pcie *pcie = dev_get_drvdata(dev);
1701 ret = clk_prepare_enable(pcie->clk);
1705 ret = reset_control_reset(pcie->rescal);
1707 goto err_disable_clk;
1709 ret = brcm_phy_start(pcie);
1713 /* Take bridge out of reset so we can access the SERDES reg */
1714 pcie->bridge_sw_init_set(pcie, 0);
1716 /* SERDES_IDDQ = 0 */
1717 tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1718 u32p_replace_bits(&tmp, 0, PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK);
1719 writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG);
1721 /* wait for serdes to be stable */
1724 ret = brcm_pcie_setup(pcie);
1729 if (pcie->ep_wakeup_capable) {
1731 * We are resuming from a suspend. In the suspend we
1732 * did not disable the power supplies, so there is
1733 * no need to enable them (and falsely increase their
1736 pcie->ep_wakeup_capable = false;
1738 ret = regulator_bulk_enable(pcie->sr->num_supplies,
1739 pcie->sr->supplies);
1741 dev_err(dev, "Could not turn on regulators\n");
1747 ret = brcm_pcie_start_link(pcie);
1752 brcm_msi_set_regs(pcie->msi);
1758 regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies);
1760 reset_control_assert(pcie->rescal);
1762 clk_disable_unprepare(pcie->clk);
1766 static void __brcm_pcie_remove(struct brcm_pcie *pcie)
1768 brcm_msi_remove(pcie);
1769 brcm_pcie_turn_off(pcie);
1770 if (brcm_phy_stop(pcie))
1771 dev_err(pcie->dev, "Could not stop phy\n");
1772 if (reset_control_assert(pcie->rescal))
1773 dev_err(pcie->dev, "Could not assert rescal reset\n");
1774 clk_disable_unprepare(pcie->clk);
1777 static void brcm_pcie_remove(struct platform_device *pdev)
1779 struct brcm_pcie *pcie = platform_get_drvdata(pdev);
1780 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1782 pci_stop_root_bus(bridge->bus);
1783 pci_remove_root_bus(bridge->bus);
1784 __brcm_pcie_remove(pcie);
1787 static const int pcie_offsets[] = {
1788 [RGR1_SW_INIT_1] = 0x9210,
1789 [EXT_CFG_INDEX] = 0x9000,
1790 [EXT_CFG_DATA] = 0x9004,
1791 [PCIE_HARD_DEBUG] = 0x4204,
1792 [INTR2_CPU] = 0x4300,
1795 static const int pcie_offsets_bmips_7425[] = {
1796 [RGR1_SW_INIT_1] = 0x8010,
1797 [EXT_CFG_INDEX] = 0x8300,
1798 [EXT_CFG_DATA] = 0x8304,
1799 [PCIE_HARD_DEBUG] = 0x4204,
1800 [INTR2_CPU] = 0x4300,
1803 static const struct pcie_cfg_data generic_cfg = {
1804 .offsets = pcie_offsets,
1806 .perst_set = brcm_pcie_perst_set_generic,
1807 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
1808 .rc_mode = brcm_pcie_rc_mode_generic,
1811 static const struct pcie_cfg_data bcm7425_cfg = {
1812 .offsets = pcie_offsets_bmips_7425,
1814 .perst_set = brcm_pcie_perst_set_generic,
1815 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
1816 .rc_mode = brcm_pcie_rc_mode_generic,
1819 static const struct pcie_cfg_data bcm7435_cfg = {
1820 .offsets = pcie_offsets,
1822 .perst_set = brcm_pcie_perst_set_generic,
1823 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
1826 static const struct pcie_cfg_data bcm4908_cfg = {
1827 .offsets = pcie_offsets,
1829 .perst_set = brcm_pcie_perst_set_4908,
1830 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
1831 .rc_mode = brcm_pcie_rc_mode_generic,
1834 static const int pcie_offset_bcm7278[] = {
1835 [RGR1_SW_INIT_1] = 0xc010,
1836 [EXT_CFG_INDEX] = 0x9000,
1837 [EXT_CFG_DATA] = 0x9004,
1838 [PCIE_HARD_DEBUG] = 0x4204,
1839 [INTR2_CPU] = 0x4300,
1842 static const struct pcie_cfg_data bcm7278_cfg = {
1843 .offsets = pcie_offset_bcm7278,
1845 .perst_set = brcm_pcie_perst_set_7278,
1846 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278,
1847 .rc_mode = brcm_pcie_rc_mode_generic,
1850 static const struct pcie_cfg_data bcm2711_cfg = {
1851 .offsets = pcie_offsets,
1853 .perst_set = brcm_pcie_perst_set_generic,
1854 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
1855 .rc_mode = brcm_pcie_rc_mode_generic,
1858 static const int pcie_offsets_bcm2712[] = {
1859 [EXT_CFG_INDEX] = 0x9000,
1860 [EXT_CFG_DATA] = 0x9004,
1861 [PCIE_HARD_DEBUG] = 0x4304,
1862 [INTR2_CPU] = 0x4400,
1865 static const struct pcie_cfg_data bcm2712_cfg = {
1866 .offsets = pcie_offsets_bcm2712,
1868 .perst_set = brcm_pcie_perst_set_2712,
1869 .bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_2712,
1870 .rc_mode = brcm_pcie_rc_mode_2712,
1873 static const struct of_device_id brcm_pcie_match[] = {
1874 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1875 { .compatible = "brcm,bcm2712-pcie", .data = &bcm2712_cfg },
1876 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
1877 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1878 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1879 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
1880 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1881 { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
1882 { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
1886 static struct pci_ops brcm_pcie_ops = {
1887 .map_bus = brcm_pcie_map_bus,
1888 .read = pci_generic_config_read,
1889 .write = pci_generic_config_write,
1890 .add_bus = brcm_pcie_add_bus,
1891 .remove_bus = brcm_pcie_remove_bus,
1894 static struct pci_ops brcm7425_pcie_ops = {
1895 .map_bus = brcm7425_pcie_map_bus,
1896 .read = pci_generic_config_read32,
1897 .write = pci_generic_config_write32,
1898 .add_bus = brcm_pcie_add_bus,
1899 .remove_bus = brcm_pcie_remove_bus,
1902 static int brcm_pcie_probe(struct platform_device *pdev)
1904 struct device_node *np = pdev->dev.of_node, *msi_np;
1905 struct pci_host_bridge *bridge;
1906 const struct pcie_cfg_data *data;
1907 struct brcm_pcie *pcie;
1910 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
1914 data = of_device_get_match_data(&pdev->dev);
1916 dev_err(&pdev->dev, "failed to look up compatible string\n");
1920 pcie = pci_host_bridge_priv(bridge);
1921 pcie->dev = &pdev->dev;
1923 pcie->reg_offsets = data->offsets;
1924 pcie->type = data->type;
1925 pcie->perst_set = data->perst_set;
1926 pcie->bridge_sw_init_set = data->bridge_sw_init_set;
1927 pcie->rc_mode = data->rc_mode;
1929 pcie->base = devm_platform_ioremap_resource(pdev, 0);
1930 if (IS_ERR(pcie->base))
1931 return PTR_ERR(pcie->base);
1933 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie");
1934 if (IS_ERR(pcie->clk))
1935 return PTR_ERR(pcie->clk);
1937 ret = of_pci_get_max_link_speed(np);
1938 pcie->gen = (ret < 0) ? 0 : ret;
1940 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc");
1941 pcie->l1ss = of_property_read_bool(np, "brcm,enable-l1ss");
1942 pcie->rcb_mps_mode = of_property_read_bool(np, "brcm,enable-mps-rcb");
1943 of_property_read_u32(np, "brcm,tperst-clk-ms", &pcie->tperst_clk_ms);
1945 ret = clk_prepare_enable(pcie->clk);
1947 dev_err(&pdev->dev, "could not enable clock\n");
1950 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal");
1951 if (IS_ERR(pcie->rescal)) {
1952 clk_disable_unprepare(pcie->clk);
1953 return PTR_ERR(pcie->rescal);
1955 pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst");
1956 if (IS_ERR(pcie->perst_reset)) {
1957 clk_disable_unprepare(pcie->clk);
1958 return PTR_ERR(pcie->perst_reset);
1960 pcie->bridge_reset =
1961 devm_reset_control_get_optional_exclusive(&pdev->dev, "bridge");
1962 if (IS_ERR(pcie->bridge_reset)) {
1963 clk_disable_unprepare(pcie->clk);
1964 return PTR_ERR(pcie->bridge_reset);
1967 ret = reset_control_deassert(pcie->rescal);
1969 dev_err(&pdev->dev, "failed to deassert 'rescal'\n");
1971 ret = brcm_phy_start(pcie);
1973 reset_control_assert(pcie->rescal);
1974 clk_disable_unprepare(pcie->clk);
1978 ret = brcm_pcie_setup(pcie);
1982 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION);
1983 if (pcie->type == BCM4908 && pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) {
1984 dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n");
1989 msi_np = of_parse_phandle(pcie->np, "msi-parent", 0);
1990 if (pci_msi_enabled() && msi_np == pcie->np) {
1991 ret = brcm_pcie_enable_msi(pcie);
1993 dev_err(pcie->dev, "probe of internal MSI failed");
1996 } else if (pci_msi_enabled() && msi_np != pcie->np) {
1997 /* Use RC_BAR1 for MIP access */
2001 if (of_property_read_u64(msi_np, "brcm,msi-pci-addr", &msi_pci_addr)) {
2002 dev_err(pcie->dev, "Unable to find MSI PCI address\n");
2007 if (of_property_read_u64(msi_np, "reg", &msi_phys_addr)) {
2008 dev_err(pcie->dev, "Unable to find MSI physical address\n");
2013 writel(lower_32_bits(msi_pci_addr) | brcm_pcie_encode_ibar_size(0x1000),
2014 pcie->base + PCIE_MISC_RC_BAR1_CONFIG_LO);
2015 writel(upper_32_bits(msi_pci_addr),
2016 pcie->base + PCIE_MISC_RC_BAR1_CONFIG_HI);
2018 writel(lower_32_bits(msi_phys_addr) |
2019 PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_ACCESS_ENABLE_MASK,
2020 pcie->base + PCIE_MISC_UBUS_BAR1_CONFIG_REMAP);
2021 writel(upper_32_bits(msi_phys_addr),
2022 pcie->base + PCIE_MISC_UBUS_BAR1_CONFIG_REMAP_HI);
2025 bridge->ops = pcie->type == BCM7425 ? &brcm7425_pcie_ops : &brcm_pcie_ops;
2026 bridge->sysdata = pcie;
2028 platform_set_drvdata(pdev, pcie);
2030 ret = pci_host_probe(bridge);
2031 if (!ret && !brcm_pcie_link_up(pcie))
2035 brcm_pcie_remove(pdev);
2039 brcm_pcie_config_clkreq(pcie);
2044 __brcm_pcie_remove(pcie);
2048 MODULE_DEVICE_TABLE(of, brcm_pcie_match);
2050 static const struct dev_pm_ops brcm_pcie_pm_ops = {
2051 .suspend_noirq = brcm_pcie_suspend_noirq,
2052 .resume_noirq = brcm_pcie_resume_noirq,
2055 static struct platform_driver brcm_pcie_driver = {
2056 .probe = brcm_pcie_probe,
2057 .remove_new = brcm_pcie_remove,
2059 .name = "brcm-pcie",
2060 .of_match_table = brcm_pcie_match,
2061 .pm = &brcm_pcie_pm_ops,
2064 module_platform_driver(brcm_pcie_driver);
2066 MODULE_LICENSE("GPL");
2067 MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");
2068 MODULE_AUTHOR("Broadcom");