1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm PCIe root complex driver
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 * Copyright 2015 Linaro Limited.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
11 #include <linux/clk.h>
12 #include <linux/crc8.h>
13 #include <linux/debugfs.h>
14 #include <linux/delay.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/interconnect.h>
17 #include <linux/interrupt.h>
19 #include <linux/iopoll.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
23 #include <linux/of_gpio.h>
24 #include <linux/pci.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/platform_device.h>
27 #include <linux/phy/pcie.h>
28 #include <linux/phy/phy.h>
29 #include <linux/regulator/consumer.h>
30 #include <linux/reset.h>
31 #include <linux/slab.h>
32 #include <linux/types.h>
34 #include "../../pci.h"
35 #include "pcie-designware.h"
38 #define PARF_SYS_CTRL 0x00
39 #define PARF_PM_CTRL 0x20
40 #define PARF_PCS_DEEMPH 0x34
41 #define PARF_PCS_SWING 0x38
42 #define PARF_PHY_CTRL 0x40
43 #define PARF_PHY_REFCLK 0x4c
44 #define PARF_CONFIG_BITS 0x50
45 #define PARF_DBI_BASE_ADDR 0x168
46 #define PARF_SLV_ADDR_SPACE_SIZE_2_3_3 0x16c /* Register offset specific to IP ver 2.3.3 */
47 #define PARF_MHI_CLOCK_RESET_CTRL 0x174
48 #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178
49 #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8
50 #define PARF_Q2A_FLUSH 0x1ac
51 #define PARF_LTSSM 0x1b0
52 #define PARF_SID_OFFSET 0x234
53 #define PARF_BDF_TRANSLATE_CFG 0x24c
54 #define PARF_SLV_ADDR_SPACE_SIZE 0x358
55 #define PARF_DEVICE_TYPE 0x1000
56 #define PARF_BDF_TO_SID_TABLE_N 0x2000
59 #define ELBI_SYS_CTRL 0x04
62 #define AXI_MSTR_RESP_COMP_CTRL0 0x818
63 #define AXI_MSTR_RESP_COMP_CTRL1 0x81c
66 #define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04
67 #define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c
68 #define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10
69 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84
70 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88
72 /* PARF_SYS_CTRL register fields */
73 #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29)
74 #define MST_WAKEUP_EN BIT(13)
75 #define SLV_WAKEUP_EN BIT(12)
76 #define MSTR_ACLK_CGC_DIS BIT(10)
77 #define SLV_ACLK_CGC_DIS BIT(9)
78 #define CORE_CLK_CGC_DIS BIT(6)
79 #define AUX_PWR_DET BIT(4)
80 #define L23_CLK_RMV_DIS BIT(2)
81 #define L1_CLK_RMV_DIS BIT(1)
83 /* PARF_PM_CTRL register fields */
84 #define REQ_NOT_ENTR_L1 BIT(5)
86 /* PARF_PCS_DEEMPH register fields */
87 #define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, 16), x)
88 #define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) FIELD_PREP(GENMASK(13, 8), x)
89 #define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) FIELD_PREP(GENMASK(5, 0), x)
91 /* PARF_PCS_SWING register fields */
92 #define PCS_SWING_TX_SWING_FULL(x) FIELD_PREP(GENMASK(14, 8), x)
93 #define PCS_SWING_TX_SWING_LOW(x) FIELD_PREP(GENMASK(6, 0), x)
95 /* PARF_PHY_CTRL register fields */
96 #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
97 #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) FIELD_PREP(PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, x)
98 #define PHY_TEST_PWR_DOWN BIT(0)
100 /* PARF_PHY_REFCLK register fields */
101 #define PHY_REFCLK_SSP_EN BIT(16)
102 #define PHY_REFCLK_USE_PAD BIT(12)
104 /* PARF_CONFIG_BITS register fields */
105 #define PHY_RX0_EQ(x) FIELD_PREP(GENMASK(26, 24), x)
107 /* PARF_SLV_ADDR_SPACE_SIZE register value */
108 #define SLV_ADDR_SPACE_SZ 0x10000000
110 /* PARF_MHI_CLOCK_RESET_CTRL register fields */
111 #define AHB_CLK_EN BIT(0)
112 #define MSTR_AXI_CLK_EN BIT(1)
113 #define BYPASS BIT(4)
115 /* PARF_AXI_MSTR_WR_ADDR_HALT register fields */
118 /* PARF_LTSSM register fields */
119 #define LTSSM_EN BIT(8)
121 /* PARF_DEVICE_TYPE register fields */
122 #define DEVICE_TYPE_RC 0x4
124 /* ELBI_SYS_CTRL register fields */
125 #define ELBI_SYS_CTRL_LT_ENABLE BIT(0)
127 /* AXI_MSTR_RESP_COMP_CTRL0 register fields */
128 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4
129 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5
131 /* AXI_MSTR_RESP_COMP_CTRL1 register fields */
132 #define CFG_BRIDGE_SB_INIT BIT(0)
134 /* PCI_EXP_SLTCAP register fields */
135 #define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, 250)
136 #define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, 1)
137 #define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \
138 PCI_EXP_SLTCAP_PCP | \
139 PCI_EXP_SLTCAP_MRLSP | \
140 PCI_EXP_SLTCAP_AIP | \
141 PCI_EXP_SLTCAP_PIP | \
142 PCI_EXP_SLTCAP_HPS | \
143 PCI_EXP_SLTCAP_EIP | \
144 PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
145 PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
147 #define PERST_DELAY_US 1000
149 #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0))
151 #define QCOM_PCIE_1_0_0_MAX_CLOCKS 4
152 struct qcom_pcie_resources_1_0_0 {
153 struct clk_bulk_data clks[QCOM_PCIE_1_0_0_MAX_CLOCKS];
154 struct reset_control *core;
155 struct regulator *vdda;
158 #define QCOM_PCIE_2_1_0_MAX_CLOCKS 5
159 #define QCOM_PCIE_2_1_0_MAX_RESETS 6
160 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
161 struct qcom_pcie_resources_2_1_0 {
162 struct clk_bulk_data clks[QCOM_PCIE_2_1_0_MAX_CLOCKS];
163 struct reset_control_bulk_data resets[QCOM_PCIE_2_1_0_MAX_RESETS];
165 struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
168 #define QCOM_PCIE_2_3_2_MAX_CLOCKS 4
169 #define QCOM_PCIE_2_3_2_MAX_SUPPLY 2
170 struct qcom_pcie_resources_2_3_2 {
171 struct clk_bulk_data clks[QCOM_PCIE_2_3_2_MAX_CLOCKS];
172 struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY];
175 #define QCOM_PCIE_2_3_3_MAX_CLOCKS 5
176 #define QCOM_PCIE_2_3_3_MAX_RESETS 7
177 struct qcom_pcie_resources_2_3_3 {
178 struct clk_bulk_data clks[QCOM_PCIE_2_3_3_MAX_CLOCKS];
179 struct reset_control_bulk_data rst[QCOM_PCIE_2_3_3_MAX_RESETS];
182 #define QCOM_PCIE_2_4_0_MAX_CLOCKS 4
183 #define QCOM_PCIE_2_4_0_MAX_RESETS 12
184 struct qcom_pcie_resources_2_4_0 {
185 struct clk_bulk_data clks[QCOM_PCIE_2_4_0_MAX_CLOCKS];
187 struct reset_control_bulk_data resets[QCOM_PCIE_2_4_0_MAX_RESETS];
191 #define QCOM_PCIE_2_7_0_MAX_CLOCKS 15
192 #define QCOM_PCIE_2_7_0_MAX_SUPPLIES 2
193 struct qcom_pcie_resources_2_7_0 {
194 struct clk_bulk_data clks[QCOM_PCIE_2_7_0_MAX_CLOCKS];
196 struct regulator_bulk_data supplies[QCOM_PCIE_2_7_0_MAX_SUPPLIES];
197 struct reset_control *rst;
200 #define QCOM_PCIE_2_9_0_MAX_CLOCKS 5
201 struct qcom_pcie_resources_2_9_0 {
202 struct clk_bulk_data clks[QCOM_PCIE_2_9_0_MAX_CLOCKS];
203 struct reset_control *rst;
206 union qcom_pcie_resources {
207 struct qcom_pcie_resources_1_0_0 v1_0_0;
208 struct qcom_pcie_resources_2_1_0 v2_1_0;
209 struct qcom_pcie_resources_2_3_2 v2_3_2;
210 struct qcom_pcie_resources_2_3_3 v2_3_3;
211 struct qcom_pcie_resources_2_4_0 v2_4_0;
212 struct qcom_pcie_resources_2_7_0 v2_7_0;
213 struct qcom_pcie_resources_2_9_0 v2_9_0;
218 struct qcom_pcie_ops {
219 int (*get_resources)(struct qcom_pcie *pcie);
220 int (*init)(struct qcom_pcie *pcie);
221 int (*post_init)(struct qcom_pcie *pcie);
222 void (*deinit)(struct qcom_pcie *pcie);
223 void (*ltssm_enable)(struct qcom_pcie *pcie);
224 int (*config_sid)(struct qcom_pcie *pcie);
227 struct qcom_pcie_cfg {
228 const struct qcom_pcie_ops *ops;
233 void __iomem *parf; /* DT parf */
234 void __iomem *elbi; /* DT elbi */
236 union qcom_pcie_resources res;
238 struct gpio_desc *reset;
239 struct icc_path *icc_mem;
240 const struct qcom_pcie_cfg *cfg;
241 struct dentry *debugfs;
245 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
247 static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
249 gpiod_set_value_cansleep(pcie->reset, 1);
250 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
253 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
255 /* Ensure that PERST has been asserted for at least 100 ms */
257 gpiod_set_value_cansleep(pcie->reset, 0);
258 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
261 static int qcom_pcie_start_link(struct dw_pcie *pci)
263 struct qcom_pcie *pcie = to_qcom_pcie(pci);
265 /* Enable Link Training state machine */
266 if (pcie->cfg->ops->ltssm_enable)
267 pcie->cfg->ops->ltssm_enable(pcie);
272 static void qcom_pcie_clear_hpc(struct dw_pcie *pci)
274 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
277 dw_pcie_dbi_ro_wr_en(pci);
279 val = readl(pci->dbi_base + offset + PCI_EXP_SLTCAP);
280 val &= ~PCI_EXP_SLTCAP_HPC;
281 writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP);
283 dw_pcie_dbi_ro_wr_dis(pci);
286 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
290 /* enable link training */
291 val = readl(pcie->elbi + ELBI_SYS_CTRL);
292 val |= ELBI_SYS_CTRL_LT_ENABLE;
293 writel(val, pcie->elbi + ELBI_SYS_CTRL);
296 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
298 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
299 struct dw_pcie *pci = pcie->pci;
300 struct device *dev = pci->dev;
301 bool is_apq = of_device_is_compatible(dev->of_node, "qcom,pcie-apq8064");
304 res->supplies[0].supply = "vdda";
305 res->supplies[1].supply = "vdda_phy";
306 res->supplies[2].supply = "vdda_refclk";
307 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
312 res->clks[0].id = "iface";
313 res->clks[1].id = "core";
314 res->clks[2].id = "phy";
315 res->clks[3].id = "aux";
316 res->clks[4].id = "ref";
318 /* iface, core, phy are required */
319 ret = devm_clk_bulk_get(dev, 3, res->clks);
323 /* aux, ref are optional */
324 ret = devm_clk_bulk_get_optional(dev, 2, res->clks + 3);
328 res->resets[0].id = "pci";
329 res->resets[1].id = "axi";
330 res->resets[2].id = "ahb";
331 res->resets[3].id = "por";
332 res->resets[4].id = "phy";
333 res->resets[5].id = "ext";
335 /* ext is optional on APQ8016 */
336 res->num_resets = is_apq ? 5 : 6;
337 ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets);
344 static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
346 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
348 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
349 reset_control_bulk_assert(res->num_resets, res->resets);
351 writel(1, pcie->parf + PARF_PHY_CTRL);
353 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
356 static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
358 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
359 struct dw_pcie *pci = pcie->pci;
360 struct device *dev = pci->dev;
363 /* reset the PCIe interface as uboot can leave it undefined state */
364 ret = reset_control_bulk_assert(res->num_resets, res->resets);
366 dev_err(dev, "cannot assert resets\n");
370 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
372 dev_err(dev, "cannot enable regulators\n");
376 ret = reset_control_bulk_deassert(res->num_resets, res->resets);
378 dev_err(dev, "cannot deassert resets\n");
379 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
386 static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie)
388 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
389 struct dw_pcie *pci = pcie->pci;
390 struct device *dev = pci->dev;
391 struct device_node *node = dev->of_node;
395 /* enable PCIe clocks and resets */
396 val = readl(pcie->parf + PARF_PHY_CTRL);
397 val &= ~PHY_TEST_PWR_DOWN;
398 writel(val, pcie->parf + PARF_PHY_CTRL);
400 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
404 if (of_device_is_compatible(node, "qcom,pcie-ipq8064") ||
405 of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) {
406 writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
407 PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
408 PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
409 pcie->parf + PARF_PCS_DEEMPH);
410 writel(PCS_SWING_TX_SWING_FULL(120) |
411 PCS_SWING_TX_SWING_LOW(120),
412 pcie->parf + PARF_PCS_SWING);
413 writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS);
416 if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
417 /* set TX termination offset */
418 val = readl(pcie->parf + PARF_PHY_CTRL);
419 val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK;
420 val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7);
421 writel(val, pcie->parf + PARF_PHY_CTRL);
424 /* enable external reference clock */
425 val = readl(pcie->parf + PARF_PHY_REFCLK);
426 /* USE_PAD is required only for ipq806x */
427 if (!of_device_is_compatible(node, "qcom,pcie-apq8064"))
428 val &= ~PHY_REFCLK_USE_PAD;
429 val |= PHY_REFCLK_SSP_EN;
430 writel(val, pcie->parf + PARF_PHY_REFCLK);
432 /* wait for clock acquisition */
433 usleep_range(1000, 1500);
435 /* Set the Max TLP size to 2K, instead of using default of 4K */
436 writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
437 pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL0);
438 writel(CFG_BRIDGE_SB_INIT,
439 pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL1);
441 qcom_pcie_clear_hpc(pcie->pci);
446 static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie)
448 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
449 struct dw_pcie *pci = pcie->pci;
450 struct device *dev = pci->dev;
453 res->vdda = devm_regulator_get(dev, "vdda");
454 if (IS_ERR(res->vdda))
455 return PTR_ERR(res->vdda);
457 res->clks[0].id = "iface";
458 res->clks[1].id = "aux";
459 res->clks[2].id = "master_bus";
460 res->clks[3].id = "slave_bus";
462 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
466 res->core = devm_reset_control_get_exclusive(dev, "core");
467 return PTR_ERR_OR_ZERO(res->core);
470 static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie)
472 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
474 reset_control_assert(res->core);
475 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
476 regulator_disable(res->vdda);
479 static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie)
481 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
482 struct dw_pcie *pci = pcie->pci;
483 struct device *dev = pci->dev;
486 ret = reset_control_deassert(res->core);
488 dev_err(dev, "cannot deassert core reset\n");
492 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
494 dev_err(dev, "cannot prepare/enable clocks\n");
495 goto err_assert_reset;
498 ret = regulator_enable(res->vdda);
500 dev_err(dev, "cannot enable vdda regulator\n");
501 goto err_disable_clks;
507 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
509 reset_control_assert(res->core);
514 static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie)
516 /* change DBI base address */
517 writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
519 if (IS_ENABLED(CONFIG_PCI_MSI)) {
520 u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
523 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
526 qcom_pcie_clear_hpc(pcie->pci);
531 static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
535 /* enable link training */
536 val = readl(pcie->parf + PARF_LTSSM);
538 writel(val, pcie->parf + PARF_LTSSM);
541 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)
543 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
544 struct dw_pcie *pci = pcie->pci;
545 struct device *dev = pci->dev;
548 res->supplies[0].supply = "vdda";
549 res->supplies[1].supply = "vddpe-3v3";
550 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
555 res->clks[0].id = "aux";
556 res->clks[1].id = "cfg";
557 res->clks[2].id = "bus_master";
558 res->clks[3].id = "bus_slave";
560 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
567 static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
569 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
571 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
572 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
575 static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
577 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
578 struct dw_pcie *pci = pcie->pci;
579 struct device *dev = pci->dev;
582 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
584 dev_err(dev, "cannot enable regulators\n");
588 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
590 dev_err(dev, "cannot prepare/enable clocks\n");
591 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
598 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
602 /* enable PCIe clocks and resets */
603 val = readl(pcie->parf + PARF_PHY_CTRL);
604 val &= ~PHY_TEST_PWR_DOWN;
605 writel(val, pcie->parf + PARF_PHY_CTRL);
607 /* change DBI base address */
608 writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
610 /* MAC PHY_POWERDOWN MUX DISABLE */
611 val = readl(pcie->parf + PARF_SYS_CTRL);
612 val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN;
613 writel(val, pcie->parf + PARF_SYS_CTRL);
615 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
617 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
619 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
621 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
623 qcom_pcie_clear_hpc(pcie->pci);
628 static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
630 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
631 struct dw_pcie *pci = pcie->pci;
632 struct device *dev = pci->dev;
633 bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019");
636 res->clks[0].id = "aux";
637 res->clks[1].id = "master_bus";
638 res->clks[2].id = "slave_bus";
639 res->clks[3].id = "iface";
641 /* qcom,pcie-ipq4019 is defined without "iface" */
642 res->num_clks = is_ipq ? 3 : 4;
644 ret = devm_clk_bulk_get(dev, res->num_clks, res->clks);
648 res->resets[0].id = "axi_m";
649 res->resets[1].id = "axi_s";
650 res->resets[2].id = "axi_m_sticky";
651 res->resets[3].id = "pipe_sticky";
652 res->resets[4].id = "pwr";
653 res->resets[5].id = "ahb";
654 res->resets[6].id = "pipe";
655 res->resets[7].id = "axi_m_vmid";
656 res->resets[8].id = "axi_s_xpu";
657 res->resets[9].id = "parf";
658 res->resets[10].id = "phy";
659 res->resets[11].id = "phy_ahb";
661 res->num_resets = is_ipq ? 12 : 6;
663 ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets);
670 static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)
672 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
674 reset_control_bulk_assert(res->num_resets, res->resets);
675 clk_bulk_disable_unprepare(res->num_clks, res->clks);
678 static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
680 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
681 struct dw_pcie *pci = pcie->pci;
682 struct device *dev = pci->dev;
685 ret = reset_control_bulk_assert(res->num_resets, res->resets);
687 dev_err(dev, "cannot assert resets\n");
691 usleep_range(10000, 12000);
693 ret = reset_control_bulk_deassert(res->num_resets, res->resets);
695 dev_err(dev, "cannot deassert resets\n");
699 usleep_range(10000, 12000);
701 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
703 reset_control_bulk_assert(res->num_resets, res->resets);
710 static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)
712 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
713 struct dw_pcie *pci = pcie->pci;
714 struct device *dev = pci->dev;
717 res->clks[0].id = "iface";
718 res->clks[1].id = "axi_m";
719 res->clks[2].id = "axi_s";
720 res->clks[3].id = "ahb";
721 res->clks[4].id = "aux";
723 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
727 res->rst[0].id = "axi_m";
728 res->rst[1].id = "axi_s";
729 res->rst[2].id = "pipe";
730 res->rst[3].id = "axi_m_sticky";
731 res->rst[4].id = "sticky";
732 res->rst[5].id = "ahb";
733 res->rst[6].id = "sleep";
735 ret = devm_reset_control_bulk_get_exclusive(dev, ARRAY_SIZE(res->rst), res->rst);
742 static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)
744 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
746 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
749 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
751 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
752 struct dw_pcie *pci = pcie->pci;
753 struct device *dev = pci->dev;
756 ret = reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst);
758 dev_err(dev, "cannot assert resets\n");
762 usleep_range(2000, 2500);
764 ret = reset_control_bulk_deassert(ARRAY_SIZE(res->rst), res->rst);
766 dev_err(dev, "cannot deassert resets\n");
771 * Don't have a way to see if the reset has completed.
772 * Wait for some time.
774 usleep_range(2000, 2500);
776 ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
778 dev_err(dev, "cannot prepare/enable clocks\n");
779 goto err_assert_resets;
786 * Not checking for failure, will anyway return
787 * the original failure in 'ret'.
789 reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst);
794 static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie)
796 struct dw_pcie *pci = pcie->pci;
797 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
800 writel(SLV_ADDR_SPACE_SZ,
801 pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_2_3_3);
803 val = readl(pcie->parf + PARF_PHY_CTRL);
804 val &= ~PHY_TEST_PWR_DOWN;
805 writel(val, pcie->parf + PARF_PHY_CTRL);
807 writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
809 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS
810 | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
811 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
812 pcie->parf + PARF_SYS_CTRL);
813 writel(0, pcie->parf + PARF_Q2A_FLUSH);
815 writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
817 dw_pcie_dbi_ro_wr_en(pci);
819 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
821 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
822 val &= ~PCI_EXP_LNKCAP_ASPMS;
823 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
825 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
828 dw_pcie_dbi_ro_wr_dis(pci);
833 static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
835 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
836 struct dw_pcie *pci = pcie->pci;
837 struct device *dev = pci->dev;
838 unsigned int num_clks, num_opt_clks;
842 res->rst = devm_reset_control_array_get_exclusive(dev);
843 if (IS_ERR(res->rst))
844 return PTR_ERR(res->rst);
846 res->supplies[0].supply = "vdda";
847 res->supplies[1].supply = "vddpe-3v3";
848 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
854 res->clks[idx++].id = "aux";
855 res->clks[idx++].id = "cfg";
856 res->clks[idx++].id = "bus_master";
857 res->clks[idx++].id = "bus_slave";
858 res->clks[idx++].id = "slave_q2a";
862 ret = devm_clk_bulk_get(dev, num_clks, res->clks);
866 res->clks[idx++].id = "tbu";
867 res->clks[idx++].id = "ddrss_sf_tbu";
868 res->clks[idx++].id = "aggre0";
869 res->clks[idx++].id = "aggre1";
870 res->clks[idx++].id = "noc_aggr";
871 res->clks[idx++].id = "noc_aggr_4";
872 res->clks[idx++].id = "noc_aggr_south_sf";
873 res->clks[idx++].id = "cnoc_qx";
874 res->clks[idx++].id = "sleep";
875 res->clks[idx++].id = "cnoc_sf_axi";
877 num_opt_clks = idx - num_clks;
880 ret = devm_clk_bulk_get_optional(dev, num_opt_clks, res->clks + num_clks);
887 static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
889 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
890 struct dw_pcie *pci = pcie->pci;
891 struct device *dev = pci->dev;
895 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
897 dev_err(dev, "cannot enable regulators\n");
901 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
903 goto err_disable_regulators;
905 ret = reset_control_assert(res->rst);
907 dev_err(dev, "reset assert failed (%d)\n", ret);
908 goto err_disable_clocks;
911 usleep_range(1000, 1500);
913 ret = reset_control_deassert(res->rst);
915 dev_err(dev, "reset deassert failed (%d)\n", ret);
916 goto err_disable_clocks;
919 /* Wait for reset to complete, required on SM8450 */
920 usleep_range(1000, 1500);
922 /* configure PCIe to RC mode */
923 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);
925 /* enable PCIe clocks and resets */
926 val = readl(pcie->parf + PARF_PHY_CTRL);
927 val &= ~PHY_TEST_PWR_DOWN;
928 writel(val, pcie->parf + PARF_PHY_CTRL);
930 /* change DBI base address */
931 writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
933 /* MAC PHY_POWERDOWN MUX DISABLE */
934 val = readl(pcie->parf + PARF_SYS_CTRL);
935 val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN;
936 writel(val, pcie->parf + PARF_SYS_CTRL);
938 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
940 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
942 /* Enable L1 and L1SS */
943 val = readl(pcie->parf + PARF_PM_CTRL);
944 val &= ~REQ_NOT_ENTR_L1;
945 writel(val, pcie->parf + PARF_PM_CTRL);
947 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
949 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
953 clk_bulk_disable_unprepare(res->num_clks, res->clks);
954 err_disable_regulators:
955 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
960 static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
962 qcom_pcie_clear_hpc(pcie->pci);
967 static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)
969 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
971 clk_bulk_disable_unprepare(res->num_clks, res->clks);
973 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
976 static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *pcie)
978 /* iommu map structure */
985 void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N;
986 struct device *dev = pcie->pci->dev;
987 u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE];
988 int i, nr_map, size = 0;
991 of_get_property(dev->of_node, "iommu-map", &size);
995 map = kzalloc(size, GFP_KERNEL);
999 of_property_read_u32_array(dev->of_node, "iommu-map", (u32 *)map,
1000 size / sizeof(u32));
1002 nr_map = size / (sizeof(*map));
1004 crc8_populate_msb(qcom_pcie_crc8_table, QCOM_PCIE_CRC8_POLYNOMIAL);
1006 /* Registers need to be zero out first */
1007 memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32));
1009 /* Extract the SMMU SID base from the first entry of iommu-map */
1010 smmu_sid_base = map[0].smmu_sid;
1012 /* Look for an available entry to hold the mapping */
1013 for (i = 0; i < nr_map; i++) {
1014 __be16 bdf_be = cpu_to_be16(map[i].bdf);
1018 hash = crc8(qcom_pcie_crc8_table, (u8 *)&bdf_be, sizeof(bdf_be), 0);
1020 val = readl(bdf_to_sid_base + hash * sizeof(u32));
1022 /* If the register is already populated, look for next available entry */
1024 u8 current_hash = hash++;
1025 u8 next_mask = 0xff;
1027 /* If NEXT field is NULL then update it with next hash */
1028 if (!(val & next_mask)) {
1030 writel(val, bdf_to_sid_base + current_hash * sizeof(u32));
1033 val = readl(bdf_to_sid_base + hash * sizeof(u32));
1036 /* BDF [31:16] | SID [15:8] | NEXT [7:0] */
1037 val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0;
1038 writel(val, bdf_to_sid_base + hash * sizeof(u32));
1046 static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie)
1048 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
1049 struct dw_pcie *pci = pcie->pci;
1050 struct device *dev = pci->dev;
1053 res->clks[0].id = "iface";
1054 res->clks[1].id = "axi_m";
1055 res->clks[2].id = "axi_s";
1056 res->clks[3].id = "axi_bridge";
1057 res->clks[4].id = "rchng";
1059 ret = devm_clk_bulk_get(dev, ARRAY_SIZE(res->clks), res->clks);
1063 res->rst = devm_reset_control_array_get_exclusive(dev);
1064 if (IS_ERR(res->rst))
1065 return PTR_ERR(res->rst);
1070 static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie)
1072 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
1074 clk_bulk_disable_unprepare(ARRAY_SIZE(res->clks), res->clks);
1077 static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
1079 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
1080 struct device *dev = pcie->pci->dev;
1083 ret = reset_control_assert(res->rst);
1085 dev_err(dev, "reset assert failed (%d)\n", ret);
1090 * Delay periods before and after reset deassert are working values
1091 * from downstream Codeaurora kernel
1093 usleep_range(2000, 2500);
1095 ret = reset_control_deassert(res->rst);
1097 dev_err(dev, "reset deassert failed (%d)\n", ret);
1101 usleep_range(2000, 2500);
1103 return clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks);
1106 static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
1108 struct dw_pcie *pci = pcie->pci;
1109 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1113 writel(SLV_ADDR_SPACE_SZ,
1114 pcie->parf + PARF_SLV_ADDR_SPACE_SIZE);
1116 val = readl(pcie->parf + PARF_PHY_CTRL);
1117 val &= ~PHY_TEST_PWR_DOWN;
1118 writel(val, pcie->parf + PARF_PHY_CTRL);
1120 writel(0, pcie->parf + PARF_DBI_BASE_ADDR);
1122 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);
1123 writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
1124 pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
1125 writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
1126 GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
1127 pci->dbi_base + GEN3_RELATED_OFF);
1129 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
1130 SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
1131 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
1132 pcie->parf + PARF_SYS_CTRL);
1134 writel(0, pcie->parf + PARF_Q2A_FLUSH);
1136 dw_pcie_dbi_ro_wr_en(pci);
1138 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
1140 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
1141 val &= ~PCI_EXP_LNKCAP_ASPMS;
1142 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
1144 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
1147 dw_pcie_dbi_ro_wr_dis(pci);
1149 for (i = 0; i < 256; i++)
1150 writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i));
1155 static int qcom_pcie_link_up(struct dw_pcie *pci)
1157 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1158 u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
1160 return !!(val & PCI_EXP_LNKSTA_DLLLA);
1163 static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
1165 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1166 struct qcom_pcie *pcie = to_qcom_pcie(pci);
1169 qcom_ep_reset_assert(pcie);
1171 ret = pcie->cfg->ops->init(pcie);
1175 ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
1179 ret = phy_power_on(pcie->phy);
1183 if (pcie->cfg->ops->post_init) {
1184 ret = pcie->cfg->ops->post_init(pcie);
1186 goto err_disable_phy;
1189 qcom_ep_reset_deassert(pcie);
1191 if (pcie->cfg->ops->config_sid) {
1192 ret = pcie->cfg->ops->config_sid(pcie);
1194 goto err_assert_reset;
1200 qcom_ep_reset_assert(pcie);
1202 phy_power_off(pcie->phy);
1204 pcie->cfg->ops->deinit(pcie);
1209 static void qcom_pcie_host_deinit(struct dw_pcie_rp *pp)
1211 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1212 struct qcom_pcie *pcie = to_qcom_pcie(pci);
1214 qcom_ep_reset_assert(pcie);
1215 phy_power_off(pcie->phy);
1216 pcie->cfg->ops->deinit(pcie);
1219 static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
1220 .host_init = qcom_pcie_host_init,
1221 .host_deinit = qcom_pcie_host_deinit,
1224 /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */
1225 static const struct qcom_pcie_ops ops_2_1_0 = {
1226 .get_resources = qcom_pcie_get_resources_2_1_0,
1227 .init = qcom_pcie_init_2_1_0,
1228 .post_init = qcom_pcie_post_init_2_1_0,
1229 .deinit = qcom_pcie_deinit_2_1_0,
1230 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1233 /* Qcom IP rev.: 1.0.0 Synopsys IP rev.: 4.11a */
1234 static const struct qcom_pcie_ops ops_1_0_0 = {
1235 .get_resources = qcom_pcie_get_resources_1_0_0,
1236 .init = qcom_pcie_init_1_0_0,
1237 .post_init = qcom_pcie_post_init_1_0_0,
1238 .deinit = qcom_pcie_deinit_1_0_0,
1239 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1242 /* Qcom IP rev.: 2.3.2 Synopsys IP rev.: 4.21a */
1243 static const struct qcom_pcie_ops ops_2_3_2 = {
1244 .get_resources = qcom_pcie_get_resources_2_3_2,
1245 .init = qcom_pcie_init_2_3_2,
1246 .post_init = qcom_pcie_post_init_2_3_2,
1247 .deinit = qcom_pcie_deinit_2_3_2,
1248 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1251 /* Qcom IP rev.: 2.4.0 Synopsys IP rev.: 4.20a */
1252 static const struct qcom_pcie_ops ops_2_4_0 = {
1253 .get_resources = qcom_pcie_get_resources_2_4_0,
1254 .init = qcom_pcie_init_2_4_0,
1255 .post_init = qcom_pcie_post_init_2_3_2,
1256 .deinit = qcom_pcie_deinit_2_4_0,
1257 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1260 /* Qcom IP rev.: 2.3.3 Synopsys IP rev.: 4.30a */
1261 static const struct qcom_pcie_ops ops_2_3_3 = {
1262 .get_resources = qcom_pcie_get_resources_2_3_3,
1263 .init = qcom_pcie_init_2_3_3,
1264 .post_init = qcom_pcie_post_init_2_3_3,
1265 .deinit = qcom_pcie_deinit_2_3_3,
1266 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1269 /* Qcom IP rev.: 2.7.0 Synopsys IP rev.: 4.30a */
1270 static const struct qcom_pcie_ops ops_2_7_0 = {
1271 .get_resources = qcom_pcie_get_resources_2_7_0,
1272 .init = qcom_pcie_init_2_7_0,
1273 .post_init = qcom_pcie_post_init_2_7_0,
1274 .deinit = qcom_pcie_deinit_2_7_0,
1275 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1278 /* Qcom IP rev.: 1.9.0 */
1279 static const struct qcom_pcie_ops ops_1_9_0 = {
1280 .get_resources = qcom_pcie_get_resources_2_7_0,
1281 .init = qcom_pcie_init_2_7_0,
1282 .post_init = qcom_pcie_post_init_2_7_0,
1283 .deinit = qcom_pcie_deinit_2_7_0,
1284 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1285 .config_sid = qcom_pcie_config_sid_1_9_0,
1288 /* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */
1289 static const struct qcom_pcie_ops ops_2_9_0 = {
1290 .get_resources = qcom_pcie_get_resources_2_9_0,
1291 .init = qcom_pcie_init_2_9_0,
1292 .post_init = qcom_pcie_post_init_2_9_0,
1293 .deinit = qcom_pcie_deinit_2_9_0,
1294 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1297 static const struct qcom_pcie_cfg cfg_1_0_0 = {
1301 static const struct qcom_pcie_cfg cfg_1_9_0 = {
1305 static const struct qcom_pcie_cfg cfg_2_1_0 = {
1309 static const struct qcom_pcie_cfg cfg_2_3_2 = {
1313 static const struct qcom_pcie_cfg cfg_2_3_3 = {
1317 static const struct qcom_pcie_cfg cfg_2_4_0 = {
1321 static const struct qcom_pcie_cfg cfg_2_7_0 = {
1325 static const struct qcom_pcie_cfg cfg_2_9_0 = {
1329 static const struct dw_pcie_ops dw_pcie_ops = {
1330 .link_up = qcom_pcie_link_up,
1331 .start_link = qcom_pcie_start_link,
1334 static int qcom_pcie_icc_init(struct qcom_pcie *pcie)
1336 struct dw_pcie *pci = pcie->pci;
1339 pcie->icc_mem = devm_of_icc_get(pci->dev, "pcie-mem");
1340 if (IS_ERR(pcie->icc_mem))
1341 return PTR_ERR(pcie->icc_mem);
1344 * Some Qualcomm platforms require interconnect bandwidth constraints
1345 * to be set before enabling interconnect clocks.
1347 * Set an initial peak bandwidth corresponding to single-lane Gen 1
1348 * for the pcie-mem path.
1350 ret = icc_set_bw(pcie->icc_mem, 0, MBps_to_icc(250));
1352 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
1360 static void qcom_pcie_icc_update(struct qcom_pcie *pcie)
1362 struct dw_pcie *pci = pcie->pci;
1363 u32 offset, status, bw;
1370 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1371 status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
1373 /* Only update constraints if link is up. */
1374 if (!(status & PCI_EXP_LNKSTA_DLLLA))
1377 speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status);
1378 width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status);
1382 bw = MBps_to_icc(250);
1385 bw = MBps_to_icc(500);
1391 bw = MBps_to_icc(985);
1395 ret = icc_set_bw(pcie->icc_mem, 0, width * bw);
1397 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
1402 static int qcom_pcie_link_transition_count(struct seq_file *s, void *data)
1404 struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private);
1406 seq_printf(s, "L0s transition count: %u\n",
1407 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L0S));
1409 seq_printf(s, "L1 transition count: %u\n",
1410 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L1));
1412 seq_printf(s, "L1.1 transition count: %u\n",
1413 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1));
1415 seq_printf(s, "L1.2 transition count: %u\n",
1416 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2));
1418 seq_printf(s, "L2 transition count: %u\n",
1419 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L2));
1424 static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie)
1426 struct dw_pcie *pci = pcie->pci;
1427 struct device *dev = pci->dev;
1430 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node);
1434 pcie->debugfs = debugfs_create_dir(name, NULL);
1435 debugfs_create_devm_seqfile(dev, "link_transition_count", pcie->debugfs,
1436 qcom_pcie_link_transition_count);
1439 static int qcom_pcie_probe(struct platform_device *pdev)
1441 const struct qcom_pcie_cfg *pcie_cfg;
1442 struct device *dev = &pdev->dev;
1443 struct qcom_pcie *pcie;
1444 struct dw_pcie_rp *pp;
1445 struct resource *res;
1446 struct dw_pcie *pci;
1449 pcie_cfg = of_device_get_match_data(dev);
1450 if (!pcie_cfg || !pcie_cfg->ops) {
1451 dev_err(dev, "Invalid platform data\n");
1455 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1459 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
1463 pm_runtime_enable(dev);
1464 ret = pm_runtime_get_sync(dev);
1466 goto err_pm_runtime_put;
1469 pci->ops = &dw_pcie_ops;
1474 pcie->cfg = pcie_cfg;
1476 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
1477 if (IS_ERR(pcie->reset)) {
1478 ret = PTR_ERR(pcie->reset);
1479 goto err_pm_runtime_put;
1482 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
1483 if (IS_ERR(pcie->parf)) {
1484 ret = PTR_ERR(pcie->parf);
1485 goto err_pm_runtime_put;
1488 pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi");
1489 if (IS_ERR(pcie->elbi)) {
1490 ret = PTR_ERR(pcie->elbi);
1491 goto err_pm_runtime_put;
1494 /* MHI region is optional */
1495 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mhi");
1497 pcie->mhi = devm_ioremap_resource(dev, res);
1498 if (IS_ERR(pcie->mhi)) {
1499 ret = PTR_ERR(pcie->mhi);
1500 goto err_pm_runtime_put;
1504 pcie->phy = devm_phy_optional_get(dev, "pciephy");
1505 if (IS_ERR(pcie->phy)) {
1506 ret = PTR_ERR(pcie->phy);
1507 goto err_pm_runtime_put;
1510 ret = qcom_pcie_icc_init(pcie);
1512 goto err_pm_runtime_put;
1514 ret = pcie->cfg->ops->get_resources(pcie);
1516 goto err_pm_runtime_put;
1518 pp->ops = &qcom_pcie_dw_ops;
1520 ret = phy_init(pcie->phy);
1522 goto err_pm_runtime_put;
1524 platform_set_drvdata(pdev, pcie);
1526 ret = dw_pcie_host_init(pp);
1528 dev_err(dev, "cannot initialize host\n");
1532 qcom_pcie_icc_update(pcie);
1535 qcom_pcie_init_debugfs(pcie);
1540 phy_exit(pcie->phy);
1542 pm_runtime_put(dev);
1543 pm_runtime_disable(dev);
1548 static int qcom_pcie_suspend_noirq(struct device *dev)
1550 struct qcom_pcie *pcie = dev_get_drvdata(dev);
1554 * Set minimum bandwidth required to keep data path functional during
1557 ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1));
1559 dev_err(dev, "Failed to set interconnect bandwidth: %d\n", ret);
1564 * Turn OFF the resources only for controllers without active PCIe
1565 * devices. For controllers with active devices, the resources are kept
1566 * ON and the link is expected to be in L0/L1 (sub)states.
1568 * Turning OFF the resources for controllers with active PCIe devices
1569 * will trigger access violation during the end of the suspend cycle,
1570 * as kernel tries to access the PCIe devices config space for masking
1573 * Also, it is not desirable to put the link into L2/L3 state as that
1574 * implies VDD supply will be removed and the devices may go into
1575 * powerdown state. This will affect the lifetime of the storage devices
1578 if (!dw_pcie_link_up(pcie->pci)) {
1579 qcom_pcie_host_deinit(&pcie->pci->pp);
1580 pcie->suspended = true;
1586 static int qcom_pcie_resume_noirq(struct device *dev)
1588 struct qcom_pcie *pcie = dev_get_drvdata(dev);
1591 if (pcie->suspended) {
1592 ret = qcom_pcie_host_init(&pcie->pci->pp);
1596 pcie->suspended = false;
1599 qcom_pcie_icc_update(pcie);
1604 static const struct of_device_id qcom_pcie_match[] = {
1605 { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
1606 { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
1607 { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
1608 { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
1609 { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
1610 { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
1611 { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
1612 { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
1613 { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
1614 { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
1615 { .compatible = "qcom,pcie-sa8540p", .data = &cfg_1_9_0 },
1616 { .compatible = "qcom,pcie-sa8775p", .data = &cfg_1_9_0},
1617 { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 },
1618 { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 },
1619 { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_1_9_0 },
1620 { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 },
1621 { .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 },
1622 { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 },
1623 { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
1624 { .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 },
1625 { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
1626 { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
1627 { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
1631 static void qcom_fixup_class(struct pci_dev *dev)
1633 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
1635 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0101, qcom_fixup_class);
1636 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0104, qcom_fixup_class);
1637 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0106, qcom_fixup_class);
1638 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0107, qcom_fixup_class);
1639 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0302, qcom_fixup_class);
1640 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1000, qcom_fixup_class);
1641 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1001, qcom_fixup_class);
1643 static const struct dev_pm_ops qcom_pcie_pm_ops = {
1644 NOIRQ_SYSTEM_SLEEP_PM_OPS(qcom_pcie_suspend_noirq, qcom_pcie_resume_noirq)
1647 static struct platform_driver qcom_pcie_driver = {
1648 .probe = qcom_pcie_probe,
1650 .name = "qcom-pcie",
1651 .suppress_bind_attrs = true,
1652 .of_match_table = qcom_pcie_match,
1653 .pm = &qcom_pcie_pm_ops,
1654 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1657 builtin_platform_driver(qcom_pcie_driver);