1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Freescale i.MX6 SoCs
5 * Copyright (C) 2013 Kosagi
6 * http://www.kosagi.com
8 * Author: Sean Cross <xobs@kosagi.com>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/gpio.h>
14 #include <linux/kernel.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
17 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
18 #include <linux/module.h>
19 #include <linux/of_gpio.h>
20 #include <linux/of_device.h>
21 #include <linux/pci.h>
22 #include <linux/platform_device.h>
23 #include <linux/regmap.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/resource.h>
26 #include <linux/signal.h>
27 #include <linux/types.h>
28 #include <linux/interrupt.h>
29 #include <linux/reset.h>
30 #include <linux/pm_domain.h>
31 #include <linux/pm_runtime.h>
33 #include "pcie-designware.h"
35 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
37 enum imx6_pcie_variants {
47 bool gpio_active_high;
50 struct clk *pcie_inbound_axi;
52 struct regmap *iomuxc_gpr;
53 struct reset_control *pciephy_reset;
54 struct reset_control *apps_reset;
55 struct reset_control *turnoff_reset;
56 enum imx6_pcie_variants variant;
58 u32 tx_deemph_gen2_3p5db;
59 u32 tx_deemph_gen2_6db;
63 struct regulator *vpcie;
65 /* power domain for pcie */
66 struct device *pd_pcie;
67 /* power domain for pcie phy */
68 struct device *pd_pcie_phy;
71 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
72 #define PHY_PLL_LOCK_WAIT_MAX_RETRIES 2000
73 #define PHY_PLL_LOCK_WAIT_USLEEP_MIN 50
74 #define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200
76 /* PCIe Root Complex registers (memory-mapped) */
77 #define PCIE_RC_IMX6_MSI_CAP 0x50
78 #define PCIE_RC_LCR 0x7c
79 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
80 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
81 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
83 #define PCIE_RC_LCSR 0x80
85 /* PCIe Port Logic registers (memory-mapped) */
86 #define PL_OFFSET 0x700
87 #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
88 #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
89 #define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
90 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
91 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
93 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
94 #define PCIE_PHY_CTRL_DATA_LOC 0
95 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
96 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
97 #define PCIE_PHY_CTRL_WR_LOC 18
98 #define PCIE_PHY_CTRL_RD_LOC 19
100 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
101 #define PCIE_PHY_STAT_ACK_LOC 16
103 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
104 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
106 /* PHY registers (not memory-mapped) */
107 #define PCIE_PHY_ATEOVRD 0x10
108 #define PCIE_PHY_ATEOVRD_EN (0x1 << 2)
109 #define PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT 0
110 #define PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK 0x1
112 #define PCIE_PHY_MPLL_OVRD_IN_LO 0x11
113 #define PCIE_PHY_MPLL_MULTIPLIER_SHIFT 2
114 #define PCIE_PHY_MPLL_MULTIPLIER_MASK 0x7f
115 #define PCIE_PHY_MPLL_MULTIPLIER_OVRD (0x1 << 9)
117 #define PCIE_PHY_RX_ASIC_OUT 0x100D
118 #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0)
120 #define PHY_RX_OVRD_IN_LO 0x1005
121 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
122 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
124 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
126 struct dw_pcie *pci = imx6_pcie->pci;
128 u32 max_iterations = 10;
129 u32 wait_counter = 0;
132 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
133 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
140 } while (wait_counter < max_iterations);
145 static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
147 struct dw_pcie *pci = imx6_pcie->pci;
151 val = addr << PCIE_PHY_CTRL_DATA_LOC;
152 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
154 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
155 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
157 ret = pcie_phy_poll_ack(imx6_pcie, 1);
161 val = addr << PCIE_PHY_CTRL_DATA_LOC;
162 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
164 return pcie_phy_poll_ack(imx6_pcie, 0);
167 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
168 static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
170 struct dw_pcie *pci = imx6_pcie->pci;
174 ret = pcie_phy_wait_ack(imx6_pcie, addr);
178 /* assert Read signal */
179 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
180 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
182 ret = pcie_phy_poll_ack(imx6_pcie, 1);
186 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
187 *data = val & 0xffff;
189 /* deassert Read signal */
190 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
192 return pcie_phy_poll_ack(imx6_pcie, 0);
195 static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
197 struct dw_pcie *pci = imx6_pcie->pci;
203 ret = pcie_phy_wait_ack(imx6_pcie, addr);
207 var = data << PCIE_PHY_CTRL_DATA_LOC;
208 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
211 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
212 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
214 ret = pcie_phy_poll_ack(imx6_pcie, 1);
218 /* deassert cap data */
219 var = data << PCIE_PHY_CTRL_DATA_LOC;
220 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
222 /* wait for ack de-assertion */
223 ret = pcie_phy_poll_ack(imx6_pcie, 0);
227 /* assert wr signal */
228 var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
229 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
232 ret = pcie_phy_poll_ack(imx6_pcie, 1);
236 /* deassert wr signal */
237 var = data << PCIE_PHY_CTRL_DATA_LOC;
238 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
240 /* wait for ack de-assertion */
241 ret = pcie_phy_poll_ack(imx6_pcie, 0);
245 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0);
250 static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
254 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
255 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
256 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
257 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
259 usleep_range(2000, 3000);
261 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
262 tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
263 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
264 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
267 /* Added for PCI abort handling */
268 static int imx6q_pcie_abort_handler(unsigned long addr,
269 unsigned int fsr, struct pt_regs *regs)
271 unsigned long pc = instruction_pointer(regs);
272 unsigned long instr = *(unsigned long *)pc;
273 int reg = (instr >> 12) & 15;
276 * If the instruction being executed was a read,
277 * make it look like it read all-ones.
279 if ((instr & 0x0c100000) == 0x04100000) {
282 if (instr & 0x00400000)
287 regs->uregs[reg] = val;
292 if ((instr & 0x0e100090) == 0x00100090) {
293 regs->uregs[reg] = -1;
301 static int imx6_pcie_attach_pd(struct device *dev)
303 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
304 struct device_link *link;
306 /* Do nothing when in a single power domain */
310 imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie");
311 if (IS_ERR(imx6_pcie->pd_pcie))
312 return PTR_ERR(imx6_pcie->pd_pcie);
313 link = device_link_add(dev, imx6_pcie->pd_pcie,
318 dev_err(dev, "Failed to add device_link to pcie pd.\n");
322 imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy");
323 if (IS_ERR(imx6_pcie->pd_pcie_phy))
324 return PTR_ERR(imx6_pcie->pd_pcie_phy);
326 device_link_add(dev, imx6_pcie->pd_pcie_phy,
331 dev_err(dev, "Failed to add device_link to pcie_phy pd: %ld\n", PTR_ERR(link));
332 return PTR_ERR(link);
338 static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
340 struct device *dev = imx6_pcie->pci->dev;
342 switch (imx6_pcie->variant) {
344 reset_control_assert(imx6_pcie->pciephy_reset);
345 reset_control_assert(imx6_pcie->apps_reset);
348 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
349 IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
350 IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
351 /* Force PCIe PHY reset */
352 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
353 IMX6SX_GPR5_PCIE_BTNRST_RESET,
354 IMX6SX_GPR5_PCIE_BTNRST_RESET);
357 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
358 IMX6Q_GPR1_PCIE_SW_RST,
359 IMX6Q_GPR1_PCIE_SW_RST);
362 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
363 IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
364 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
365 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
369 if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
370 int ret = regulator_disable(imx6_pcie->vpcie);
373 dev_err(dev, "failed to disable vpcie regulator: %d\n",
378 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
380 struct dw_pcie *pci = imx6_pcie->pci;
381 struct device *dev = pci->dev;
384 switch (imx6_pcie->variant) {
386 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
388 dev_err(dev, "unable to enable pcie_axi clock\n");
392 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
393 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
395 case IMX6QP: /* FALLTHROUGH */
397 /* power up core phy and enable ref clock */
398 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
399 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
401 * the async reset input need ref clock to sync internally,
402 * when the ref clock comes after reset, internal synced
403 * reset time is too short, cannot meet the requirement.
404 * add one ~10us delay here.
407 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
408 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
417 static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
420 unsigned int retries;
421 struct device *dev = imx6_pcie->pci->dev;
423 for (retries = 0; retries < PHY_PLL_LOCK_WAIT_MAX_RETRIES; retries++) {
424 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR22, &val);
426 if (val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED)
429 usleep_range(PHY_PLL_LOCK_WAIT_USLEEP_MIN,
430 PHY_PLL_LOCK_WAIT_USLEEP_MAX);
433 dev_err(dev, "PCIe PLL lock timeout\n");
436 static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
438 struct dw_pcie *pci = imx6_pcie->pci;
439 struct device *dev = pci->dev;
442 if (imx6_pcie->vpcie && !regulator_is_enabled(imx6_pcie->vpcie)) {
443 ret = regulator_enable(imx6_pcie->vpcie);
445 dev_err(dev, "failed to enable vpcie regulator: %d\n",
451 ret = clk_prepare_enable(imx6_pcie->pcie_phy);
453 dev_err(dev, "unable to enable pcie_phy clock\n");
457 ret = clk_prepare_enable(imx6_pcie->pcie_bus);
459 dev_err(dev, "unable to enable pcie_bus clock\n");
463 ret = clk_prepare_enable(imx6_pcie->pcie);
465 dev_err(dev, "unable to enable pcie clock\n");
469 ret = imx6_pcie_enable_ref_clk(imx6_pcie);
471 dev_err(dev, "unable to enable pcie ref clock\n");
475 /* allow the clocks to stabilize */
476 usleep_range(200, 500);
478 /* Some boards don't have PCIe reset GPIO. */
479 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
480 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
481 imx6_pcie->gpio_active_high);
483 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
484 !imx6_pcie->gpio_active_high);
487 switch (imx6_pcie->variant) {
489 reset_control_deassert(imx6_pcie->pciephy_reset);
490 imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
493 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
494 IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
497 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
498 IMX6Q_GPR1_PCIE_SW_RST, 0);
500 usleep_range(200, 500);
502 case IMX6Q: /* Nothing to do */
509 clk_disable_unprepare(imx6_pcie->pcie);
511 clk_disable_unprepare(imx6_pcie->pcie_bus);
513 clk_disable_unprepare(imx6_pcie->pcie_phy);
515 if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
516 ret = regulator_disable(imx6_pcie->vpcie);
518 dev_err(dev, "failed to disable vpcie regulator: %d\n",
523 static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
525 switch (imx6_pcie->variant) {
527 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
528 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
531 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
532 IMX6SX_GPR12_PCIE_RX_EQ_MASK,
533 IMX6SX_GPR12_PCIE_RX_EQ_2);
536 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
537 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
539 /* configure constant input signal to the pcie ctrl and phy */
540 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
541 IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
543 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
544 IMX6Q_GPR8_TX_DEEMPH_GEN1,
545 imx6_pcie->tx_deemph_gen1 << 0);
546 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
547 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
548 imx6_pcie->tx_deemph_gen2_3p5db << 6);
549 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
550 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
551 imx6_pcie->tx_deemph_gen2_6db << 12);
552 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
553 IMX6Q_GPR8_TX_SWING_FULL,
554 imx6_pcie->tx_swing_full << 18);
555 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
556 IMX6Q_GPR8_TX_SWING_LOW,
557 imx6_pcie->tx_swing_low << 25);
561 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
562 IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
565 static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
567 unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy);
574 * The default settings of the MPLL are for a 125MHz input
575 * clock, so no need to reconfigure anything in that case.
587 dev_err(imx6_pcie->pci->dev,
588 "Unsupported PHY reference clock rate %lu\n", phy_rate);
592 pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val);
593 val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK <<
594 PCIE_PHY_MPLL_MULTIPLIER_SHIFT);
595 val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT;
596 val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD;
597 pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val);
599 pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val);
600 val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK <<
601 PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT);
602 val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT;
603 val |= PCIE_PHY_ATEOVRD_EN;
604 pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val);
609 static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
611 struct dw_pcie *pci = imx6_pcie->pci;
612 struct device *dev = pci->dev;
614 /* check if the link is up or not */
615 if (!dw_pcie_wait_for_link(pci))
618 dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
619 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
620 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
624 static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
626 struct dw_pcie *pci = imx6_pcie->pci;
627 struct device *dev = pci->dev;
629 unsigned int retries;
631 for (retries = 0; retries < 200; retries++) {
632 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
633 /* Test if the speed change finished. */
634 if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
636 usleep_range(100, 1000);
639 dev_err(dev, "Speed change timeout\n");
643 static void imx6_pcie_ltssm_enable(struct device *dev)
645 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
647 switch (imx6_pcie->variant) {
651 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
652 IMX6Q_GPR12_PCIE_CTL_2,
653 IMX6Q_GPR12_PCIE_CTL_2);
656 reset_control_deassert(imx6_pcie->apps_reset);
661 static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
663 struct dw_pcie *pci = imx6_pcie->pci;
664 struct device *dev = pci->dev;
669 * Force Gen1 operation when starting the link. In case the link is
670 * started in Gen2 mode, there is a possibility the devices on the
671 * bus will not be detected at all. This happens with PCIe switches.
673 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
674 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
675 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
676 dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
679 imx6_pcie_ltssm_enable(dev);
681 ret = imx6_pcie_wait_for_link(imx6_pcie);
685 if (imx6_pcie->link_gen == 2) {
686 /* Allow Gen2 mode after the link is up. */
687 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
688 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
689 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
690 dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
693 * Start Directed Speed Change so the best possible
694 * speed both link partners support can be negotiated.
696 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
697 tmp |= PORT_LOGIC_SPEED_CHANGE;
698 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
700 if (imx6_pcie->variant != IMX7D) {
702 * On i.MX7, DIRECT_SPEED_CHANGE behaves differently
703 * from i.MX6 family when no link speed transition
704 * occurs and we go Gen1 -> yep, Gen1. The difference
705 * is that, in such case, it will not be cleared by HW
706 * which will cause the following code to report false
710 ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
712 dev_err(dev, "Failed to bring link up!\n");
717 /* Make sure link training is finished as well! */
718 ret = imx6_pcie_wait_for_link(imx6_pcie);
720 dev_err(dev, "Failed to bring link up!\n");
724 dev_info(dev, "Link: Gen2 disabled\n");
727 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR);
728 dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
732 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
733 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
734 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
735 imx6_pcie_reset_phy(imx6_pcie);
739 static int imx6_pcie_host_init(struct pcie_port *pp)
741 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
742 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
744 imx6_pcie_assert_core_reset(imx6_pcie);
745 imx6_pcie_init_phy(imx6_pcie);
746 imx6_pcie_deassert_core_reset(imx6_pcie);
747 imx6_setup_phy_mpll(imx6_pcie);
748 dw_pcie_setup_rc(pp);
749 imx6_pcie_establish_link(imx6_pcie);
751 if (IS_ENABLED(CONFIG_PCI_MSI))
752 dw_pcie_msi_init(pp);
757 static const struct dw_pcie_host_ops imx6_pcie_host_ops = {
758 .host_init = imx6_pcie_host_init,
761 static int imx6_add_pcie_port(struct imx6_pcie *imx6_pcie,
762 struct platform_device *pdev)
764 struct dw_pcie *pci = imx6_pcie->pci;
765 struct pcie_port *pp = &pci->pp;
766 struct device *dev = &pdev->dev;
769 if (IS_ENABLED(CONFIG_PCI_MSI)) {
770 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
771 if (pp->msi_irq <= 0) {
772 dev_err(dev, "failed to get MSI irq\n");
777 pp->ops = &imx6_pcie_host_ops;
779 ret = dw_pcie_host_init(pp);
781 dev_err(dev, "failed to initialize host\n");
788 static const struct dw_pcie_ops dw_pcie_ops = {
789 /* No special ops needed, but pcie-designware still expects this struct */
792 #ifdef CONFIG_PM_SLEEP
793 static void imx6_pcie_ltssm_disable(struct device *dev)
795 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
797 switch (imx6_pcie->variant) {
800 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
801 IMX6Q_GPR12_PCIE_CTL_2, 0);
804 reset_control_assert(imx6_pcie->apps_reset);
807 dev_err(dev, "ltssm_disable not supported\n");
811 static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
813 struct device *dev = imx6_pcie->pci->dev;
815 /* Some variants have a turnoff reset in DT */
816 if (imx6_pcie->turnoff_reset) {
817 reset_control_assert(imx6_pcie->turnoff_reset);
818 reset_control_deassert(imx6_pcie->turnoff_reset);
819 goto pm_turnoff_sleep;
822 /* Others poke directly at IOMUXC registers */
823 switch (imx6_pcie->variant) {
825 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
826 IMX6SX_GPR12_PCIE_PM_TURN_OFF,
827 IMX6SX_GPR12_PCIE_PM_TURN_OFF);
828 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
829 IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0);
832 dev_err(dev, "PME_Turn_Off not implemented\n");
837 * Components with an upstream port must respond to
838 * PME_Turn_Off with PME_TO_Ack but we can't check.
840 * The standard recommends a 1-10ms timeout after which to
841 * proceed anyway as if acks were received.
844 usleep_range(1000, 10000);
847 static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
849 clk_disable_unprepare(imx6_pcie->pcie);
850 clk_disable_unprepare(imx6_pcie->pcie_phy);
851 clk_disable_unprepare(imx6_pcie->pcie_bus);
853 switch (imx6_pcie->variant) {
855 clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
858 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
859 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
860 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
867 static inline bool imx6_pcie_supports_suspend(struct imx6_pcie *imx6_pcie)
869 return (imx6_pcie->variant == IMX7D ||
870 imx6_pcie->variant == IMX6SX);
873 static int imx6_pcie_suspend_noirq(struct device *dev)
875 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
877 if (!imx6_pcie_supports_suspend(imx6_pcie))
880 imx6_pcie_pm_turnoff(imx6_pcie);
881 imx6_pcie_clk_disable(imx6_pcie);
882 imx6_pcie_ltssm_disable(dev);
887 static int imx6_pcie_resume_noirq(struct device *dev)
890 struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
891 struct pcie_port *pp = &imx6_pcie->pci->pp;
893 if (!imx6_pcie_supports_suspend(imx6_pcie))
896 imx6_pcie_assert_core_reset(imx6_pcie);
897 imx6_pcie_init_phy(imx6_pcie);
898 imx6_pcie_deassert_core_reset(imx6_pcie);
899 dw_pcie_setup_rc(pp);
901 ret = imx6_pcie_establish_link(imx6_pcie);
903 dev_info(dev, "pcie link is down after resume.\n");
909 static const struct dev_pm_ops imx6_pcie_pm_ops = {
910 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq,
911 imx6_pcie_resume_noirq)
914 static int imx6_pcie_probe(struct platform_device *pdev)
916 struct device *dev = &pdev->dev;
918 struct imx6_pcie *imx6_pcie;
919 struct resource *dbi_base;
920 struct device_node *node = dev->of_node;
924 imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
928 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
933 pci->ops = &dw_pcie_ops;
935 imx6_pcie->pci = pci;
937 (enum imx6_pcie_variants)of_device_get_match_data(dev);
939 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
940 pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
941 if (IS_ERR(pci->dbi_base))
942 return PTR_ERR(pci->dbi_base);
945 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
946 imx6_pcie->gpio_active_high = of_property_read_bool(node,
947 "reset-gpio-active-high");
948 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
949 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
950 imx6_pcie->gpio_active_high ?
951 GPIOF_OUT_INIT_HIGH :
955 dev_err(dev, "unable to get reset gpio\n");
958 } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
959 return imx6_pcie->reset_gpio;
963 imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
964 if (IS_ERR(imx6_pcie->pcie_phy)) {
965 dev_err(dev, "pcie_phy clock source missing or invalid\n");
966 return PTR_ERR(imx6_pcie->pcie_phy);
969 imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
970 if (IS_ERR(imx6_pcie->pcie_bus)) {
971 dev_err(dev, "pcie_bus clock source missing or invalid\n");
972 return PTR_ERR(imx6_pcie->pcie_bus);
975 imx6_pcie->pcie = devm_clk_get(dev, "pcie");
976 if (IS_ERR(imx6_pcie->pcie)) {
977 dev_err(dev, "pcie clock source missing or invalid\n");
978 return PTR_ERR(imx6_pcie->pcie);
981 switch (imx6_pcie->variant) {
983 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
985 if (IS_ERR(imx6_pcie->pcie_inbound_axi)) {
986 dev_err(dev, "pcie_inbound_axi clock missing or invalid\n");
987 return PTR_ERR(imx6_pcie->pcie_inbound_axi);
991 imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev,
993 if (IS_ERR(imx6_pcie->pciephy_reset)) {
994 dev_err(dev, "Failed to get PCIEPHY reset control\n");
995 return PTR_ERR(imx6_pcie->pciephy_reset);
998 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev,
1000 if (IS_ERR(imx6_pcie->apps_reset)) {
1001 dev_err(dev, "Failed to get PCIE APPS reset control\n");
1002 return PTR_ERR(imx6_pcie->apps_reset);
1009 /* Grab turnoff reset */
1010 imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff");
1011 if (IS_ERR(imx6_pcie->turnoff_reset)) {
1012 dev_err(dev, "Failed to get TURNOFF reset control\n");
1013 return PTR_ERR(imx6_pcie->turnoff_reset);
1016 /* Grab GPR config register range */
1017 imx6_pcie->iomuxc_gpr =
1018 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
1019 if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
1020 dev_err(dev, "unable to find iomuxc registers\n");
1021 return PTR_ERR(imx6_pcie->iomuxc_gpr);
1024 /* Grab PCIe PHY Tx Settings */
1025 if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
1026 &imx6_pcie->tx_deemph_gen1))
1027 imx6_pcie->tx_deemph_gen1 = 0;
1029 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
1030 &imx6_pcie->tx_deemph_gen2_3p5db))
1031 imx6_pcie->tx_deemph_gen2_3p5db = 0;
1033 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
1034 &imx6_pcie->tx_deemph_gen2_6db))
1035 imx6_pcie->tx_deemph_gen2_6db = 20;
1037 if (of_property_read_u32(node, "fsl,tx-swing-full",
1038 &imx6_pcie->tx_swing_full))
1039 imx6_pcie->tx_swing_full = 127;
1041 if (of_property_read_u32(node, "fsl,tx-swing-low",
1042 &imx6_pcie->tx_swing_low))
1043 imx6_pcie->tx_swing_low = 127;
1045 /* Limit link speed */
1046 ret = of_property_read_u32(node, "fsl,max-link-speed",
1047 &imx6_pcie->link_gen);
1049 imx6_pcie->link_gen = 1;
1051 imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
1052 if (IS_ERR(imx6_pcie->vpcie)) {
1053 if (PTR_ERR(imx6_pcie->vpcie) == -EPROBE_DEFER)
1054 return -EPROBE_DEFER;
1055 imx6_pcie->vpcie = NULL;
1058 platform_set_drvdata(pdev, imx6_pcie);
1060 ret = imx6_pcie_attach_pd(dev);
1064 ret = imx6_add_pcie_port(imx6_pcie, pdev);
1068 if (pci_msi_enabled()) {
1069 val = dw_pcie_readw_dbi(pci, PCIE_RC_IMX6_MSI_CAP +
1071 val |= PCI_MSI_FLAGS_ENABLE;
1072 dw_pcie_writew_dbi(pci, PCIE_RC_IMX6_MSI_CAP + PCI_MSI_FLAGS,
1079 static void imx6_pcie_shutdown(struct platform_device *pdev)
1081 struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
1083 /* bring down link, so bootloader gets clean state in case of reboot */
1084 imx6_pcie_assert_core_reset(imx6_pcie);
1087 static const struct of_device_id imx6_pcie_of_match[] = {
1088 { .compatible = "fsl,imx6q-pcie", .data = (void *)IMX6Q, },
1089 { .compatible = "fsl,imx6sx-pcie", .data = (void *)IMX6SX, },
1090 { .compatible = "fsl,imx6qp-pcie", .data = (void *)IMX6QP, },
1091 { .compatible = "fsl,imx7d-pcie", .data = (void *)IMX7D, },
1095 static struct platform_driver imx6_pcie_driver = {
1097 .name = "imx6q-pcie",
1098 .of_match_table = imx6_pcie_of_match,
1099 .suppress_bind_attrs = true,
1100 .pm = &imx6_pcie_pm_ops,
1102 .probe = imx6_pcie_probe,
1103 .shutdown = imx6_pcie_shutdown,
1106 static int __init imx6_pcie_init(void)
1109 * Since probe() can be deferred we need to make sure that
1110 * hook_fault_code is not called after __init memory is freed
1111 * by kernel and since imx6q_pcie_abort_handler() is a no-op,
1112 * we can install the handler here without risking it
1113 * accessing some uninitialized driver state.
1115 hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0,
1116 "external abort on non-linefetch");
1118 return platform_driver_register(&imx6_pcie_driver);
1120 device_initcall(imx6_pcie_init);