1 # SPDX-License-Identifier: GPL-2.0
6 # select this to offer the PCI prompt
10 # select this to unconditionally force on PCI support
20 This option enables support for the PCI local bus, including
21 support for PCI-X and the foundations for PCI Express support.
22 Say 'Y' here unless you know what you are doing.
30 config PCI_DOMAINS_GENERIC
37 source "drivers/pci/pcie/Kconfig"
40 bool "Message Signaled Interrupts (MSI and MSI-X)"
41 select GENERIC_MSI_IRQ
43 This allows device drivers to enable MSI (Message Signaled
44 Interrupts). Message Signaled Interrupts enable a device to
45 generate an interrupt using an inbound Memory Write on its
46 PCI bus instead of asserting a device IRQ pin.
48 Use of PCI MSI interrupts can be disabled at kernel boot time
49 by using the 'pci=nomsi' option. This disables MSI for the
52 If you don't know what to do here, say Y.
54 config PCI_MSI_IRQ_DOMAIN
57 select GENERIC_MSI_IRQ_DOMAIN
59 config PCI_MSI_ARCH_FALLBACKS
64 bool "Enable PCI quirk workarounds" if EXPERT
66 This enables workarounds for various PCI chipset bugs/quirks.
67 Disable this only if your target machine is unaffected by PCI
72 depends on DEBUG_KERNEL
74 Say Y here if you want the PCI core to produce a bunch of debug
75 messages to the system log. Select this if you are having a
76 problem with PCI support and want to see more of what is going on.
80 config PCI_REALLOC_ENABLE_AUTO
81 bool "Enable PCI resource re-allocation detection"
84 Say Y here if you want the PCI core to detect if PCI resource
85 re-allocation needs to be enabled. You can always use pci=realloc=on
86 or pci=realloc=off to override it. It will automatically
87 re-allocate PCI resources if SR-IOV BARs have not been allocated by
93 tristate "PCI Stub driver"
95 Say Y or M here if you want be able to reserve a PCI device
96 when it is going to be assigned to a guest operating system.
101 tristate "PCI PF Stub driver"
104 Say Y or M here if you want to enable support for devices that
105 require SR-IOV support, while at the same time the PF (Physical
106 Function) itself is not providing any actual services on the
107 host itself such as storage or networking.
109 When in doubt, say N.
111 config XEN_PCIDEV_FRONTEND
112 tristate "Xen PCI Frontend"
115 select XEN_XENBUS_FRONTEND
118 The PCI device frontend driver allows the kernel to import arbitrary
119 PCI devices from a PCI backend to support PCI driver domains.
130 config PCI_LOCKLESS_CONFIG
133 config PCI_BRIDGE_EMUL
137 bool "PCI IOV support"
140 I/O Virtualization is a PCI feature supported by some devices
141 which allows them to create virtual devices which share their
147 bool "PCI PRI support"
150 PRI is the PCI Page Request Interface. It allows PCI devices that are
151 behind an IOMMU to recover from page faults.
156 bool "PCI PASID support"
159 Process Address Space Identifiers (PASIDs) can be used by PCI devices
160 to access more than one IO address space at the same time. To make
161 use of this feature an IOMMU is required which also supports PASIDs.
162 Select this option if you have such an IOMMU and want to compile the
163 driver for it into your kernel.
168 bool "PCI peer-to-peer transfer support"
169 depends on ZONE_DEVICE
171 # The need for the scatterlist DMA bus address flag means PCI P2PDMA
175 select GENERIC_ALLOCATOR
177 Enableѕ drivers to do PCI peer-to-peer transactions to and from
178 BARs that are exposed in other devices that are the part of
179 the hierarchy where peer-to-peer DMA is guaranteed by the PCI
180 specification to work (ie. anything below a single PCI bridge).
182 Many PCIe root complexes do not support P2P transactions and
183 it's hard to tell which support it at all, so at this time,
184 P2P DMA transactions must be between devices behind the same root
190 def_bool y if (DMI || ACPI)
194 tristate "Hyper-V PCI Frontend"
195 depends on ((X86 && X86_64) || ARM64) && HYPERV && PCI_MSI && PCI_MSI_IRQ_DOMAIN && SYSFS
196 select PCI_HYPERV_INTERFACE
198 The PCI device frontend driver allows the kernel to import arbitrary
199 PCI devices from a PCI backend to support PCI driver domains.
202 prompt "PCI Express hierarchy optimization setting"
203 default PCIE_BUS_DEFAULT
204 depends on PCI && EXPERT
206 MPS (Max Payload Size) and MRRS (Max Read Request Size) are PCIe
207 device parameters that affect performance and the ability to
208 support hotplug and peer-to-peer DMA.
210 The following choices set the MPS and MRRS optimization strategy
211 at compile-time. The choices are the same as those offered for
212 the kernel command-line parameter 'pci', i.e.,
213 'pci=pcie_bus_tune_off', 'pci=pcie_bus_safe',
214 'pci=pcie_bus_perf', and 'pci=pcie_bus_peer2peer'.
216 This is a compile-time setting and can be overridden by the above
217 command-line parameters. If unsure, choose PCIE_BUS_DEFAULT.
219 config PCIE_BUS_TUNE_OFF
223 Use the BIOS defaults; don't touch MPS at all. This is the same
224 as booting with 'pci=pcie_bus_tune_off'.
226 config PCIE_BUS_DEFAULT
230 Default choice; ensure that the MPS matches upstream bridge.
236 Use largest MPS that boot-time devices support. If you have a
237 closed system with no possibility of adding new devices, this
238 will use the largest MPS that's supported by all devices. This
239 is the same as booting with 'pci=pcie_bus_safe'.
241 config PCIE_BUS_PERFORMANCE
245 Use MPS and MRRS for best performance. Ensure that a given
246 device's MPS is no larger than its parent MPS, which allows us to
247 keep all switches/bridges to the max MPS supported by their
248 parent. This is the same as booting with 'pci=pcie_bus_perf'.
250 config PCIE_BUS_PEER2PEER
254 Set MPS = 128 for all devices. MPS configuration effected by the
255 other options could cause the MPS on one root port to be
256 different than that of the MPS on another, which may cause
257 hot-added devices or peer-to-peer DMA to fail. Set MPS to the
258 smallest possible value (128B) system-wide to avoid these issues.
259 This is the same as booting with 'pci=pcie_bus_peer2peer'.
264 bool "VGA Arbitration" if EXPERT
266 depends on (PCI && !S390)
268 Some "legacy" VGA devices implemented on PCI typically have the same
269 hard-decoded addresses as they did on ISA. When multiple PCI devices
270 are accessed at same time they need some kind of coordination. Please
271 see Documentation/gpu/vgaarbiter.rst for more details. Select this to
274 config VGA_ARB_MAX_GPUS
275 int "Maximum number of GPUs"
279 Reserves space in the kernel to maintain resource locking for
280 multiple GPUS. The overhead for each GPU is very small.
282 source "drivers/pci/hotplug/Kconfig"
283 source "drivers/pci/controller/Kconfig"
284 source "drivers/pci/endpoint/Kconfig"
285 source "drivers/pci/switch/Kconfig"