drivers/nvmem/rockchip-otp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Rockchip OTP Driver
   4  *
   5  * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
   6  * Author: Finley Xiao <finley.xiao@rock-chips.com>
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/device.h>
  12 #include <linux/io.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/module.h>
  15 #include <linux/nvmem-provider.h>
  16 #include <linux/reset.h>
  17 #include <linux/slab.h>
  18 #include <linux/of.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/platform_device.h>
  21
  22 /* OTP Register Offsets */
  23 #define OTPC_SBPI_CTRL                  0x0020
  24 #define OTPC_SBPI_CMD_VALID_PRE         0x0024
  25 #define OTPC_SBPI_CS_VALID_PRE          0x0028
  26 #define OTPC_SBPI_STATUS                0x002C
  27 #define OTPC_USER_CTRL                  0x0100
  28 #define OTPC_USER_ADDR                  0x0104
  29 #define OTPC_USER_ENABLE                0x0108
  30 #define OTPC_USER_Q                     0x0124
  31 #define OTPC_INT_STATUS                 0x0304
  32 #define OTPC_SBPI_CMD0_OFFSET           0x1000
  33 #define OTPC_SBPI_CMD1_OFFSET           0x1004
  34
  35 /* OTP Register bits and masks */
  36 #define OTPC_USER_ADDR_MASK             GENMASK(31, 16)
  37 #define OTPC_USE_USER                   BIT(0)
  38 #define OTPC_USE_USER_MASK              GENMASK(16, 16)
  39 #define OTPC_USER_FSM_ENABLE            BIT(0)
  40 #define OTPC_USER_FSM_ENABLE_MASK       GENMASK(16, 16)
  41 #define OTPC_SBPI_DONE                  BIT(1)
  42 #define OTPC_USER_DONE                  BIT(2)
  43
  44 #define SBPI_DAP_ADDR                   0x02
  45 #define SBPI_DAP_ADDR_SHIFT             8
  46 #define SBPI_DAP_ADDR_MASK              GENMASK(31, 24)
  47 #define SBPI_CMD_VALID_MASK             GENMASK(31, 16)
  48 #define SBPI_DAP_CMD_WRF                0xC0
  49 #define SBPI_DAP_REG_ECC                0x3A
  50 #define SBPI_ECC_ENABLE                 0x00
  51 #define SBPI_ECC_DISABLE                0x09
  52 #define SBPI_ENABLE                     BIT(0)
  53 #define SBPI_ENABLE_MASK                GENMASK(16, 16)
  54
  55 #define OTPC_TIMEOUT                    10000
  56
  57 struct rockchip_data {
  58         int size;
  59         const char * const *clks;
  60         int num_clks;
  61         nvmem_reg_read_t reg_read;
  62 };
  63
  64 struct rockchip_otp {
  65         struct device *dev;
  66         void __iomem *base;
  67         struct clk_bulk_data *clks;
  68         struct reset_control *rst;
  69         const struct rockchip_data *data;
  70 };
  71
  72 static int rockchip_otp_reset(struct rockchip_otp *otp)
  73 {
  74         int ret;
  75
  76         ret = reset_control_assert(otp->rst);
  77         if (ret) {
  78                 dev_err(otp->dev, "failed to assert otp phy %d\n", ret);
  79                 return ret;
  80         }
  81
  82         udelay(2);
  83
  84         ret = reset_control_deassert(otp->rst);
  85         if (ret) {
  86                 dev_err(otp->dev, "failed to deassert otp phy %d\n", ret);
  87                 return ret;
  88         }
  89
  90         return 0;
  91 }
  92
  93 static int rockchip_otp_wait_status(struct rockchip_otp *otp,
  94                                     unsigned int reg, u32 flag)
  95 {
  96         u32 status = 0;
  97         int ret;
  98
  99         ret = readl_poll_timeout_atomic(otp->base + reg, status,
 100                                         (status & flag), 1, OTPC_TIMEOUT);
 101         if (ret)
 102                 return ret;
 103
 104         /* clean int status */
 105         writel(flag, otp->base + reg);
 106
 107         return 0;
 108 }
 109
 110 static int rockchip_otp_ecc_enable(struct rockchip_otp *otp, bool enable)
 111 {
 112         int ret = 0;
 113
 114         writel(SBPI_DAP_ADDR_MASK | (SBPI_DAP_ADDR << SBPI_DAP_ADDR_SHIFT),
 115                otp->base + OTPC_SBPI_CTRL);
 116
 117         writel(SBPI_CMD_VALID_MASK | 0x1, otp->base + OTPC_SBPI_CMD_VALID_PRE);
 118         writel(SBPI_DAP_CMD_WRF | SBPI_DAP_REG_ECC,
 119                otp->base + OTPC_SBPI_CMD0_OFFSET);
 120         if (enable)
 121                 writel(SBPI_ECC_ENABLE, otp->base + OTPC_SBPI_CMD1_OFFSET);
 122         else
 123                 writel(SBPI_ECC_DISABLE, otp->base + OTPC_SBPI_CMD1_OFFSET);
 124
 125         writel(SBPI_ENABLE_MASK | SBPI_ENABLE, otp->base + OTPC_SBPI_CTRL);
 126
 127         ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_SBPI_DONE);
 128         if (ret < 0)
 129                 dev_err(otp->dev, "timeout during ecc_enable\n");
 130
 131         return ret;
 132 }
 133
 134 static int px30_otp_read(void *context, unsigned int offset,
 135                          void *val, size_t bytes)
 136 {
 137         struct rockchip_otp *otp = context;
 138         u8 *buf = val;
 139         int ret;
 140
 141         ret = rockchip_otp_reset(otp);
 142         if (ret) {
 143                 dev_err(otp->dev, "failed to reset otp phy\n");
 144                 return ret;
 145         }
 146
 147         ret = rockchip_otp_ecc_enable(otp, false);
 148         if (ret < 0) {
 149                 dev_err(otp->dev, "rockchip_otp_ecc_enable err\n");
 150                 return ret;
 151         }
 152
 153         writel(OTPC_USE_USER | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
 154         udelay(5);
 155         while (bytes--) {
 156                 writel(offset++ | OTPC_USER_ADDR_MASK,
 157                        otp->base + OTPC_USER_ADDR);
 158                 writel(OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK,
 159                        otp->base + OTPC_USER_ENABLE);
 160                 ret = rockchip_otp_wait_status(otp, OTPC_INT_STATUS, OTPC_USER_DONE);
 161                 if (ret < 0) {
 162                         dev_err(otp->dev, "timeout during read setup\n");
 163                         goto read_end;
 164                 }
 165                 *buf++ = readb(otp->base + OTPC_USER_Q);
 166         }
 167
 168 read_end:
 169         writel(0x0 | OTPC_USE_USER_MASK, otp->base + OTPC_USER_CTRL);
 170
 171         return ret;
 172 }
 173
 174 static int rockchip_otp_read(void *context, unsigned int offset,
 175                              void *val, size_t bytes)
 176 {
 177         struct rockchip_otp *otp = context;
 178         int ret;
 179
 180         if (!otp->data || !otp->data->reg_read)
 181                 return -EINVAL;
 182
 183         ret = clk_bulk_prepare_enable(otp->data->num_clks, otp->clks);
 184         if (ret < 0) {
 185                 dev_err(otp->dev, "failed to prepare/enable clks\n");
 186                 return ret;
 187         }
 188
 189         ret = otp->data->reg_read(context, offset, val, bytes);
 190
 191         clk_bulk_disable_unprepare(otp->data->num_clks, otp->clks);
 192
 193         return ret;
 194 }
 195
 196 static struct nvmem_config otp_config = {
 197         .name = "rockchip-otp",
 198         .owner = THIS_MODULE,
 199         .read_only = true,
 200         .stride = 1,
 201         .word_size = 1,
 202         .reg_read = rockchip_otp_read,
 203 };
 204
 205 static const char * const px30_otp_clocks[] = {
 206         "otp", "apb_pclk", "phy",
 207 };
 208
 209 static const struct rockchip_data px30_data = {
 210         .size = 0x40,
 211         .clks = px30_otp_clocks,
 212         .num_clks = ARRAY_SIZE(px30_otp_clocks),
 213         .reg_read = px30_otp_read,
 214 };
 215
 216 static const struct of_device_id rockchip_otp_match[] = {
 217         {
 218                 .compatible = "rockchip,px30-otp",
 219                 .data = (void *)&px30_data,
 220         },
 221         {
 222                 .compatible = "rockchip,rk3308-otp",
 223                 .data = (void *)&px30_data,
 224         },
 225         { /* sentinel */ },
 226 };
 227 MODULE_DEVICE_TABLE(of, rockchip_otp_match);
 228
 229 static int rockchip_otp_probe(struct platform_device *pdev)
 230 {
 231         struct device *dev = &pdev->dev;
 232         struct rockchip_otp *otp;
 233         const struct rockchip_data *data;
 234         struct nvmem_device *nvmem;
 235         int ret, i;
 236
 237         data = of_device_get_match_data(dev);
 238         if (!data)
 239                 return dev_err_probe(dev, -EINVAL, "failed to get match data\n");
 240
 241         otp = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_otp),
 242                            GFP_KERNEL);
 243         if (!otp)
 244                 return -ENOMEM;
 245
 246         otp->data = data;
 247         otp->dev = dev;
 248         otp->base = devm_platform_ioremap_resource(pdev, 0);
 249         if (IS_ERR(otp->base))
 250                 return dev_err_probe(dev, PTR_ERR(otp->base),
 251                                      "failed to ioremap resource\n");
 252
 253         otp->clks = devm_kcalloc(dev, data->num_clks, sizeof(*otp->clks),
 254                                  GFP_KERNEL);
 255         if (!otp->clks)
 256                 return -ENOMEM;
 257
 258         for (i = 0; i < data->num_clks; ++i)
 259                 otp->clks[i].id = data->clks[i];
 260
 261         ret = devm_clk_bulk_get(dev, data->num_clks, otp->clks);
 262         if (ret)
 263                 return dev_err_probe(dev, ret, "failed to get clocks\n");
 264
 265         otp->rst = devm_reset_control_array_get_exclusive(dev);
 266         if (IS_ERR(otp->rst))
 267                 return dev_err_probe(dev, PTR_ERR(otp->rst),
 268                                      "failed to get resets\n");
 269
 270         otp_config.size = data->size;
 271         otp_config.priv = otp;
 272         otp_config.dev = dev;
 273
 274         nvmem = devm_nvmem_register(dev, &otp_config);
 275         if (IS_ERR(nvmem))
 276                 return dev_err_probe(dev, PTR_ERR(nvmem),
 277                                      "failed to register nvmem device\n");
 278         return 0;
 279 }
 280
 281 static struct platform_driver rockchip_otp_driver = {
 282         .probe = rockchip_otp_probe,
 283         .driver = {
 284                 .name = "rockchip-otp",
 285                 .of_match_table = rockchip_otp_match,
 286         },
 287 };
 288
 289 module_platform_driver(rockchip_otp_driver);
 290 MODULE_DESCRIPTION("Rockchip OTP driver");
 291 MODULE_LICENSE("GPL v2");