drivers/nvme/host/pci.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * NVM Express device driver
   4  * Copyright (c) 2011-2014, Intel Corporation.
   5  */
   6
   7 #include <linux/acpi.h>
   8 #include <linux/aer.h>
   9 #include <linux/async.h>
  10 #include <linux/blkdev.h>
  11 #include <linux/blk-mq.h>
  12 #include <linux/blk-mq-pci.h>
  13 #include <linux/dmi.h>
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/io.h>
  17 #include <linux/mm.h>
  18 #include <linux/module.h>
  19 #include <linux/mutex.h>
  20 #include <linux/once.h>
  21 #include <linux/pci.h>
  22 #include <linux/suspend.h>
  23 #include <linux/t10-pi.h>
  24 #include <linux/types.h>
  25 #include <linux/io-64-nonatomic-lo-hi.h>
  26 #include <linux/io-64-nonatomic-hi-lo.h>
  27 #include <linux/sed-opal.h>
  28 #include <linux/pci-p2pdma.h>
  29
  30 #include "trace.h"
  31 #include "nvme.h"
  32
  33 #define SQ_SIZE(q)      ((q)->q_depth << (q)->sqes)
  34 #define CQ_SIZE(q)      ((q)->q_depth * sizeof(struct nvme_completion))
  35
  36 #define SGES_PER_PAGE   (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
  37
  38 /*
  39  * These can be higher, but we need to ensure that any command doesn't
  40  * require an sg allocation that needs more than a page of data.
  41  */
  42 #define NVME_MAX_KB_SZ  4096
  43 #define NVME_MAX_SEGS   127
  44
  45 static int use_threaded_interrupts;
  46 module_param(use_threaded_interrupts, int, 0);
  47
  48 static bool use_cmb_sqes = true;
  49 module_param(use_cmb_sqes, bool, 0444);
  50 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  51
  52 static unsigned int max_host_mem_size_mb = 128;
  53 module_param(max_host_mem_size_mb, uint, 0444);
  54 MODULE_PARM_DESC(max_host_mem_size_mb,
  55         "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
  56
  57 static unsigned int sgl_threshold = SZ_32K;
  58 module_param(sgl_threshold, uint, 0644);
  59 MODULE_PARM_DESC(sgl_threshold,
  60                 "Use SGLs when average request segment size is larger or equal to "
  61                 "this size. Use 0 to disable SGLs.");
  62
  63 #define NVME_PCI_MIN_QUEUE_SIZE 2
  64 #define NVME_PCI_MAX_QUEUE_SIZE 4095
  65 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
  66 static const struct kernel_param_ops io_queue_depth_ops = {
  67         .set = io_queue_depth_set,
  68         .get = param_get_uint,
  69 };
  70
  71 static unsigned int io_queue_depth = 1024;
  72 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
  73 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
  74
  75 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
  76 {
  77         unsigned int n;
  78         int ret;
  79
  80         ret = kstrtouint(val, 10, &n);
  81         if (ret != 0 || n > num_possible_cpus())
  82                 return -EINVAL;
  83         return param_set_uint(val, kp);
  84 }
  85
  86 static const struct kernel_param_ops io_queue_count_ops = {
  87         .set = io_queue_count_set,
  88         .get = param_get_uint,
  89 };
  90
  91 static unsigned int write_queues;
  92 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
  93 MODULE_PARM_DESC(write_queues,
  94         "Number of queues to use for writes. If not set, reads and writes "
  95         "will share a queue set.");
  96
  97 static unsigned int poll_queues;
  98 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
  99 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
 100
 101 static bool noacpi;
 102 module_param(noacpi, bool, 0444);
 103 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
 104
 105 struct nvme_dev;
 106 struct nvme_queue;
 107
 108 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
 109 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
 110
 111 /*
 112  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
 113  */
 114 struct nvme_dev {
 115         struct nvme_queue *queues;
 116         struct blk_mq_tag_set tagset;
 117         struct blk_mq_tag_set admin_tagset;
 118         u32 __iomem *dbs;
 119         struct device *dev;
 120         struct dma_pool *prp_page_pool;
 121         struct dma_pool *prp_small_pool;
 122         unsigned online_queues;
 123         unsigned max_qid;
 124         unsigned io_queues[HCTX_MAX_TYPES];
 125         unsigned int num_vecs;
 126         u32 q_depth;
 127         int io_sqes;
 128         u32 db_stride;
 129         void __iomem *bar;
 130         unsigned long bar_mapped_size;
 131         struct work_struct remove_work;
 132         struct mutex shutdown_lock;
 133         bool subsystem;
 134         u64 cmb_size;
 135         bool cmb_use_sqes;
 136         u32 cmbsz;
 137         u32 cmbloc;
 138         struct nvme_ctrl ctrl;
 139         u32 last_ps;
 140         bool hmb;
 141
 142         mempool_t *iod_mempool;
 143
 144         /* shadow doorbell buffer support: */
 145         u32 *dbbuf_dbs;
 146         dma_addr_t dbbuf_dbs_dma_addr;
 147         u32 *dbbuf_eis;
 148         dma_addr_t dbbuf_eis_dma_addr;
 149
 150         /* host memory buffer support: */
 151         u64 host_mem_size;
 152         u32 nr_host_mem_descs;
 153         dma_addr_t host_mem_descs_dma;
 154         struct nvme_host_mem_buf_desc *host_mem_descs;
 155         void **host_mem_desc_bufs;
 156         unsigned int nr_allocated_queues;
 157         unsigned int nr_write_queues;
 158         unsigned int nr_poll_queues;
 159
 160         bool attrs_added;
 161 };
 162
 163 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
 164 {
 165         return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
 166                         NVME_PCI_MAX_QUEUE_SIZE);
 167 }
 168
 169 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
 170 {
 171         return qid * 2 * stride;
 172 }
 173
 174 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
 175 {
 176         return (qid * 2 + 1) * stride;
 177 }
 178
 179 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 180 {
 181         return container_of(ctrl, struct nvme_dev, ctrl);
 182 }
 183
 184 /*
 185  * An NVM Express queue.  Each device has at least two (one for admin
 186  * commands and one for I/O commands).
 187  */
 188 struct nvme_queue {
 189         struct nvme_dev *dev;
 190         spinlock_t sq_lock;
 191         void *sq_cmds;
 192          /* only used for poll queues: */
 193         spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
 194         struct nvme_completion *cqes;
 195         dma_addr_t sq_dma_addr;
 196         dma_addr_t cq_dma_addr;
 197         u32 __iomem *q_db;
 198         u32 q_depth;
 199         u16 cq_vector;
 200         u16 sq_tail;
 201         u16 last_sq_tail;
 202         u16 cq_head;
 203         u16 qid;
 204         u8 cq_phase;
 205         u8 sqes;
 206         unsigned long flags;
 207 #define NVMEQ_ENABLED           0
 208 #define NVMEQ_SQ_CMB            1
 209 #define NVMEQ_DELETE_ERROR      2
 210 #define NVMEQ_POLLED            3
 211         u32 *dbbuf_sq_db;
 212         u32 *dbbuf_cq_db;
 213         u32 *dbbuf_sq_ei;
 214         u32 *dbbuf_cq_ei;
 215         struct completion delete_done;
 216 };
 217
 218 /*
 219  * The nvme_iod describes the data in an I/O.
 220  *
 221  * The sg pointer contains the list of PRP/SGL chunk allocations in addition
 222  * to the actual struct scatterlist.
 223  */
 224 struct nvme_iod {
 225         struct nvme_request req;
 226         struct nvme_command cmd;
 227         struct nvme_queue *nvmeq;
 228         bool use_sgl;
 229         int aborted;
 230         int npages;             /* In the PRP list. 0 means small pool in use */
 231         int nents;              /* Used in scatterlist */
 232         dma_addr_t first_dma;
 233         unsigned int dma_len;   /* length of single DMA segment mapping */
 234         dma_addr_t meta_dma;
 235         struct scatterlist *sg;
 236 };
 237
 238 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
 239 {
 240         return dev->nr_allocated_queues * 8 * dev->db_stride;
 241 }
 242
 243 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
 244 {
 245         unsigned int mem_size = nvme_dbbuf_size(dev);
 246
 247         if (dev->dbbuf_dbs)
 248                 return 0;
 249
 250         dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
 251                                             &dev->dbbuf_dbs_dma_addr,
 252                                             GFP_KERNEL);
 253         if (!dev->dbbuf_dbs)
 254                 return -ENOMEM;
 255         dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
 256                                             &dev->dbbuf_eis_dma_addr,
 257                                             GFP_KERNEL);
 258         if (!dev->dbbuf_eis) {
 259                 dma_free_coherent(dev->dev, mem_size,
 260                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 261                 dev->dbbuf_dbs = NULL;
 262                 return -ENOMEM;
 263         }
 264
 265         return 0;
 266 }
 267
 268 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
 269 {
 270         unsigned int mem_size = nvme_dbbuf_size(dev);
 271
 272         if (dev->dbbuf_dbs) {
 273                 dma_free_coherent(dev->dev, mem_size,
 274                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 275                 dev->dbbuf_dbs = NULL;
 276         }
 277         if (dev->dbbuf_eis) {
 278                 dma_free_coherent(dev->dev, mem_size,
 279                                   dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
 280                 dev->dbbuf_eis = NULL;
 281         }
 282 }
 283
 284 static void nvme_dbbuf_init(struct nvme_dev *dev,
 285                             struct nvme_queue *nvmeq, int qid)
 286 {
 287         if (!dev->dbbuf_dbs || !qid)
 288                 return;
 289
 290         nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
 291         nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
 292         nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
 293         nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
 294 }
 295
 296 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
 297 {
 298         if (!nvmeq->qid)
 299                 return;
 300
 301         nvmeq->dbbuf_sq_db = NULL;
 302         nvmeq->dbbuf_cq_db = NULL;
 303         nvmeq->dbbuf_sq_ei = NULL;
 304         nvmeq->dbbuf_cq_ei = NULL;
 305 }
 306
 307 static void nvme_dbbuf_set(struct nvme_dev *dev)
 308 {
 309         struct nvme_command c = { };
 310         unsigned int i;
 311
 312         if (!dev->dbbuf_dbs)
 313                 return;
 314
 315         c.dbbuf.opcode = nvme_admin_dbbuf;
 316         c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
 317         c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
 318
 319         if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
 320                 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
 321                 /* Free memory and continue on */
 322                 nvme_dbbuf_dma_free(dev);
 323
 324                 for (i = 1; i <= dev->online_queues; i++)
 325                         nvme_dbbuf_free(&dev->queues[i]);
 326         }
 327 }
 328
 329 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
 330 {
 331         return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
 332 }
 333
 334 /* Update dbbuf and return true if an MMIO is required */
 335 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
 336                                               volatile u32 *dbbuf_ei)
 337 {
 338         if (dbbuf_db) {
 339                 u16 old_value;
 340
 341                 /*
 342                  * Ensure that the queue is written before updating
 343                  * the doorbell in memory
 344                  */
 345                 wmb();
 346
 347                 old_value = *dbbuf_db;
 348                 *dbbuf_db = value;
 349
 350                 /*
 351                  * Ensure that the doorbell is updated before reading the event
 352                  * index from memory.  The controller needs to provide similar
 353                  * ordering to ensure the envent index is updated before reading
 354                  * the doorbell.
 355                  */
 356                 mb();
 357
 358                 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
 359                         return false;
 360         }
 361
 362         return true;
 363 }
 364
 365 /*
 366  * Will slightly overestimate the number of pages needed.  This is OK
 367  * as it only leads to a small amount of wasted memory for the lifetime of
 368  * the I/O.
 369  */
 370 static int nvme_pci_npages_prp(void)
 371 {
 372         unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
 373                                       NVME_CTRL_PAGE_SIZE);
 374         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 375 }
 376
 377 /*
 378  * Calculates the number of pages needed for the SGL segments. For example a 4k
 379  * page can accommodate 256 SGL descriptors.
 380  */
 381 static int nvme_pci_npages_sgl(void)
 382 {
 383         return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
 384                         PAGE_SIZE);
 385 }
 386
 387 static size_t nvme_pci_iod_alloc_size(void)
 388 {
 389         size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
 390
 391         return sizeof(__le64 *) * npages +
 392                 sizeof(struct scatterlist) * NVME_MAX_SEGS;
 393 }
 394
 395 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 396                                 unsigned int hctx_idx)
 397 {
 398         struct nvme_dev *dev = data;
 399         struct nvme_queue *nvmeq = &dev->queues[0];
 400
 401         WARN_ON(hctx_idx != 0);
 402         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 403
 404         hctx->driver_data = nvmeq;
 405         return 0;
 406 }
 407
 408 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 409                           unsigned int hctx_idx)
 410 {
 411         struct nvme_dev *dev = data;
 412         struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
 413
 414         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 415         hctx->driver_data = nvmeq;
 416         return 0;
 417 }
 418
 419 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
 420                 unsigned int hctx_idx, unsigned int numa_node)
 421 {
 422         struct nvme_dev *dev = set->driver_data;
 423         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 424         int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
 425         struct nvme_queue *nvmeq = &dev->queues[queue_idx];
 426
 427         BUG_ON(!nvmeq);
 428         iod->nvmeq = nvmeq;
 429
 430         nvme_req(req)->ctrl = &dev->ctrl;
 431         nvme_req(req)->cmd = &iod->cmd;
 432         return 0;
 433 }
 434
 435 static int queue_irq_offset(struct nvme_dev *dev)
 436 {
 437         /* if we have more than 1 vec, admin queue offsets us by 1 */
 438         if (dev->num_vecs > 1)
 439                 return 1;
 440
 441         return 0;
 442 }
 443
 444 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 445 {
 446         struct nvme_dev *dev = set->driver_data;
 447         int i, qoff, offset;
 448
 449         offset = queue_irq_offset(dev);
 450         for (i = 0, qoff = 0; i < set->nr_maps; i++) {
 451                 struct blk_mq_queue_map *map = &set->map[i];
 452
 453                 map->nr_queues = dev->io_queues[i];
 454                 if (!map->nr_queues) {
 455                         BUG_ON(i == HCTX_TYPE_DEFAULT);
 456                         continue;
 457                 }
 458
 459                 /*
 460                  * The poll queue(s) doesn't have an IRQ (and hence IRQ
 461                  * affinity), so use the regular blk-mq cpu mapping
 462                  */
 463                 map->queue_offset = qoff;
 464                 if (i != HCTX_TYPE_POLL && offset)
 465                         blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
 466                 else
 467                         blk_mq_map_queues(map);
 468                 qoff += map->nr_queues;
 469                 offset += map->nr_queues;
 470         }
 471
 472         return 0;
 473 }
 474
 475 /*
 476  * Write sq tail if we are asked to, or if the next command would wrap.
 477  */
 478 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
 479 {
 480         if (!write_sq) {
 481                 u16 next_tail = nvmeq->sq_tail + 1;
 482
 483                 if (next_tail == nvmeq->q_depth)
 484                         next_tail = 0;
 485                 if (next_tail != nvmeq->last_sq_tail)
 486                         return;
 487         }
 488
 489         if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
 490                         nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
 491                 writel(nvmeq->sq_tail, nvmeq->q_db);
 492         nvmeq->last_sq_tail = nvmeq->sq_tail;
 493 }
 494
 495 /**
 496  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 497  * @nvmeq: The queue to use
 498  * @cmd: The command to send
 499  * @write_sq: whether to write to the SQ doorbell
 500  */
 501 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
 502                             bool write_sq)
 503 {
 504         spin_lock(&nvmeq->sq_lock);
 505         memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
 506                cmd, sizeof(*cmd));
 507         if (++nvmeq->sq_tail == nvmeq->q_depth)
 508                 nvmeq->sq_tail = 0;
 509         nvme_write_sq_db(nvmeq, write_sq);
 510         spin_unlock(&nvmeq->sq_lock);
 511 }
 512
 513 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
 514 {
 515         struct nvme_queue *nvmeq = hctx->driver_data;
 516
 517         spin_lock(&nvmeq->sq_lock);
 518         if (nvmeq->sq_tail != nvmeq->last_sq_tail)
 519                 nvme_write_sq_db(nvmeq, true);
 520         spin_unlock(&nvmeq->sq_lock);
 521 }
 522
 523 static void **nvme_pci_iod_list(struct request *req)
 524 {
 525         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 526         return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
 527 }
 528
 529 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
 530 {
 531         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 532         int nseg = blk_rq_nr_phys_segments(req);
 533         unsigned int avg_seg_size;
 534
 535         avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
 536
 537         if (!nvme_ctrl_sgl_supported(&dev->ctrl))
 538                 return false;
 539         if (!iod->nvmeq->qid)
 540                 return false;
 541         if (!sgl_threshold || avg_seg_size < sgl_threshold)
 542                 return false;
 543         return true;
 544 }
 545
 546 static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
 547 {
 548         const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
 549         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 550         dma_addr_t dma_addr = iod->first_dma;
 551         int i;
 552
 553         for (i = 0; i < iod->npages; i++) {
 554                 __le64 *prp_list = nvme_pci_iod_list(req)[i];
 555                 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
 556
 557                 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
 558                 dma_addr = next_dma_addr;
 559         }
 560 }
 561
 562 static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
 563 {
 564         const int last_sg = SGES_PER_PAGE - 1;
 565         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 566         dma_addr_t dma_addr = iod->first_dma;
 567         int i;
 568
 569         for (i = 0; i < iod->npages; i++) {
 570                 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
 571                 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
 572
 573                 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
 574                 dma_addr = next_dma_addr;
 575         }
 576 }
 577
 578 static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
 579 {
 580         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 581
 582         if (is_pci_p2pdma_page(sg_page(iod->sg)))
 583                 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
 584                                     rq_dma_dir(req));
 585         else
 586                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
 587 }
 588
 589 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 590 {
 591         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 592
 593         if (iod->dma_len) {
 594                 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
 595                                rq_dma_dir(req));
 596                 return;
 597         }
 598
 599         WARN_ON_ONCE(!iod->nents);
 600
 601         nvme_unmap_sg(dev, req);
 602         if (iod->npages == 0)
 603                 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
 604                               iod->first_dma);
 605         else if (iod->use_sgl)
 606                 nvme_free_sgls(dev, req);
 607         else
 608                 nvme_free_prps(dev, req);
 609         mempool_free(iod->sg, dev->iod_mempool);
 610 }
 611
 612 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
 613 {
 614         int i;
 615         struct scatterlist *sg;
 616
 617         for_each_sg(sgl, sg, nents, i) {
 618                 dma_addr_t phys = sg_phys(sg);
 619                 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
 620                         "dma_address:%pad dma_length:%d\n",
 621                         i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
 622                         sg_dma_len(sg));
 623         }
 624 }
 625
 626 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
 627                 struct request *req, struct nvme_rw_command *cmnd)
 628 {
 629         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 630         struct dma_pool *pool;
 631         int length = blk_rq_payload_bytes(req);
 632         struct scatterlist *sg = iod->sg;
 633         int dma_len = sg_dma_len(sg);
 634         u64 dma_addr = sg_dma_address(sg);
 635         int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
 636         __le64 *prp_list;
 637         void **list = nvme_pci_iod_list(req);
 638         dma_addr_t prp_dma;
 639         int nprps, i;
 640
 641         length -= (NVME_CTRL_PAGE_SIZE - offset);
 642         if (length <= 0) {
 643                 iod->first_dma = 0;
 644                 goto done;
 645         }
 646
 647         dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
 648         if (dma_len) {
 649                 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
 650         } else {
 651                 sg = sg_next(sg);
 652                 dma_addr = sg_dma_address(sg);
 653                 dma_len = sg_dma_len(sg);
 654         }
 655
 656         if (length <= NVME_CTRL_PAGE_SIZE) {
 657                 iod->first_dma = dma_addr;
 658                 goto done;
 659         }
 660
 661         nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
 662         if (nprps <= (256 / 8)) {
 663                 pool = dev->prp_small_pool;
 664                 iod->npages = 0;
 665         } else {
 666                 pool = dev->prp_page_pool;
 667                 iod->npages = 1;
 668         }
 669
 670         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 671         if (!prp_list) {
 672                 iod->first_dma = dma_addr;
 673                 iod->npages = -1;
 674                 return BLK_STS_RESOURCE;
 675         }
 676         list[0] = prp_list;
 677         iod->first_dma = prp_dma;
 678         i = 0;
 679         for (;;) {
 680                 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
 681                         __le64 *old_prp_list = prp_list;
 682                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 683                         if (!prp_list)
 684                                 goto free_prps;
 685                         list[iod->npages++] = prp_list;
 686                         prp_list[0] = old_prp_list[i - 1];
 687                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 688                         i = 1;
 689                 }
 690                 prp_list[i++] = cpu_to_le64(dma_addr);
 691                 dma_len -= NVME_CTRL_PAGE_SIZE;
 692                 dma_addr += NVME_CTRL_PAGE_SIZE;
 693                 length -= NVME_CTRL_PAGE_SIZE;
 694                 if (length <= 0)
 695                         break;
 696                 if (dma_len > 0)
 697                         continue;
 698                 if (unlikely(dma_len < 0))
 699                         goto bad_sgl;
 700                 sg = sg_next(sg);
 701                 dma_addr = sg_dma_address(sg);
 702                 dma_len = sg_dma_len(sg);
 703         }
 704 done:
 705         cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 706         cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
 707         return BLK_STS_OK;
 708 free_prps:
 709         nvme_free_prps(dev, req);
 710         return BLK_STS_RESOURCE;
 711 bad_sgl:
 712         WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
 713                         "Invalid SGL for payload:%d nents:%d\n",
 714                         blk_rq_payload_bytes(req), iod->nents);
 715         return BLK_STS_IOERR;
 716 }
 717
 718 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
 719                 struct scatterlist *sg)
 720 {
 721         sge->addr = cpu_to_le64(sg_dma_address(sg));
 722         sge->length = cpu_to_le32(sg_dma_len(sg));
 723         sge->type = NVME_SGL_FMT_DATA_DESC << 4;
 724 }
 725
 726 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
 727                 dma_addr_t dma_addr, int entries)
 728 {
 729         sge->addr = cpu_to_le64(dma_addr);
 730         if (entries < SGES_PER_PAGE) {
 731                 sge->length = cpu_to_le32(entries * sizeof(*sge));
 732                 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
 733         } else {
 734                 sge->length = cpu_to_le32(PAGE_SIZE);
 735                 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
 736         }
 737 }
 738
 739 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
 740                 struct request *req, struct nvme_rw_command *cmd, int entries)
 741 {
 742         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 743         struct dma_pool *pool;
 744         struct nvme_sgl_desc *sg_list;
 745         struct scatterlist *sg = iod->sg;
 746         dma_addr_t sgl_dma;
 747         int i = 0;
 748
 749         /* setting the transfer type as SGL */
 750         cmd->flags = NVME_CMD_SGL_METABUF;
 751
 752         if (entries == 1) {
 753                 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
 754                 return BLK_STS_OK;
 755         }
 756
 757         if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
 758                 pool = dev->prp_small_pool;
 759                 iod->npages = 0;
 760         } else {
 761                 pool = dev->prp_page_pool;
 762                 iod->npages = 1;
 763         }
 764
 765         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 766         if (!sg_list) {
 767                 iod->npages = -1;
 768                 return BLK_STS_RESOURCE;
 769         }
 770
 771         nvme_pci_iod_list(req)[0] = sg_list;
 772         iod->first_dma = sgl_dma;
 773
 774         nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
 775
 776         do {
 777                 if (i == SGES_PER_PAGE) {
 778                         struct nvme_sgl_desc *old_sg_desc = sg_list;
 779                         struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
 780
 781                         sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 782                         if (!sg_list)
 783                                 goto free_sgls;
 784
 785                         i = 0;
 786                         nvme_pci_iod_list(req)[iod->npages++] = sg_list;
 787                         sg_list[i++] = *link;
 788                         nvme_pci_sgl_set_seg(link, sgl_dma, entries);
 789                 }
 790
 791                 nvme_pci_sgl_set_data(&sg_list[i++], sg);
 792                 sg = sg_next(sg);
 793         } while (--entries > 0);
 794
 795         return BLK_STS_OK;
 796 free_sgls:
 797         nvme_free_sgls(dev, req);
 798         return BLK_STS_RESOURCE;
 799 }
 800
 801 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
 802                 struct request *req, struct nvme_rw_command *cmnd,
 803                 struct bio_vec *bv)
 804 {
 805         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 806         unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
 807         unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
 808
 809         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 810         if (dma_mapping_error(dev->dev, iod->first_dma))
 811                 return BLK_STS_RESOURCE;
 812         iod->dma_len = bv->bv_len;
 813
 814         cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
 815         if (bv->bv_len > first_prp_len)
 816                 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
 817         return BLK_STS_OK;
 818 }
 819
 820 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
 821                 struct request *req, struct nvme_rw_command *cmnd,
 822                 struct bio_vec *bv)
 823 {
 824         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 825
 826         iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 827         if (dma_mapping_error(dev->dev, iod->first_dma))
 828                 return BLK_STS_RESOURCE;
 829         iod->dma_len = bv->bv_len;
 830
 831         cmnd->flags = NVME_CMD_SGL_METABUF;
 832         cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
 833         cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
 834         cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
 835         return BLK_STS_OK;
 836 }
 837
 838 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
 839                 struct nvme_command *cmnd)
 840 {
 841         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 842         blk_status_t ret = BLK_STS_RESOURCE;
 843         int nr_mapped;
 844
 845         if (blk_rq_nr_phys_segments(req) == 1) {
 846                 struct bio_vec bv = req_bvec(req);
 847
 848                 if (!is_pci_p2pdma_page(bv.bv_page)) {
 849                         if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
 850                                 return nvme_setup_prp_simple(dev, req,
 851                                                              &cmnd->rw, &bv);
 852
 853                         if (iod->nvmeq->qid && sgl_threshold &&
 854                             nvme_ctrl_sgl_supported(&dev->ctrl))
 855                                 return nvme_setup_sgl_simple(dev, req,
 856                                                              &cmnd->rw, &bv);
 857                 }
 858         }
 859
 860         iod->dma_len = 0;
 861         iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
 862         if (!iod->sg)
 863                 return BLK_STS_RESOURCE;
 864         sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
 865         iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
 866         if (!iod->nents)
 867                 goto out_free_sg;
 868
 869         if (is_pci_p2pdma_page(sg_page(iod->sg)))
 870                 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
 871                                 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
 872         else
 873                 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
 874                                              rq_dma_dir(req), DMA_ATTR_NO_WARN);
 875         if (!nr_mapped)
 876                 goto out_free_sg;
 877
 878         iod->use_sgl = nvme_pci_use_sgls(dev, req);
 879         if (iod->use_sgl)
 880                 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
 881         else
 882                 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
 883         if (ret != BLK_STS_OK)
 884                 goto out_unmap_sg;
 885         return BLK_STS_OK;
 886
 887 out_unmap_sg:
 888         nvme_unmap_sg(dev, req);
 889 out_free_sg:
 890         mempool_free(iod->sg, dev->iod_mempool);
 891         return ret;
 892 }
 893
 894 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
 895                 struct nvme_command *cmnd)
 896 {
 897         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 898
 899         iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
 900                         rq_dma_dir(req), 0);
 901         if (dma_mapping_error(dev->dev, iod->meta_dma))
 902                 return BLK_STS_IOERR;
 903         cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
 904         return BLK_STS_OK;
 905 }
 906
 907 /*
 908  * NOTE: ns is NULL when called on the admin queue.
 909  */
 910 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 911                          const struct blk_mq_queue_data *bd)
 912 {
 913         struct nvme_ns *ns = hctx->queue->queuedata;
 914         struct nvme_queue *nvmeq = hctx->driver_data;
 915         struct nvme_dev *dev = nvmeq->dev;
 916         struct request *req = bd->rq;
 917         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 918         struct nvme_command *cmnd = &iod->cmd;
 919         blk_status_t ret;
 920
 921         iod->aborted = 0;
 922         iod->npages = -1;
 923         iod->nents = 0;
 924
 925         /*
 926          * We should not need to do this, but we're still using this to
 927          * ensure we can drain requests on a dying queue.
 928          */
 929         if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
 930                 return BLK_STS_IOERR;
 931
 932         if (!nvme_check_ready(&dev->ctrl, req, true))
 933                 return nvme_fail_nonready_command(&dev->ctrl, req);
 934
 935         ret = nvme_setup_cmd(ns, req);
 936         if (ret)
 937                 return ret;
 938
 939         if (blk_rq_nr_phys_segments(req)) {
 940                 ret = nvme_map_data(dev, req, cmnd);
 941                 if (ret)
 942                         goto out_free_cmd;
 943         }
 944
 945         if (blk_integrity_rq(req)) {
 946                 ret = nvme_map_metadata(dev, req, cmnd);
 947                 if (ret)
 948                         goto out_unmap_data;
 949         }
 950
 951         blk_mq_start_request(req);
 952         nvme_submit_cmd(nvmeq, cmnd, bd->last);
 953         return BLK_STS_OK;
 954 out_unmap_data:
 955         nvme_unmap_data(dev, req);
 956 out_free_cmd:
 957         nvme_cleanup_cmd(req);
 958         return ret;
 959 }
 960
 961 static void nvme_pci_complete_rq(struct request *req)
 962 {
 963         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 964         struct nvme_dev *dev = iod->nvmeq->dev;
 965
 966         if (blk_integrity_rq(req))
 967                 dma_unmap_page(dev->dev, iod->meta_dma,
 968                                rq_integrity_vec(req)->bv_len, rq_data_dir(req));
 969         if (blk_rq_nr_phys_segments(req))
 970                 nvme_unmap_data(dev, req);
 971         nvme_complete_rq(req);
 972 }
 973
 974 /* We read the CQE phase first to check if the rest of the entry is valid */
 975 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
 976 {
 977         struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
 978
 979         return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
 980 }
 981
 982 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
 983 {
 984         u16 head = nvmeq->cq_head;
 985
 986         if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
 987                                               nvmeq->dbbuf_cq_ei))
 988                 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 989 }
 990
 991 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
 992 {
 993         if (!nvmeq->qid)
 994                 return nvmeq->dev->admin_tagset.tags[0];
 995         return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
 996 }
 997
 998 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
 999 {
1000         struct nvme_completion *cqe = &nvmeq->cqes[idx];
1001         __u16 command_id = READ_ONCE(cqe->command_id);
1002         struct request *req;
1003
1004         /*
1005          * AEN requests are special as they don't time out and can
1006          * survive any kind of queue freeze and often don't respond to
1007          * aborts.  We don't even bother to allocate a struct request
1008          * for them but rather special case them here.
1009          */
1010         if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1011                 nvme_complete_async_event(&nvmeq->dev->ctrl,
1012                                 cqe->status, &cqe->result);
1013                 return;
1014         }
1015
1016         req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
1017         if (unlikely(!req)) {
1018                 dev_warn(nvmeq->dev->ctrl.device,
1019                         "invalid id %d completed on queue %d\n",
1020                         command_id, le16_to_cpu(cqe->sq_id));
1021                 return;
1022         }
1023
1024         trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1025         if (!nvme_try_complete_req(req, cqe->status, cqe->result))
1026                 nvme_pci_complete_rq(req);
1027 }
1028
1029 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1030 {
1031         u32 tmp = nvmeq->cq_head + 1;
1032
1033         if (tmp == nvmeq->q_depth) {
1034                 nvmeq->cq_head = 0;
1035                 nvmeq->cq_phase ^= 1;
1036         } else {
1037                 nvmeq->cq_head = tmp;
1038         }
1039 }
1040
1041 static inline int nvme_process_cq(struct nvme_queue *nvmeq)
1042 {
1043         int found = 0;
1044
1045         while (nvme_cqe_pending(nvmeq)) {
1046                 found++;
1047                 /*
1048                  * load-load control dependency between phase and the rest of
1049                  * the cqe requires a full read memory barrier
1050                  */
1051                 dma_rmb();
1052                 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
1053                 nvme_update_cq_head(nvmeq);
1054         }
1055
1056         if (found)
1057                 nvme_ring_cq_doorbell(nvmeq);
1058         return found;
1059 }
1060
1061 static irqreturn_t nvme_irq(int irq, void *data)
1062 {
1063         struct nvme_queue *nvmeq = data;
1064
1065         if (nvme_process_cq(nvmeq))
1066                 return IRQ_HANDLED;
1067         return IRQ_NONE;
1068 }
1069
1070 static irqreturn_t nvme_irq_check(int irq, void *data)
1071 {
1072         struct nvme_queue *nvmeq = data;
1073
1074         if (nvme_cqe_pending(nvmeq))
1075                 return IRQ_WAKE_THREAD;
1076         return IRQ_NONE;
1077 }
1078
1079 /*
1080  * Poll for completions for any interrupt driven queue
1081  * Can be called from any context.
1082  */
1083 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1084 {
1085         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1086
1087         WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1088
1089         disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1090         nvme_process_cq(nvmeq);
1091         enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1092 }
1093
1094 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1095 {
1096         struct nvme_queue *nvmeq = hctx->driver_data;
1097         bool found;
1098
1099         if (!nvme_cqe_pending(nvmeq))
1100                 return 0;
1101
1102         spin_lock(&nvmeq->cq_poll_lock);
1103         found = nvme_process_cq(nvmeq);
1104         spin_unlock(&nvmeq->cq_poll_lock);
1105
1106         return found;
1107 }
1108
1109 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1110 {
1111         struct nvme_dev *dev = to_nvme_dev(ctrl);
1112         struct nvme_queue *nvmeq = &dev->queues[0];
1113         struct nvme_command c = { };
1114
1115         c.common.opcode = nvme_admin_async_event;
1116         c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1117         nvme_submit_cmd(nvmeq, &c, true);
1118 }
1119
1120 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1121 {
1122         struct nvme_command c = { };
1123
1124         c.delete_queue.opcode = opcode;
1125         c.delete_queue.qid = cpu_to_le16(id);
1126
1127         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1128 }
1129
1130 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1131                 struct nvme_queue *nvmeq, s16 vector)
1132 {
1133         struct nvme_command c = { };
1134         int flags = NVME_QUEUE_PHYS_CONTIG;
1135
1136         if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1137                 flags |= NVME_CQ_IRQ_ENABLED;
1138
1139         /*
1140          * Note: we (ab)use the fact that the prp fields survive if no data
1141          * is attached to the request.
1142          */
1143         c.create_cq.opcode = nvme_admin_create_cq;
1144         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1145         c.create_cq.cqid = cpu_to_le16(qid);
1146         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1147         c.create_cq.cq_flags = cpu_to_le16(flags);
1148         c.create_cq.irq_vector = cpu_to_le16(vector);
1149
1150         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1151 }
1152
1153 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1154                                                 struct nvme_queue *nvmeq)
1155 {
1156         struct nvme_ctrl *ctrl = &dev->ctrl;
1157         struct nvme_command c = { };
1158         int flags = NVME_QUEUE_PHYS_CONTIG;
1159
1160         /*
1161          * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1162          * set. Since URGENT priority is zeroes, it makes all queues
1163          * URGENT.
1164          */
1165         if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1166                 flags |= NVME_SQ_PRIO_MEDIUM;
1167
1168         /*
1169          * Note: we (ab)use the fact that the prp fields survive if no data
1170          * is attached to the request.
1171          */
1172         c.create_sq.opcode = nvme_admin_create_sq;
1173         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1174         c.create_sq.sqid = cpu_to_le16(qid);
1175         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1176         c.create_sq.sq_flags = cpu_to_le16(flags);
1177         c.create_sq.cqid = cpu_to_le16(qid);
1178
1179         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1180 }
1181
1182 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1183 {
1184         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1185 }
1186
1187 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1188 {
1189         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1190 }
1191
1192 static void abort_endio(struct request *req, blk_status_t error)
1193 {
1194         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1195         struct nvme_queue *nvmeq = iod->nvmeq;
1196
1197         dev_warn(nvmeq->dev->ctrl.device,
1198                  "Abort status: 0x%x", nvme_req(req)->status);
1199         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1200         blk_mq_free_request(req);
1201 }
1202
1203 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1204 {
1205         /* If true, indicates loss of adapter communication, possibly by a
1206          * NVMe Subsystem reset.
1207          */
1208         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1209
1210         /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1211         switch (dev->ctrl.state) {
1212         case NVME_CTRL_RESETTING:
1213         case NVME_CTRL_CONNECTING:
1214                 return false;
1215         default:
1216                 break;
1217         }
1218
1219         /* We shouldn't reset unless the controller is on fatal error state
1220          * _or_ if we lost the communication with it.
1221          */
1222         if (!(csts & NVME_CSTS_CFS) && !nssro)
1223                 return false;
1224
1225         return true;
1226 }
1227
1228 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1229 {
1230         /* Read a config register to help see what died. */
1231         u16 pci_status;
1232         int result;
1233
1234         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1235                                       &pci_status);
1236         if (result == PCIBIOS_SUCCESSFUL)
1237                 dev_warn(dev->ctrl.device,
1238                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1239                          csts, pci_status);
1240         else
1241                 dev_warn(dev->ctrl.device,
1242                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1243                          csts, result);
1244 }
1245
1246 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1247 {
1248         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1249         struct nvme_queue *nvmeq = iod->nvmeq;
1250         struct nvme_dev *dev = nvmeq->dev;
1251         struct request *abort_req;
1252         struct nvme_command cmd = { };
1253         u32 csts = readl(dev->bar + NVME_REG_CSTS);
1254
1255         /* If PCI error recovery process is happening, we cannot reset or
1256          * the recovery mechanism will surely fail.
1257          */
1258         mb();
1259         if (pci_channel_offline(to_pci_dev(dev->dev)))
1260                 return BLK_EH_RESET_TIMER;
1261
1262         /*
1263          * Reset immediately if the controller is failed
1264          */
1265         if (nvme_should_reset(dev, csts)) {
1266                 nvme_warn_reset(dev, csts);
1267                 nvme_dev_disable(dev, false);
1268                 nvme_reset_ctrl(&dev->ctrl);
1269                 return BLK_EH_DONE;
1270         }
1271
1272         /*
1273          * Did we miss an interrupt?
1274          */
1275         if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1276                 nvme_poll(req->mq_hctx);
1277         else
1278                 nvme_poll_irqdisable(nvmeq);
1279
1280         if (blk_mq_request_completed(req)) {
1281                 dev_warn(dev->ctrl.device,
1282                          "I/O %d QID %d timeout, completion polled\n",
1283                          req->tag, nvmeq->qid);
1284                 return BLK_EH_DONE;
1285         }
1286
1287         /*
1288          * Shutdown immediately if controller times out while starting. The
1289          * reset work will see the pci device disabled when it gets the forced
1290          * cancellation error. All outstanding requests are completed on
1291          * shutdown, so we return BLK_EH_DONE.
1292          */
1293         switch (dev->ctrl.state) {
1294         case NVME_CTRL_CONNECTING:
1295                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1296                 fallthrough;
1297         case NVME_CTRL_DELETING:
1298                 dev_warn_ratelimited(dev->ctrl.device,
1299                          "I/O %d QID %d timeout, disable controller\n",
1300                          req->tag, nvmeq->qid);
1301                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1302                 nvme_dev_disable(dev, true);
1303                 return BLK_EH_DONE;
1304         case NVME_CTRL_RESETTING:
1305                 return BLK_EH_RESET_TIMER;
1306         default:
1307                 break;
1308         }
1309
1310         /*
1311          * Shutdown the controller immediately and schedule a reset if the
1312          * command was already aborted once before and still hasn't been
1313          * returned to the driver, or if this is the admin queue.
1314          */
1315         if (!nvmeq->qid || iod->aborted) {
1316                 dev_warn(dev->ctrl.device,
1317                          "I/O %d QID %d timeout, reset controller\n",
1318                          req->tag, nvmeq->qid);
1319                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1320                 nvme_dev_disable(dev, false);
1321                 nvme_reset_ctrl(&dev->ctrl);
1322
1323                 return BLK_EH_DONE;
1324         }
1325
1326         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1327                 atomic_inc(&dev->ctrl.abort_limit);
1328                 return BLK_EH_RESET_TIMER;
1329         }
1330         iod->aborted = 1;
1331
1332         cmd.abort.opcode = nvme_admin_abort_cmd;
1333         cmd.abort.cid = nvme_cid(req);
1334         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1335
1336         dev_warn(nvmeq->dev->ctrl.device,
1337                 "I/O %d QID %d timeout, aborting\n",
1338                  req->tag, nvmeq->qid);
1339
1340         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1341                         BLK_MQ_REQ_NOWAIT);
1342         if (IS_ERR(abort_req)) {
1343                 atomic_inc(&dev->ctrl.abort_limit);
1344                 return BLK_EH_RESET_TIMER;
1345         }
1346
1347         abort_req->end_io_data = NULL;
1348         blk_execute_rq_nowait(NULL, abort_req, 0, abort_endio);
1349
1350         /*
1351          * The aborted req will be completed on receiving the abort req.
1352          * We enable the timer again. If hit twice, it'll cause a device reset,
1353          * as the device then is in a faulty state.
1354          */
1355         return BLK_EH_RESET_TIMER;
1356 }
1357
1358 static void nvme_free_queue(struct nvme_queue *nvmeq)
1359 {
1360         dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1361                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1362         if (!nvmeq->sq_cmds)
1363                 return;
1364
1365         if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1366                 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1367                                 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1368         } else {
1369                 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1370                                 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1371         }
1372 }
1373
1374 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1375 {
1376         int i;
1377
1378         for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1379                 dev->ctrl.queue_count--;
1380                 nvme_free_queue(&dev->queues[i]);
1381         }
1382 }
1383
1384 /**
1385  * nvme_suspend_queue - put queue into suspended state
1386  * @nvmeq: queue to suspend
1387  */
1388 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1389 {
1390         if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1391                 return 1;
1392
1393         /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1394         mb();
1395
1396         nvmeq->dev->online_queues--;
1397         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1398                 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1399         if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1400                 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1401         return 0;
1402 }
1403
1404 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1405 {
1406         int i;
1407
1408         for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1409                 nvme_suspend_queue(&dev->queues[i]);
1410 }
1411
1412 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1413 {
1414         struct nvme_queue *nvmeq = &dev->queues[0];
1415
1416         if (shutdown)
1417                 nvme_shutdown_ctrl(&dev->ctrl);
1418         else
1419                 nvme_disable_ctrl(&dev->ctrl);
1420
1421         nvme_poll_irqdisable(nvmeq);
1422 }
1423
1424 /*
1425  * Called only on a device that has been disabled and after all other threads
1426  * that can check this device's completion queues have synced, except
1427  * nvme_poll(). This is the last chance for the driver to see a natural
1428  * completion before nvme_cancel_request() terminates all incomplete requests.
1429  */
1430 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1431 {
1432         int i;
1433
1434         for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1435                 spin_lock(&dev->queues[i].cq_poll_lock);
1436                 nvme_process_cq(&dev->queues[i]);
1437                 spin_unlock(&dev->queues[i].cq_poll_lock);
1438         }
1439 }
1440
1441 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1442                                 int entry_size)
1443 {
1444         int q_depth = dev->q_depth;
1445         unsigned q_size_aligned = roundup(q_depth * entry_size,
1446                                           NVME_CTRL_PAGE_SIZE);
1447
1448         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1449                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1450
1451                 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1452                 q_depth = div_u64(mem_per_q, entry_size);
1453
1454                 /*
1455                  * Ensure the reduced q_depth is above some threshold where it
1456                  * would be better to map queues in system memory with the
1457                  * original depth
1458                  */
1459                 if (q_depth < 64)
1460                         return -ENOMEM;
1461         }
1462
1463         return q_depth;
1464 }
1465
1466 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1467                                 int qid)
1468 {
1469         struct pci_dev *pdev = to_pci_dev(dev->dev);
1470
1471         if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1472                 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1473                 if (nvmeq->sq_cmds) {
1474                         nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1475                                                         nvmeq->sq_cmds);
1476                         if (nvmeq->sq_dma_addr) {
1477                                 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1478                                 return 0;
1479                         }
1480
1481                         pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1482                 }
1483         }
1484
1485         nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1486                                 &nvmeq->sq_dma_addr, GFP_KERNEL);
1487         if (!nvmeq->sq_cmds)
1488                 return -ENOMEM;
1489         return 0;
1490 }
1491
1492 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1493 {
1494         struct nvme_queue *nvmeq = &dev->queues[qid];
1495
1496         if (dev->ctrl.queue_count > qid)
1497                 return 0;
1498
1499         nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1500         nvmeq->q_depth = depth;
1501         nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1502                                          &nvmeq->cq_dma_addr, GFP_KERNEL);
1503         if (!nvmeq->cqes)
1504                 goto free_nvmeq;
1505
1506         if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1507                 goto free_cqdma;
1508
1509         nvmeq->dev = dev;
1510         spin_lock_init(&nvmeq->sq_lock);
1511         spin_lock_init(&nvmeq->cq_poll_lock);
1512         nvmeq->cq_head = 0;
1513         nvmeq->cq_phase = 1;
1514         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1515         nvmeq->qid = qid;
1516         dev->ctrl.queue_count++;
1517
1518         return 0;
1519
1520  free_cqdma:
1521         dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1522                           nvmeq->cq_dma_addr);
1523  free_nvmeq:
1524         return -ENOMEM;
1525 }
1526
1527 static int queue_request_irq(struct nvme_queue *nvmeq)
1528 {
1529         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1530         int nr = nvmeq->dev->ctrl.instance;
1531
1532         if (use_threaded_interrupts) {
1533                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1534                                 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1535         } else {
1536                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1537                                 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1538         }
1539 }
1540
1541 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1542 {
1543         struct nvme_dev *dev = nvmeq->dev;
1544
1545         nvmeq->sq_tail = 0;
1546         nvmeq->last_sq_tail = 0;
1547         nvmeq->cq_head = 0;
1548         nvmeq->cq_phase = 1;
1549         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1550         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1551         nvme_dbbuf_init(dev, nvmeq, qid);
1552         dev->online_queues++;
1553         wmb(); /* ensure the first interrupt sees the initialization */
1554 }
1555
1556 /*
1557  * Try getting shutdown_lock while setting up IO queues.
1558  */
1559 static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1560 {
1561         /*
1562          * Give up if the lock is being held by nvme_dev_disable.
1563          */
1564         if (!mutex_trylock(&dev->shutdown_lock))
1565                 return -ENODEV;
1566
1567         /*
1568          * Controller is in wrong state, fail early.
1569          */
1570         if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1571                 mutex_unlock(&dev->shutdown_lock);
1572                 return -ENODEV;
1573         }
1574
1575         return 0;
1576 }
1577
1578 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1579 {
1580         struct nvme_dev *dev = nvmeq->dev;
1581         int result;
1582         u16 vector = 0;
1583
1584         clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1585
1586         /*
1587          * A queue's vector matches the queue identifier unless the controller
1588          * has only one vector available.
1589          */
1590         if (!polled)
1591                 vector = dev->num_vecs == 1 ? 0 : qid;
1592         else
1593                 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1594
1595         result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1596         if (result)
1597                 return result;
1598
1599         result = adapter_alloc_sq(dev, qid, nvmeq);
1600         if (result < 0)
1601                 return result;
1602         if (result)
1603                 goto release_cq;
1604
1605         nvmeq->cq_vector = vector;
1606
1607         result = nvme_setup_io_queues_trylock(dev);
1608         if (result)
1609                 return result;
1610         nvme_init_queue(nvmeq, qid);
1611         if (!polled) {
1612                 result = queue_request_irq(nvmeq);
1613                 if (result < 0)
1614                         goto release_sq;
1615         }
1616
1617         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1618         mutex_unlock(&dev->shutdown_lock);
1619         return result;
1620
1621 release_sq:
1622         dev->online_queues--;
1623         mutex_unlock(&dev->shutdown_lock);
1624         adapter_delete_sq(dev, qid);
1625 release_cq:
1626         adapter_delete_cq(dev, qid);
1627         return result;
1628 }
1629
1630 static const struct blk_mq_ops nvme_mq_admin_ops = {
1631         .queue_rq       = nvme_queue_rq,
1632         .complete       = nvme_pci_complete_rq,
1633         .init_hctx      = nvme_admin_init_hctx,
1634         .init_request   = nvme_init_request,
1635         .timeout        = nvme_timeout,
1636 };
1637
1638 static const struct blk_mq_ops nvme_mq_ops = {
1639         .queue_rq       = nvme_queue_rq,
1640         .complete       = nvme_pci_complete_rq,
1641         .commit_rqs     = nvme_commit_rqs,
1642         .init_hctx      = nvme_init_hctx,
1643         .init_request   = nvme_init_request,
1644         .map_queues     = nvme_pci_map_queues,
1645         .timeout        = nvme_timeout,
1646         .poll           = nvme_poll,
1647 };
1648
1649 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1650 {
1651         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1652                 /*
1653                  * If the controller was reset during removal, it's possible
1654                  * user requests may be waiting on a stopped queue. Start the
1655                  * queue to flush these to completion.
1656                  */
1657                 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1658                 blk_cleanup_queue(dev->ctrl.admin_q);
1659                 blk_mq_free_tag_set(&dev->admin_tagset);
1660         }
1661 }
1662
1663 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1664 {
1665         if (!dev->ctrl.admin_q) {
1666                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1667                 dev->admin_tagset.nr_hw_queues = 1;
1668
1669                 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1670                 dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
1671                 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
1672                 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1673                 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1674                 dev->admin_tagset.driver_data = dev;
1675
1676                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1677                         return -ENOMEM;
1678                 dev->ctrl.admin_tagset = &dev->admin_tagset;
1679
1680                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1681                 if (IS_ERR(dev->ctrl.admin_q)) {
1682                         blk_mq_free_tag_set(&dev->admin_tagset);
1683                         dev->ctrl.admin_q = NULL;
1684                         return -ENOMEM;
1685                 }
1686                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1687                         nvme_dev_remove_admin(dev);
1688                         dev->ctrl.admin_q = NULL;
1689                         return -ENODEV;
1690                 }
1691         } else
1692                 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1693
1694         return 0;
1695 }
1696
1697 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1698 {
1699         return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1700 }
1701
1702 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1703 {
1704         struct pci_dev *pdev = to_pci_dev(dev->dev);
1705
1706         if (size <= dev->bar_mapped_size)
1707                 return 0;
1708         if (size > pci_resource_len(pdev, 0))
1709                 return -ENOMEM;
1710         if (dev->bar)
1711                 iounmap(dev->bar);
1712         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1713         if (!dev->bar) {
1714                 dev->bar_mapped_size = 0;
1715                 return -ENOMEM;
1716         }
1717         dev->bar_mapped_size = size;
1718         dev->dbs = dev->bar + NVME_REG_DBS;
1719
1720         return 0;
1721 }
1722
1723 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1724 {
1725         int result;
1726         u32 aqa;
1727         struct nvme_queue *nvmeq;
1728
1729         result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1730         if (result < 0)
1731                 return result;
1732
1733         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1734                                 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1735
1736         if (dev->subsystem &&
1737             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1738                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1739
1740         result = nvme_disable_ctrl(&dev->ctrl);
1741         if (result < 0)
1742                 return result;
1743
1744         result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1745         if (result)
1746                 return result;
1747
1748         dev->ctrl.numa_node = dev_to_node(dev->dev);
1749
1750         nvmeq = &dev->queues[0];
1751         aqa = nvmeq->q_depth - 1;
1752         aqa |= aqa << 16;
1753
1754         writel(aqa, dev->bar + NVME_REG_AQA);
1755         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1756         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1757
1758         result = nvme_enable_ctrl(&dev->ctrl);
1759         if (result)
1760                 return result;
1761
1762         nvmeq->cq_vector = 0;
1763         nvme_init_queue(nvmeq, 0);
1764         result = queue_request_irq(nvmeq);
1765         if (result) {
1766                 dev->online_queues--;
1767                 return result;
1768         }
1769
1770         set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1771         return result;
1772 }
1773
1774 static int nvme_create_io_queues(struct nvme_dev *dev)
1775 {
1776         unsigned i, max, rw_queues;
1777         int ret = 0;
1778
1779         for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1780                 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1781                         ret = -ENOMEM;
1782                         break;
1783                 }
1784         }
1785
1786         max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1787         if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1788                 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1789                                 dev->io_queues[HCTX_TYPE_READ];
1790         } else {
1791                 rw_queues = max;
1792         }
1793
1794         for (i = dev->online_queues; i <= max; i++) {
1795                 bool polled = i > rw_queues;
1796
1797                 ret = nvme_create_queue(&dev->queues[i], i, polled);
1798                 if (ret)
1799                         break;
1800         }
1801
1802         /*
1803          * Ignore failing Create SQ/CQ commands, we can continue with less
1804          * than the desired amount of queues, and even a controller without
1805          * I/O queues can still be used to issue admin commands.  This might
1806          * be useful to upgrade a buggy firmware for example.
1807          */
1808         return ret >= 0 ? 0 : ret;
1809 }
1810
1811 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1812 {
1813         u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1814
1815         return 1ULL << (12 + 4 * szu);
1816 }
1817
1818 static u32 nvme_cmb_size(struct nvme_dev *dev)
1819 {
1820         return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1821 }
1822
1823 static void nvme_map_cmb(struct nvme_dev *dev)
1824 {
1825         u64 size, offset;
1826         resource_size_t bar_size;
1827         struct pci_dev *pdev = to_pci_dev(dev->dev);
1828         int bar;
1829
1830         if (dev->cmb_size)
1831                 return;
1832
1833         if (NVME_CAP_CMBS(dev->ctrl.cap))
1834                 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1835
1836         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1837         if (!dev->cmbsz)
1838                 return;
1839         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1840
1841         size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1842         offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1843         bar = NVME_CMB_BIR(dev->cmbloc);
1844         bar_size = pci_resource_len(pdev, bar);
1845
1846         if (offset > bar_size)
1847                 return;
1848
1849         /*
1850          * Tell the controller about the host side address mapping the CMB,
1851          * and enable CMB decoding for the NVMe 1.4+ scheme:
1852          */
1853         if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1854                 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1855                              (pci_bus_address(pdev, bar) + offset),
1856                              dev->bar + NVME_REG_CMBMSC);
1857         }
1858
1859         /*
1860          * Controllers may support a CMB size larger than their BAR,
1861          * for example, due to being behind a bridge. Reduce the CMB to
1862          * the reported size of the BAR
1863          */
1864         if (size > bar_size - offset)
1865                 size = bar_size - offset;
1866
1867         if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1868                 dev_warn(dev->ctrl.device,
1869                          "failed to register the CMB\n");
1870                 return;
1871         }
1872
1873         dev->cmb_size = size;
1874         dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1875
1876         if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1877                         (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1878                 pci_p2pmem_publish(pdev, true);
1879 }
1880
1881 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1882 {
1883         u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1884         u64 dma_addr = dev->host_mem_descs_dma;
1885         struct nvme_command c = { };
1886         int ret;
1887
1888         c.features.opcode       = nvme_admin_set_features;
1889         c.features.fid          = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1890         c.features.dword11      = cpu_to_le32(bits);
1891         c.features.dword12      = cpu_to_le32(host_mem_size);
1892         c.features.dword13      = cpu_to_le32(lower_32_bits(dma_addr));
1893         c.features.dword14      = cpu_to_le32(upper_32_bits(dma_addr));
1894         c.features.dword15      = cpu_to_le32(dev->nr_host_mem_descs);
1895
1896         ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1897         if (ret) {
1898                 dev_warn(dev->ctrl.device,
1899                          "failed to set host mem (err %d, flags %#x).\n",
1900                          ret, bits);
1901         } else
1902                 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1903
1904         return ret;
1905 }
1906
1907 static void nvme_free_host_mem(struct nvme_dev *dev)
1908 {
1909         int i;
1910
1911         for (i = 0; i < dev->nr_host_mem_descs; i++) {
1912                 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1913                 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
1914
1915                 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1916                                le64_to_cpu(desc->addr),
1917                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1918         }
1919
1920         kfree(dev->host_mem_desc_bufs);
1921         dev->host_mem_desc_bufs = NULL;
1922         dma_free_coherent(dev->dev,
1923                         dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1924                         dev->host_mem_descs, dev->host_mem_descs_dma);
1925         dev->host_mem_descs = NULL;
1926         dev->nr_host_mem_descs = 0;
1927 }
1928
1929 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1930                 u32 chunk_size)
1931 {
1932         struct nvme_host_mem_buf_desc *descs;
1933         u32 max_entries, len;
1934         dma_addr_t descs_dma;
1935         int i = 0;
1936         void **bufs;
1937         u64 size, tmp;
1938
1939         tmp = (preferred + chunk_size - 1);
1940         do_div(tmp, chunk_size);
1941         max_entries = tmp;
1942
1943         if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1944                 max_entries = dev->ctrl.hmmaxd;
1945
1946         descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1947                                    &descs_dma, GFP_KERNEL);
1948         if (!descs)
1949                 goto out;
1950
1951         bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1952         if (!bufs)
1953                 goto out_free_descs;
1954
1955         for (size = 0; size < preferred && i < max_entries; size += len) {
1956                 dma_addr_t dma_addr;
1957
1958                 len = min_t(u64, chunk_size, preferred - size);
1959                 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1960                                 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1961                 if (!bufs[i])
1962                         break;
1963
1964                 descs[i].addr = cpu_to_le64(dma_addr);
1965                 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
1966                 i++;
1967         }
1968
1969         if (!size)
1970                 goto out_free_bufs;
1971
1972         dev->nr_host_mem_descs = i;
1973         dev->host_mem_size = size;
1974         dev->host_mem_descs = descs;
1975         dev->host_mem_descs_dma = descs_dma;
1976         dev->host_mem_desc_bufs = bufs;
1977         return 0;
1978
1979 out_free_bufs:
1980         while (--i >= 0) {
1981                 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
1982
1983                 dma_free_attrs(dev->dev, size, bufs[i],
1984                                le64_to_cpu(descs[i].addr),
1985                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1986         }
1987
1988         kfree(bufs);
1989 out_free_descs:
1990         dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1991                         descs_dma);
1992 out:
1993         dev->host_mem_descs = NULL;
1994         return -ENOMEM;
1995 }
1996
1997 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1998 {
1999         u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2000         u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2001         u64 chunk_size;
2002
2003         /* start big and work our way down */
2004         for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2005                 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2006                         if (!min || dev->host_mem_size >= min)
2007                                 return 0;
2008                         nvme_free_host_mem(dev);
2009                 }
2010         }
2011
2012         return -ENOMEM;
2013 }
2014
2015 static int nvme_setup_host_mem(struct nvme_dev *dev)
2016 {
2017         u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2018         u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2019         u64 min = (u64)dev->ctrl.hmmin * 4096;
2020         u32 enable_bits = NVME_HOST_MEM_ENABLE;
2021         int ret;
2022
2023         preferred = min(preferred, max);
2024         if (min > max) {
2025                 dev_warn(dev->ctrl.device,
2026                         "min host memory (%lld MiB) above limit (%d MiB).\n",
2027                         min >> ilog2(SZ_1M), max_host_mem_size_mb);
2028                 nvme_free_host_mem(dev);
2029                 return 0;
2030         }
2031
2032         /*
2033          * If we already have a buffer allocated check if we can reuse it.
2034          */
2035         if (dev->host_mem_descs) {
2036                 if (dev->host_mem_size >= min)
2037                         enable_bits |= NVME_HOST_MEM_RETURN;
2038                 else
2039                         nvme_free_host_mem(dev);
2040         }
2041
2042         if (!dev->host_mem_descs) {
2043                 if (nvme_alloc_host_mem(dev, min, preferred)) {
2044                         dev_warn(dev->ctrl.device,
2045                                 "failed to allocate host memory buffer.\n");
2046                         return 0; /* controller must work without HMB */
2047                 }
2048
2049                 dev_info(dev->ctrl.device,
2050                         "allocated %lld MiB host memory buffer.\n",
2051                         dev->host_mem_size >> ilog2(SZ_1M));
2052         }
2053
2054         ret = nvme_set_host_mem(dev, enable_bits);
2055         if (ret)
2056                 nvme_free_host_mem(dev);
2057         return ret;
2058 }
2059
2060 static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2061                 char *buf)
2062 {
2063         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2064
2065         return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz  : x%08x\n",
2066                        ndev->cmbloc, ndev->cmbsz);
2067 }
2068 static DEVICE_ATTR_RO(cmb);
2069
2070 static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2071                 char *buf)
2072 {
2073         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2074
2075         return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2076 }
2077 static DEVICE_ATTR_RO(cmbloc);
2078
2079 static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2080                 char *buf)
2081 {
2082         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2083
2084         return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2085 }
2086 static DEVICE_ATTR_RO(cmbsz);
2087
2088 static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2089                         char *buf)
2090 {
2091         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2092
2093         return sysfs_emit(buf, "%d\n", ndev->hmb);
2094 }
2095
2096 static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2097                          const char *buf, size_t count)
2098 {
2099         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2100         bool new;
2101         int ret;
2102
2103         if (strtobool(buf, &new) < 0)
2104                 return -EINVAL;
2105
2106         if (new == ndev->hmb)
2107                 return count;
2108
2109         if (new) {
2110                 ret = nvme_setup_host_mem(ndev);
2111         } else {
2112                 ret = nvme_set_host_mem(ndev, 0);
2113                 if (!ret)
2114                         nvme_free_host_mem(ndev);
2115         }
2116
2117         if (ret < 0)
2118                 return ret;
2119
2120         return count;
2121 }
2122 static DEVICE_ATTR_RW(hmb);
2123
2124 static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2125                 struct attribute *a, int n)
2126 {
2127         struct nvme_ctrl *ctrl =
2128                 dev_get_drvdata(container_of(kobj, struct device, kobj));
2129         struct nvme_dev *dev = to_nvme_dev(ctrl);
2130
2131         if (a == &dev_attr_cmb.attr ||
2132             a == &dev_attr_cmbloc.attr ||
2133             a == &dev_attr_cmbsz.attr) {
2134                 if (!dev->cmbsz)
2135                         return 0;
2136         }
2137         if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2138                 return 0;
2139
2140         return a->mode;
2141 }
2142
2143 static struct attribute *nvme_pci_attrs[] = {
2144         &dev_attr_cmb.attr,
2145         &dev_attr_cmbloc.attr,
2146         &dev_attr_cmbsz.attr,
2147         &dev_attr_hmb.attr,
2148         NULL,
2149 };
2150
2151 static const struct attribute_group nvme_pci_attr_group = {
2152         .attrs          = nvme_pci_attrs,
2153         .is_visible     = nvme_pci_attrs_are_visible,
2154 };
2155
2156 /*
2157  * nirqs is the number of interrupts available for write and read
2158  * queues. The core already reserved an interrupt for the admin queue.
2159  */
2160 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2161 {
2162         struct nvme_dev *dev = affd->priv;
2163         unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2164
2165         /*
2166          * If there is no interrupt available for queues, ensure that
2167          * the default queue is set to 1. The affinity set size is
2168          * also set to one, but the irq core ignores it for this case.
2169          *
2170          * If only one interrupt is available or 'write_queue' == 0, combine
2171          * write and read queues.
2172          *
2173          * If 'write_queues' > 0, ensure it leaves room for at least one read
2174          * queue.
2175          */
2176         if (!nrirqs) {
2177                 nrirqs = 1;
2178                 nr_read_queues = 0;
2179         } else if (nrirqs == 1 || !nr_write_queues) {
2180                 nr_read_queues = 0;
2181         } else if (nr_write_queues >= nrirqs) {
2182                 nr_read_queues = 1;
2183         } else {
2184                 nr_read_queues = nrirqs - nr_write_queues;
2185         }
2186
2187         dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2188         affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2189         dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2190         affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2191         affd->nr_sets = nr_read_queues ? 2 : 1;
2192 }
2193
2194 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2195 {
2196         struct pci_dev *pdev = to_pci_dev(dev->dev);
2197         struct irq_affinity affd = {
2198                 .pre_vectors    = 1,
2199                 .calc_sets      = nvme_calc_irq_sets,
2200                 .priv           = dev,
2201         };
2202         unsigned int irq_queues, poll_queues;
2203
2204         /*
2205          * Poll queues don't need interrupts, but we need at least one I/O queue
2206          * left over for non-polled I/O.
2207          */
2208         poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2209         dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2210
2211         /*
2212          * Initialize for the single interrupt case, will be updated in
2213          * nvme_calc_irq_sets().
2214          */
2215         dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2216         dev->io_queues[HCTX_TYPE_READ] = 0;
2217
2218         /*
2219          * We need interrupts for the admin queue and each non-polled I/O queue,
2220          * but some Apple controllers require all queues to use the first
2221          * vector.
2222          */
2223         irq_queues = 1;
2224         if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2225                 irq_queues += (nr_io_queues - poll_queues);
2226         return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2227                               PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2228 }
2229
2230 static void nvme_disable_io_queues(struct nvme_dev *dev)
2231 {
2232         if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2233                 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2234 }
2235
2236 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2237 {
2238         /*
2239          * If tags are shared with admin queue (Apple bug), then
2240          * make sure we only use one IO queue.
2241          */
2242         if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2243                 return 1;
2244         return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2245 }
2246
2247 static int nvme_setup_io_queues(struct nvme_dev *dev)
2248 {
2249         struct nvme_queue *adminq = &dev->queues[0];
2250         struct pci_dev *pdev = to_pci_dev(dev->dev);
2251         unsigned int nr_io_queues;
2252         unsigned long size;
2253         int result;
2254
2255         /*
2256          * Sample the module parameters once at reset time so that we have
2257          * stable values to work with.
2258          */
2259         dev->nr_write_queues = write_queues;
2260         dev->nr_poll_queues = poll_queues;
2261
2262         nr_io_queues = dev->nr_allocated_queues - 1;
2263         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2264         if (result < 0)
2265                 return result;
2266
2267         if (nr_io_queues == 0)
2268                 return 0;
2269
2270         /*
2271          * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2272          * from set to unset. If there is a window to it is truely freed,
2273          * pci_free_irq_vectors() jumping into this window will crash.
2274          * And take lock to avoid racing with pci_free_irq_vectors() in
2275          * nvme_dev_disable() path.
2276          */
2277         result = nvme_setup_io_queues_trylock(dev);
2278         if (result)
2279                 return result;
2280         if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2281                 pci_free_irq(pdev, 0, adminq);
2282
2283         if (dev->cmb_use_sqes) {
2284                 result = nvme_cmb_qdepth(dev, nr_io_queues,
2285                                 sizeof(struct nvme_command));
2286                 if (result > 0)
2287                         dev->q_depth = result;
2288                 else
2289                         dev->cmb_use_sqes = false;
2290         }
2291
2292         do {
2293                 size = db_bar_size(dev, nr_io_queues);
2294                 result = nvme_remap_bar(dev, size);
2295                 if (!result)
2296                         break;
2297                 if (!--nr_io_queues) {
2298                         result = -ENOMEM;
2299                         goto out_unlock;
2300                 }
2301         } while (1);
2302         adminq->q_db = dev->dbs;
2303
2304  retry:
2305         /* Deregister the admin queue's interrupt */
2306         if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2307                 pci_free_irq(pdev, 0, adminq);
2308
2309         /*
2310          * If we enable msix early due to not intx, disable it again before
2311          * setting up the full range we need.
2312          */
2313         pci_free_irq_vectors(pdev);
2314
2315         result = nvme_setup_irqs(dev, nr_io_queues);
2316         if (result <= 0) {
2317                 result = -EIO;
2318                 goto out_unlock;
2319         }
2320
2321         dev->num_vecs = result;
2322         result = max(result - 1, 1);
2323         dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2324
2325         /*
2326          * Should investigate if there's a performance win from allocating
2327          * more queues than interrupt vectors; it might allow the submission
2328          * path to scale better, even if the receive path is limited by the
2329          * number of interrupts.
2330          */
2331         result = queue_request_irq(adminq);
2332         if (result)
2333                 goto out_unlock;
2334         set_bit(NVMEQ_ENABLED, &adminq->flags);
2335         mutex_unlock(&dev->shutdown_lock);
2336
2337         result = nvme_create_io_queues(dev);
2338         if (result || dev->online_queues < 2)
2339                 return result;
2340
2341         if (dev->online_queues - 1 < dev->max_qid) {
2342                 nr_io_queues = dev->online_queues - 1;
2343                 nvme_disable_io_queues(dev);
2344                 result = nvme_setup_io_queues_trylock(dev);
2345                 if (result)
2346                         return result;
2347                 nvme_suspend_io_queues(dev);
2348                 goto retry;
2349         }
2350         dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2351                                         dev->io_queues[HCTX_TYPE_DEFAULT],
2352                                         dev->io_queues[HCTX_TYPE_READ],
2353                                         dev->io_queues[HCTX_TYPE_POLL]);
2354         return 0;
2355 out_unlock:
2356         mutex_unlock(&dev->shutdown_lock);
2357         return result;
2358 }
2359
2360 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2361 {
2362         struct nvme_queue *nvmeq = req->end_io_data;
2363
2364         blk_mq_free_request(req);
2365         complete(&nvmeq->delete_done);
2366 }
2367
2368 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2369 {
2370         struct nvme_queue *nvmeq = req->end_io_data;
2371
2372         if (error)
2373                 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2374
2375         nvme_del_queue_end(req, error);
2376 }
2377
2378 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2379 {
2380         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2381         struct request *req;
2382         struct nvme_command cmd = { };
2383
2384         cmd.delete_queue.opcode = opcode;
2385         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2386
2387         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
2388         if (IS_ERR(req))
2389                 return PTR_ERR(req);
2390
2391         req->end_io_data = nvmeq;
2392
2393         init_completion(&nvmeq->delete_done);
2394         blk_execute_rq_nowait(NULL, req, false,
2395                         opcode == nvme_admin_delete_cq ?
2396                                 nvme_del_cq_end : nvme_del_queue_end);
2397         return 0;
2398 }
2399
2400 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2401 {
2402         int nr_queues = dev->online_queues - 1, sent = 0;
2403         unsigned long timeout;
2404
2405  retry:
2406         timeout = NVME_ADMIN_TIMEOUT;
2407         while (nr_queues > 0) {
2408                 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2409                         break;
2410                 nr_queues--;
2411                 sent++;
2412         }
2413         while (sent) {
2414                 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2415
2416                 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2417                                 timeout);
2418                 if (timeout == 0)
2419                         return false;
2420
2421                 sent--;
2422                 if (nr_queues)
2423                         goto retry;
2424         }
2425         return true;
2426 }
2427
2428 static void nvme_dev_add(struct nvme_dev *dev)
2429 {
2430         int ret;
2431
2432         if (!dev->ctrl.tagset) {
2433                 dev->tagset.ops = &nvme_mq_ops;
2434                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2435                 dev->tagset.nr_maps = 2; /* default + read */
2436                 if (dev->io_queues[HCTX_TYPE_POLL])
2437                         dev->tagset.nr_maps++;
2438                 dev->tagset.timeout = NVME_IO_TIMEOUT;
2439                 dev->tagset.numa_node = dev->ctrl.numa_node;
2440                 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2441                                                 BLK_MQ_MAX_DEPTH) - 1;
2442                 dev->tagset.cmd_size = sizeof(struct nvme_iod);
2443                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2444                 dev->tagset.driver_data = dev;
2445
2446                 /*
2447                  * Some Apple controllers requires tags to be unique
2448                  * across admin and IO queue, so reserve the first 32
2449                  * tags of the IO queue.
2450                  */
2451                 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2452                         dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2453
2454                 ret = blk_mq_alloc_tag_set(&dev->tagset);
2455                 if (ret) {
2456                         dev_warn(dev->ctrl.device,
2457                                 "IO queues tagset allocation failed %d\n", ret);
2458                         return;
2459                 }
2460                 dev->ctrl.tagset = &dev->tagset;
2461         } else {
2462                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2463
2464                 /* Free previously allocated queues that are no longer usable */
2465                 nvme_free_queues(dev, dev->online_queues);
2466         }
2467
2468         nvme_dbbuf_set(dev);
2469 }
2470
2471 static int nvme_pci_enable(struct nvme_dev *dev)
2472 {
2473         int result = -ENOMEM;
2474         struct pci_dev *pdev = to_pci_dev(dev->dev);
2475         int dma_address_bits = 64;
2476
2477         if (pci_enable_device_mem(pdev))
2478                 return result;
2479
2480         pci_set_master(pdev);
2481
2482         if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2483                 dma_address_bits = 48;
2484         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
2485                 goto disable;
2486
2487         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2488                 result = -ENODEV;
2489                 goto disable;
2490         }
2491
2492         /*
2493          * Some devices and/or platforms don't advertise or work with INTx
2494          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2495          * adjust this later.
2496          */
2497         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2498         if (result < 0)
2499                 return result;
2500
2501         dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2502
2503         dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2504                                 io_queue_depth);
2505         dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2506         dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2507         dev->dbs = dev->bar + 4096;
2508
2509         /*
2510          * Some Apple controllers require a non-standard SQE size.
2511          * Interestingly they also seem to ignore the CC:IOSQES register
2512          * so we don't bother updating it here.
2513          */
2514         if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2515                 dev->io_sqes = 7;
2516         else
2517                 dev->io_sqes = NVME_NVM_IOSQES;
2518
2519         /*
2520          * Temporary fix for the Apple controller found in the MacBook8,1 and
2521          * some MacBook7,1 to avoid controller resets and data loss.
2522          */
2523         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2524                 dev->q_depth = 2;
2525                 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2526                         "set queue depth=%u to work around controller resets\n",
2527                         dev->q_depth);
2528         } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2529                    (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2530                    NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2531                 dev->q_depth = 64;
2532                 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2533                         "set queue depth=%u\n", dev->q_depth);
2534         }
2535
2536         /*
2537          * Controllers with the shared tags quirk need the IO queue to be
2538          * big enough so that we get 32 tags for the admin queue
2539          */
2540         if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2541             (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2542                 dev->q_depth = NVME_AQ_DEPTH + 2;
2543                 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2544                          dev->q_depth);
2545         }
2546
2547
2548         nvme_map_cmb(dev);
2549
2550         pci_enable_pcie_error_reporting(pdev);
2551         pci_save_state(pdev);
2552         return 0;
2553
2554  disable:
2555         pci_disable_device(pdev);
2556         return result;
2557 }
2558
2559 static void nvme_dev_unmap(struct nvme_dev *dev)
2560 {
2561         if (dev->bar)
2562                 iounmap(dev->bar);
2563         pci_release_mem_regions(to_pci_dev(dev->dev));
2564 }
2565
2566 static void nvme_pci_disable(struct nvme_dev *dev)
2567 {
2568         struct pci_dev *pdev = to_pci_dev(dev->dev);
2569
2570         pci_free_irq_vectors(pdev);
2571
2572         if (pci_is_enabled(pdev)) {
2573                 pci_disable_pcie_error_reporting(pdev);
2574                 pci_disable_device(pdev);
2575         }
2576 }
2577
2578 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2579 {
2580         bool dead = true, freeze = false;
2581         struct pci_dev *pdev = to_pci_dev(dev->dev);
2582
2583         mutex_lock(&dev->shutdown_lock);
2584         if (pci_is_enabled(pdev)) {
2585                 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2586
2587                 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2588                     dev->ctrl.state == NVME_CTRL_RESETTING) {
2589                         freeze = true;
2590                         nvme_start_freeze(&dev->ctrl);
2591                 }
2592                 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2593                         pdev->error_state  != pci_channel_io_normal);
2594         }
2595
2596         /*
2597          * Give the controller a chance to complete all entered requests if
2598          * doing a safe shutdown.
2599          */
2600         if (!dead && shutdown && freeze)
2601                 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2602
2603         nvme_stop_queues(&dev->ctrl);
2604
2605         if (!dead && dev->ctrl.queue_count > 0) {
2606                 nvme_disable_io_queues(dev);
2607                 nvme_disable_admin_queue(dev, shutdown);
2608         }
2609         nvme_suspend_io_queues(dev);
2610         nvme_suspend_queue(&dev->queues[0]);
2611         nvme_pci_disable(dev);
2612         nvme_reap_pending_cqes(dev);
2613
2614         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2615         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2616         blk_mq_tagset_wait_completed_request(&dev->tagset);
2617         blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
2618
2619         /*
2620          * The driver will not be starting up queues again if shutting down so
2621          * must flush all entered requests to their failed completion to avoid
2622          * deadlocking blk-mq hot-cpu notifier.
2623          */
2624         if (shutdown) {
2625                 nvme_start_queues(&dev->ctrl);
2626                 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2627                         blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2628         }
2629         mutex_unlock(&dev->shutdown_lock);
2630 }
2631
2632 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2633 {
2634         if (!nvme_wait_reset(&dev->ctrl))
2635                 return -EBUSY;
2636         nvme_dev_disable(dev, shutdown);
2637         return 0;
2638 }
2639
2640 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2641 {
2642         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2643                                                 NVME_CTRL_PAGE_SIZE,
2644                                                 NVME_CTRL_PAGE_SIZE, 0);
2645         if (!dev->prp_page_pool)
2646                 return -ENOMEM;
2647
2648         /* Optimisation for I/Os between 4k and 128k */
2649         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2650                                                 256, 256, 0);
2651         if (!dev->prp_small_pool) {
2652                 dma_pool_destroy(dev->prp_page_pool);
2653                 return -ENOMEM;
2654         }
2655         return 0;
2656 }
2657
2658 static void nvme_release_prp_pools(struct nvme_dev *dev)
2659 {
2660         dma_pool_destroy(dev->prp_page_pool);
2661         dma_pool_destroy(dev->prp_small_pool);
2662 }
2663
2664 static void nvme_free_tagset(struct nvme_dev *dev)
2665 {
2666         if (dev->tagset.tags)
2667                 blk_mq_free_tag_set(&dev->tagset);
2668         dev->ctrl.tagset = NULL;
2669 }
2670
2671 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2672 {
2673         struct nvme_dev *dev = to_nvme_dev(ctrl);
2674
2675         nvme_dbbuf_dma_free(dev);
2676         nvme_free_tagset(dev);
2677         if (dev->ctrl.admin_q)
2678                 blk_put_queue(dev->ctrl.admin_q);
2679         free_opal_dev(dev->ctrl.opal_dev);
2680         mempool_destroy(dev->iod_mempool);
2681         put_device(dev->dev);
2682         kfree(dev->queues);
2683         kfree(dev);
2684 }
2685
2686 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2687 {
2688         /*
2689          * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2690          * may be holding this pci_dev's device lock.
2691          */
2692         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2693         nvme_get_ctrl(&dev->ctrl);
2694         nvme_dev_disable(dev, false);
2695         nvme_kill_queues(&dev->ctrl);
2696         if (!queue_work(nvme_wq, &dev->remove_work))
2697                 nvme_put_ctrl(&dev->ctrl);
2698 }
2699
2700 static void nvme_reset_work(struct work_struct *work)
2701 {
2702         struct nvme_dev *dev =
2703                 container_of(work, struct nvme_dev, ctrl.reset_work);
2704         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2705         int result;
2706
2707         if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2708                 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2709                          dev->ctrl.state);
2710                 result = -ENODEV;
2711                 goto out;
2712         }
2713
2714         /*
2715          * If we're called to reset a live controller first shut it down before
2716          * moving on.
2717          */
2718         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2719                 nvme_dev_disable(dev, false);
2720         nvme_sync_queues(&dev->ctrl);
2721
2722         mutex_lock(&dev->shutdown_lock);
2723         result = nvme_pci_enable(dev);
2724         if (result)
2725                 goto out_unlock;
2726
2727         result = nvme_pci_configure_admin_queue(dev);
2728         if (result)
2729                 goto out_unlock;
2730
2731         result = nvme_alloc_admin_tags(dev);
2732         if (result)
2733                 goto out_unlock;
2734
2735         dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
2736
2737         /*
2738          * Limit the max command size to prevent iod->sg allocations going
2739          * over a single page.
2740          */
2741         dev->ctrl.max_hw_sectors = min_t(u32,
2742                 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2743         dev->ctrl.max_segments = NVME_MAX_SEGS;
2744
2745         /*
2746          * Don't limit the IOMMU merged segment size.
2747          */
2748         dma_set_max_seg_size(dev->dev, 0xffffffff);
2749
2750         mutex_unlock(&dev->shutdown_lock);
2751
2752         /*
2753          * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2754          * initializing procedure here.
2755          */
2756         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2757                 dev_warn(dev->ctrl.device,
2758                         "failed to mark controller CONNECTING\n");
2759                 result = -EBUSY;
2760                 goto out;
2761         }
2762
2763         /*
2764          * We do not support an SGL for metadata (yet), so we are limited to a
2765          * single integrity segment for the separate metadata pointer.
2766          */
2767         dev->ctrl.max_integrity_segments = 1;
2768
2769         result = nvme_init_ctrl_finish(&dev->ctrl);
2770         if (result)
2771                 goto out;
2772
2773         if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2774                 if (!dev->ctrl.opal_dev)
2775                         dev->ctrl.opal_dev =
2776                                 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2777                 else if (was_suspend)
2778                         opal_unlock_from_suspend(dev->ctrl.opal_dev);
2779         } else {
2780                 free_opal_dev(dev->ctrl.opal_dev);
2781                 dev->ctrl.opal_dev = NULL;
2782         }
2783
2784         if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2785                 result = nvme_dbbuf_dma_alloc(dev);
2786                 if (result)
2787                         dev_warn(dev->dev,
2788                                  "unable to allocate dma for dbbuf\n");
2789         }
2790
2791         if (dev->ctrl.hmpre) {
2792                 result = nvme_setup_host_mem(dev);
2793                 if (result < 0)
2794                         goto out;
2795         }
2796
2797         result = nvme_setup_io_queues(dev);
2798         if (result)
2799                 goto out;
2800
2801         /*
2802          * Keep the controller around but remove all namespaces if we don't have
2803          * any working I/O queue.
2804          */
2805         if (dev->online_queues < 2) {
2806                 dev_warn(dev->ctrl.device, "IO queues not created\n");
2807                 nvme_kill_queues(&dev->ctrl);
2808                 nvme_remove_namespaces(&dev->ctrl);
2809                 nvme_free_tagset(dev);
2810         } else {
2811                 nvme_start_queues(&dev->ctrl);
2812                 nvme_wait_freeze(&dev->ctrl);
2813                 nvme_dev_add(dev);
2814                 nvme_unfreeze(&dev->ctrl);
2815         }
2816
2817         /*
2818          * If only admin queue live, keep it to do further investigation or
2819          * recovery.
2820          */
2821         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2822                 dev_warn(dev->ctrl.device,
2823                         "failed to mark controller live state\n");
2824                 result = -ENODEV;
2825                 goto out;
2826         }
2827
2828         if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj,
2829                         &nvme_pci_attr_group))
2830                 dev->attrs_added = true;
2831
2832         nvme_start_ctrl(&dev->ctrl);
2833         return;
2834
2835  out_unlock:
2836         mutex_unlock(&dev->shutdown_lock);
2837  out:
2838         if (result)
2839                 dev_warn(dev->ctrl.device,
2840                          "Removing after probe failure status: %d\n", result);
2841         nvme_remove_dead_ctrl(dev);
2842 }
2843
2844 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2845 {
2846         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2847         struct pci_dev *pdev = to_pci_dev(dev->dev);
2848
2849         if (pci_get_drvdata(pdev))
2850                 device_release_driver(&pdev->dev);
2851         nvme_put_ctrl(&dev->ctrl);
2852 }
2853
2854 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2855 {
2856         *val = readl(to_nvme_dev(ctrl)->bar + off);
2857         return 0;
2858 }
2859
2860 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2861 {
2862         writel(val, to_nvme_dev(ctrl)->bar + off);
2863         return 0;
2864 }
2865
2866 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2867 {
2868         *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2869         return 0;
2870 }
2871
2872 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2873 {
2874         struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2875
2876         return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2877 }
2878
2879 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2880         .name                   = "pcie",
2881         .module                 = THIS_MODULE,
2882         .flags                  = NVME_F_METADATA_SUPPORTED |
2883                                   NVME_F_PCI_P2PDMA,
2884         .reg_read32             = nvme_pci_reg_read32,
2885         .reg_write32            = nvme_pci_reg_write32,
2886         .reg_read64             = nvme_pci_reg_read64,
2887         .free_ctrl              = nvme_pci_free_ctrl,
2888         .submit_async_event     = nvme_pci_submit_async_event,
2889         .get_address            = nvme_pci_get_address,
2890 };
2891
2892 static int nvme_dev_map(struct nvme_dev *dev)
2893 {
2894         struct pci_dev *pdev = to_pci_dev(dev->dev);
2895
2896         if (pci_request_mem_regions(pdev, "nvme"))
2897                 return -ENODEV;
2898
2899         if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2900                 goto release;
2901
2902         return 0;
2903   release:
2904         pci_release_mem_regions(pdev);
2905         return -ENODEV;
2906 }
2907
2908 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2909 {
2910         if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2911                 /*
2912                  * Several Samsung devices seem to drop off the PCIe bus
2913                  * randomly when APST is on and uses the deepest sleep state.
2914                  * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2915                  * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2916                  * 950 PRO 256GB", but it seems to be restricted to two Dell
2917                  * laptops.
2918                  */
2919                 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2920                     (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2921                      dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2922                         return NVME_QUIRK_NO_DEEPEST_PS;
2923         } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2924                 /*
2925                  * Samsung SSD 960 EVO drops off the PCIe bus after system
2926                  * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2927                  * within few minutes after bootup on a Coffee Lake board -
2928                  * ASUS PRIME Z370-A
2929                  */
2930                 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2931                     (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2932                      dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2933                         return NVME_QUIRK_NO_APST;
2934         } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2935                     pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2936                    (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2937                 /*
2938                  * Forcing to use host managed nvme power settings for
2939                  * lowest idle power with quick resume latency on
2940                  * Samsung and Toshiba SSDs based on suspend behavior
2941                  * on Coffee Lake board for LENOVO C640
2942                  */
2943                 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2944                      dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2945                         return NVME_QUIRK_SIMPLE_SUSPEND;
2946         }
2947
2948         return 0;
2949 }
2950
2951 static void nvme_async_probe(void *data, async_cookie_t cookie)
2952 {
2953         struct nvme_dev *dev = data;
2954
2955         flush_work(&dev->ctrl.reset_work);
2956         flush_work(&dev->ctrl.scan_work);
2957         nvme_put_ctrl(&dev->ctrl);
2958 }
2959
2960 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2961 {
2962         int node, result = -ENOMEM;
2963         struct nvme_dev *dev;
2964         unsigned long quirks = id->driver_data;
2965         size_t alloc_size;
2966
2967         node = dev_to_node(&pdev->dev);
2968         if (node == NUMA_NO_NODE)
2969                 set_dev_node(&pdev->dev, first_memory_node);
2970
2971         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2972         if (!dev)
2973                 return -ENOMEM;
2974
2975         dev->nr_write_queues = write_queues;
2976         dev->nr_poll_queues = poll_queues;
2977         dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2978         dev->queues = kcalloc_node(dev->nr_allocated_queues,
2979                         sizeof(struct nvme_queue), GFP_KERNEL, node);
2980         if (!dev->queues)
2981                 goto free;
2982
2983         dev->dev = get_device(&pdev->dev);
2984         pci_set_drvdata(pdev, dev);
2985
2986         result = nvme_dev_map(dev);
2987         if (result)
2988                 goto put_pci;
2989
2990         INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2991         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2992         mutex_init(&dev->shutdown_lock);
2993
2994         result = nvme_setup_prp_pools(dev);
2995         if (result)
2996                 goto unmap;
2997
2998         quirks |= check_vendor_combination_bug(pdev);
2999
3000         if (!noacpi && acpi_storage_d3(&pdev->dev)) {
3001                 /*
3002                  * Some systems use a bios work around to ask for D3 on
3003                  * platforms that support kernel managed suspend.
3004                  */
3005                 dev_info(&pdev->dev,
3006                          "platform quirk: setting simple suspend\n");
3007                 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
3008         }
3009
3010         /*
3011          * Double check that our mempool alloc size will cover the biggest
3012          * command we support.
3013          */
3014         alloc_size = nvme_pci_iod_alloc_size();
3015         WARN_ON_ONCE(alloc_size > PAGE_SIZE);
3016
3017         dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
3018                                                 mempool_kfree,
3019                                                 (void *) alloc_size,
3020                                                 GFP_KERNEL, node);
3021         if (!dev->iod_mempool) {
3022                 result = -ENOMEM;
3023                 goto release_pools;
3024         }
3025
3026         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
3027                         quirks);
3028         if (result)
3029                 goto release_mempool;
3030
3031         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3032
3033         nvme_reset_ctrl(&dev->ctrl);
3034         async_schedule(nvme_async_probe, dev);
3035
3036         return 0;
3037
3038  release_mempool:
3039         mempool_destroy(dev->iod_mempool);
3040  release_pools:
3041         nvme_release_prp_pools(dev);
3042  unmap:
3043         nvme_dev_unmap(dev);
3044  put_pci:
3045         put_device(dev->dev);
3046  free:
3047         kfree(dev->queues);
3048         kfree(dev);
3049         return result;
3050 }
3051
3052 static void nvme_reset_prepare(struct pci_dev *pdev)
3053 {
3054         struct nvme_dev *dev = pci_get_drvdata(pdev);
3055
3056         /*
3057          * We don't need to check the return value from waiting for the reset
3058          * state as pci_dev device lock is held, making it impossible to race
3059          * with ->remove().
3060          */
3061         nvme_disable_prepare_reset(dev, false);
3062         nvme_sync_queues(&dev->ctrl);
3063 }
3064
3065 static void nvme_reset_done(struct pci_dev *pdev)
3066 {
3067         struct nvme_dev *dev = pci_get_drvdata(pdev);
3068
3069         if (!nvme_try_sched_reset(&dev->ctrl))
3070                 flush_work(&dev->ctrl.reset_work);
3071 }
3072
3073 static void nvme_shutdown(struct pci_dev *pdev)
3074 {
3075         struct nvme_dev *dev = pci_get_drvdata(pdev);
3076
3077         nvme_disable_prepare_reset(dev, true);
3078 }
3079
3080 static void nvme_remove_attrs(struct nvme_dev *dev)
3081 {
3082         if (dev->attrs_added)
3083                 sysfs_remove_group(&dev->ctrl.device->kobj,
3084                                    &nvme_pci_attr_group);
3085 }
3086
3087 /*
3088  * The driver's remove may be called on a device in a partially initialized
3089  * state. This function must not have any dependencies on the device state in
3090  * order to proceed.
3091  */
3092 static void nvme_remove(struct pci_dev *pdev)
3093 {
3094         struct nvme_dev *dev = pci_get_drvdata(pdev);
3095
3096         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3097         pci_set_drvdata(pdev, NULL);
3098
3099         if (!pci_device_is_present(pdev)) {
3100                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3101                 nvme_dev_disable(dev, true);
3102         }
3103
3104         flush_work(&dev->ctrl.reset_work);
3105         nvme_stop_ctrl(&dev->ctrl);
3106         nvme_remove_namespaces(&dev->ctrl);
3107         nvme_dev_disable(dev, true);
3108         nvme_remove_attrs(dev);
3109         nvme_free_host_mem(dev);
3110         nvme_dev_remove_admin(dev);
3111         nvme_free_queues(dev, 0);
3112         nvme_release_prp_pools(dev);
3113         nvme_dev_unmap(dev);
3114         nvme_uninit_ctrl(&dev->ctrl);
3115 }
3116
3117 #ifdef CONFIG_PM_SLEEP
3118 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3119 {
3120         return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3121 }
3122
3123 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3124 {
3125         return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3126 }
3127
3128 static int nvme_resume(struct device *dev)
3129 {
3130         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3131         struct nvme_ctrl *ctrl = &ndev->ctrl;
3132
3133         if (ndev->last_ps == U32_MAX ||
3134             nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3135                 goto reset;
3136         if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3137                 goto reset;
3138
3139         return 0;
3140 reset:
3141         return nvme_try_sched_reset(ctrl);
3142 }
3143
3144 static int nvme_suspend(struct device *dev)
3145 {
3146         struct pci_dev *pdev = to_pci_dev(dev);
3147         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3148         struct nvme_ctrl *ctrl = &ndev->ctrl;
3149         int ret = -EBUSY;
3150
3151         ndev->last_ps = U32_MAX;
3152
3153         /*
3154          * The platform does not remove power for a kernel managed suspend so
3155          * use host managed nvme power settings for lowest idle power if
3156          * possible. This should have quicker resume latency than a full device
3157          * shutdown.  But if the firmware is involved after the suspend or the
3158          * device does not support any non-default power states, shut down the
3159          * device fully.
3160          *
3161          * If ASPM is not enabled for the device, shut down the device and allow
3162          * the PCI bus layer to put it into D3 in order to take the PCIe link
3163          * down, so as to allow the platform to achieve its minimum low-power
3164          * state (which may not be possible if the link is up).
3165          */
3166         if (pm_suspend_via_firmware() || !ctrl->npss ||
3167             !pcie_aspm_enabled(pdev) ||
3168             (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3169                 return nvme_disable_prepare_reset(ndev, true);
3170
3171         nvme_start_freeze(ctrl);
3172         nvme_wait_freeze(ctrl);
3173         nvme_sync_queues(ctrl);
3174
3175         if (ctrl->state != NVME_CTRL_LIVE)
3176                 goto unfreeze;
3177
3178         /*
3179          * Host memory access may not be successful in a system suspend state,
3180          * but the specification allows the controller to access memory in a
3181          * non-operational power state.
3182          */
3183         if (ndev->hmb) {
3184                 ret = nvme_set_host_mem(ndev, 0);
3185                 if (ret < 0)
3186                         goto unfreeze;
3187         }
3188
3189         ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3190         if (ret < 0)
3191                 goto unfreeze;
3192
3193         /*
3194          * A saved state prevents pci pm from generically controlling the
3195          * device's power. If we're using protocol specific settings, we don't
3196          * want pci interfering.
3197          */
3198         pci_save_state(pdev);
3199
3200         ret = nvme_set_power_state(ctrl, ctrl->npss);
3201         if (ret < 0)
3202                 goto unfreeze;
3203
3204         if (ret) {
3205                 /* discard the saved state */
3206                 pci_load_saved_state(pdev, NULL);
3207
3208                 /*
3209                  * Clearing npss forces a controller reset on resume. The
3210                  * correct value will be rediscovered then.
3211                  */
3212                 ret = nvme_disable_prepare_reset(ndev, true);
3213                 ctrl->npss = 0;
3214         }
3215 unfreeze:
3216         nvme_unfreeze(ctrl);
3217         return ret;
3218 }
3219
3220 static int nvme_simple_suspend(struct device *dev)
3221 {
3222         struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3223
3224         return nvme_disable_prepare_reset(ndev, true);
3225 }
3226
3227 static int nvme_simple_resume(struct device *dev)
3228 {
3229         struct pci_dev *pdev = to_pci_dev(dev);
3230         struct nvme_dev *ndev = pci_get_drvdata(pdev);
3231
3232         return nvme_try_sched_reset(&ndev->ctrl);
3233 }
3234
3235 static const struct dev_pm_ops nvme_dev_pm_ops = {
3236         .suspend        = nvme_suspend,
3237         .resume         = nvme_resume,
3238         .freeze         = nvme_simple_suspend,
3239         .thaw           = nvme_simple_resume,
3240         .poweroff       = nvme_simple_suspend,
3241         .restore        = nvme_simple_resume,
3242 };
3243 #endif /* CONFIG_PM_SLEEP */
3244
3245 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3246                                                 pci_channel_state_t state)
3247 {
3248         struct nvme_dev *dev = pci_get_drvdata(pdev);
3249
3250         /*
3251          * A frozen channel requires a reset. When detected, this method will
3252          * shutdown the controller to quiesce. The controller will be restarted
3253          * after the slot reset through driver's slot_reset callback.
3254          */
3255         switch (state) {
3256         case pci_channel_io_normal:
3257                 return PCI_ERS_RESULT_CAN_RECOVER;
3258         case pci_channel_io_frozen:
3259                 dev_warn(dev->ctrl.device,
3260                         "frozen state error detected, reset controller\n");
3261                 nvme_dev_disable(dev, false);
3262                 return PCI_ERS_RESULT_NEED_RESET;
3263         case pci_channel_io_perm_failure:
3264                 dev_warn(dev->ctrl.device,
3265                         "failure state error detected, request disconnect\n");
3266                 return PCI_ERS_RESULT_DISCONNECT;
3267         }
3268         return PCI_ERS_RESULT_NEED_RESET;
3269 }
3270
3271 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3272 {
3273         struct nvme_dev *dev = pci_get_drvdata(pdev);
3274
3275         dev_info(dev->ctrl.device, "restart after slot reset\n");
3276         pci_restore_state(pdev);
3277         nvme_reset_ctrl(&dev->ctrl);
3278         return PCI_ERS_RESULT_RECOVERED;
3279 }
3280
3281 static void nvme_error_resume(struct pci_dev *pdev)
3282 {
3283         struct nvme_dev *dev = pci_get_drvdata(pdev);
3284
3285         flush_work(&dev->ctrl.reset_work);
3286 }
3287
3288 static const struct pci_error_handlers nvme_err_handler = {
3289         .error_detected = nvme_error_detected,
3290         .slot_reset     = nvme_slot_reset,
3291         .resume         = nvme_error_resume,
3292         .reset_prepare  = nvme_reset_prepare,
3293         .reset_done     = nvme_reset_done,
3294 };
3295
3296 static const struct pci_device_id nvme_id_table[] = {
3297         { PCI_VDEVICE(INTEL, 0x0953),   /* Intel 750/P3500/P3600/P3700 */
3298                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3299                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3300         { PCI_VDEVICE(INTEL, 0x0a53),   /* Intel P3520 */
3301                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3302                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3303         { PCI_VDEVICE(INTEL, 0x0a54),   /* Intel P4500/P4600 */
3304                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3305                                 NVME_QUIRK_DEALLOCATE_ZEROES |
3306                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3307         { PCI_VDEVICE(INTEL, 0x0a55),   /* Dell Express Flash P4600 */
3308                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3309                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
3310         { PCI_VDEVICE(INTEL, 0xf1a5),   /* Intel 600P/P3100 */
3311                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3312                                 NVME_QUIRK_MEDIUM_PRIO_SQ |
3313                                 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3314                                 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3315         { PCI_VDEVICE(INTEL, 0xf1a6),   /* Intel 760p/Pro 7600p */
3316                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3317         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
3318                 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3319                                 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3320                                 NVME_QUIRK_BOGUS_NID, },
3321         { PCI_VDEVICE(REDHAT, 0x0010),  /* Qemu emulated controller */
3322                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3323         { PCI_DEVICE(0x126f, 0x2263),   /* Silicon Motion unidentified */
3324                 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
3325         { PCI_DEVICE(0x1bb1, 0x0100),   /* Seagate Nytro Flash Storage */
3326                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3327                                 NVME_QUIRK_NO_NS_DESC_LIST, },
3328         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
3329                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3330         { PCI_DEVICE(0x1c58, 0x0023),   /* WDC SN200 adapter */
3331                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3332         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
3333                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3334         { PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
3335                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3336         { PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
3337                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3338                                 NVME_QUIRK_DISABLE_WRITE_ZEROES|
3339                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3340         { PCI_DEVICE(0x1987, 0x5016),   /* Phison E16 */
3341                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3342                                 NVME_QUIRK_BOGUS_NID, },
3343         { PCI_DEVICE(0x1b4b, 0x1092),   /* Lexar 256 GB SSD */
3344                 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3345                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3346         { PCI_DEVICE(0x1cc1, 0x33f8),   /* ADATA IM2P33F8ABR1 1 TB */
3347                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3348         { PCI_DEVICE(0x10ec, 0x5762),   /* ADATA SX6000LNP */
3349                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3350                                 NVME_QUIRK_BOGUS_NID, },
3351         { PCI_DEVICE(0x1cc1, 0x8201),   /* ADATA SX8200PNP 512GB */
3352                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3353                                 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3354          { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3355                 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
3356          { PCI_DEVICE(0x1344, 0x6001),   /* Micron Nitro NVMe */
3357                  .driver_data = NVME_QUIRK_BOGUS_NID, },
3358         { PCI_DEVICE(0x1c5c, 0x1504),   /* SK Hynix PC400 */
3359                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3360         { PCI_DEVICE(0x15b7, 0x2001),   /*  Sandisk Skyhawk */
3361                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3362         { PCI_DEVICE(0x1d97, 0x2263),   /* SPCC */
3363                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3364         { PCI_DEVICE(0x2646, 0x2262),   /* KINGSTON SKC2000 NVMe SSD */
3365                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3366         { PCI_DEVICE(0x2646, 0x2263),   /* KINGSTON A2000 NVMe SSD  */
3367                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3368         { PCI_DEVICE(0x2646, 0x5018),   /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */
3369                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3370         { PCI_DEVICE(0x2646, 0x5016),   /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */
3371                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3372         { PCI_DEVICE(0x2646, 0x501A),   /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */
3373                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3374         { PCI_DEVICE(0x2646, 0x501B),   /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */
3375                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3376         { PCI_DEVICE(0x2646, 0x501E),   /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */
3377                 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3378         { PCI_DEVICE(0x1f40, 0x5236),   /* Netac Technologies Co. NV7000 NVMe SSD */
3379                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3380         { PCI_DEVICE(0x1e4B, 0x1001),   /* MAXIO MAP1001 */
3381                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3382         { PCI_DEVICE(0x1e4B, 0x1002),   /* MAXIO MAP1002 */
3383                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3384         { PCI_DEVICE(0x1e4B, 0x1202),   /* MAXIO MAP1202 */
3385                 .driver_data = NVME_QUIRK_BOGUS_NID, },
3386         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3387                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3388         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3389                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3390         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3391                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3392         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3393                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3394         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3395                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3396         { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3397                 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3398         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3399                 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3400         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3401         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3402                 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3403                                 NVME_QUIRK_128_BYTES_SQES |
3404                                 NVME_QUIRK_SHARED_TAGS |
3405                                 NVME_QUIRK_SKIP_CID_GEN },
3406         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3407         { 0, }
3408 };
3409 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3410
3411 static struct pci_driver nvme_driver = {
3412         .name           = "nvme",
3413         .id_table       = nvme_id_table,
3414         .probe          = nvme_probe,
3415         .remove         = nvme_remove,
3416         .shutdown       = nvme_shutdown,
3417 #ifdef CONFIG_PM_SLEEP
3418         .driver         = {
3419                 .pm     = &nvme_dev_pm_ops,
3420         },
3421 #endif
3422         .sriov_configure = pci_sriov_configure_simple,
3423         .err_handler    = &nvme_err_handler,
3424 };
3425
3426 static int __init nvme_init(void)
3427 {
3428         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3429         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3430         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3431         BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3432
3433         return pci_register_driver(&nvme_driver);
3434 }
3435
3436 static void __exit nvme_exit(void)
3437 {
3438         pci_unregister_driver(&nvme_driver);
3439         flush_workqueue(nvme_wq);
3440 }
3441
3442 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3443 MODULE_LICENSE("GPL");
3444 MODULE_VERSION("1.0");
3445 module_init(nvme_init);
3446 module_exit(nvme_exit);