1 // SPDX-License-Identifier: GPL-2.0
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
7 #include <linux/acpi.h>
9 #include <linux/async.h>
10 #include <linux/blkdev.h>
11 #include <linux/blk-mq.h>
12 #include <linux/blk-mq-pci.h>
13 #include <linux/dmi.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
18 #include <linux/module.h>
19 #include <linux/mutex.h>
20 #include <linux/once.h>
21 #include <linux/pci.h>
22 #include <linux/suspend.h>
23 #include <linux/t10-pi.h>
24 #include <linux/types.h>
25 #include <linux/io-64-nonatomic-lo-hi.h>
26 #include <linux/io-64-nonatomic-hi-lo.h>
27 #include <linux/sed-opal.h>
28 #include <linux/pci-p2pdma.h>
33 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
34 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
36 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
39 * These can be higher, but we need to ensure that any command doesn't
40 * require an sg allocation that needs more than a page of data.
42 #define NVME_MAX_KB_SZ 4096
43 #define NVME_MAX_SEGS 127
45 static int use_threaded_interrupts;
46 module_param(use_threaded_interrupts, int, 0);
48 static bool use_cmb_sqes = true;
49 module_param(use_cmb_sqes, bool, 0444);
50 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
52 static unsigned int max_host_mem_size_mb = 128;
53 module_param(max_host_mem_size_mb, uint, 0444);
54 MODULE_PARM_DESC(max_host_mem_size_mb,
55 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
57 static unsigned int sgl_threshold = SZ_32K;
58 module_param(sgl_threshold, uint, 0644);
59 MODULE_PARM_DESC(sgl_threshold,
60 "Use SGLs when average request segment size is larger or equal to "
61 "this size. Use 0 to disable SGLs.");
63 #define NVME_PCI_MIN_QUEUE_SIZE 2
64 #define NVME_PCI_MAX_QUEUE_SIZE 4095
65 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
66 static const struct kernel_param_ops io_queue_depth_ops = {
67 .set = io_queue_depth_set,
68 .get = param_get_uint,
71 static unsigned int io_queue_depth = 1024;
72 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
73 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
75 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
80 ret = kstrtouint(val, 10, &n);
81 if (ret != 0 || n > num_possible_cpus())
83 return param_set_uint(val, kp);
86 static const struct kernel_param_ops io_queue_count_ops = {
87 .set = io_queue_count_set,
88 .get = param_get_uint,
91 static unsigned int write_queues;
92 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
93 MODULE_PARM_DESC(write_queues,
94 "Number of queues to use for writes. If not set, reads and writes "
95 "will share a queue set.");
97 static unsigned int poll_queues;
98 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
99 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
102 module_param(noacpi, bool, 0444);
103 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
108 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
109 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
112 * Represents an NVM Express device. Each nvme_dev is a PCI function.
115 struct nvme_queue *queues;
116 struct blk_mq_tag_set tagset;
117 struct blk_mq_tag_set admin_tagset;
120 struct dma_pool *prp_page_pool;
121 struct dma_pool *prp_small_pool;
122 unsigned online_queues;
124 unsigned io_queues[HCTX_MAX_TYPES];
125 unsigned int num_vecs;
130 unsigned long bar_mapped_size;
131 struct work_struct remove_work;
132 struct mutex shutdown_lock;
138 struct nvme_ctrl ctrl;
142 mempool_t *iod_mempool;
144 /* shadow doorbell buffer support: */
146 dma_addr_t dbbuf_dbs_dma_addr;
148 dma_addr_t dbbuf_eis_dma_addr;
150 /* host memory buffer support: */
152 u32 nr_host_mem_descs;
153 dma_addr_t host_mem_descs_dma;
154 struct nvme_host_mem_buf_desc *host_mem_descs;
155 void **host_mem_desc_bufs;
156 unsigned int nr_allocated_queues;
157 unsigned int nr_write_queues;
158 unsigned int nr_poll_queues;
163 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
165 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
166 NVME_PCI_MAX_QUEUE_SIZE);
169 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
171 return qid * 2 * stride;
174 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
176 return (qid * 2 + 1) * stride;
179 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
181 return container_of(ctrl, struct nvme_dev, ctrl);
185 * An NVM Express queue. Each device has at least two (one for admin
186 * commands and one for I/O commands).
189 struct nvme_dev *dev;
192 /* only used for poll queues: */
193 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
194 struct nvme_completion *cqes;
195 dma_addr_t sq_dma_addr;
196 dma_addr_t cq_dma_addr;
207 #define NVMEQ_ENABLED 0
208 #define NVMEQ_SQ_CMB 1
209 #define NVMEQ_DELETE_ERROR 2
210 #define NVMEQ_POLLED 3
215 struct completion delete_done;
219 * The nvme_iod describes the data in an I/O.
221 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
222 * to the actual struct scatterlist.
225 struct nvme_request req;
226 struct nvme_command cmd;
227 struct nvme_queue *nvmeq;
230 int npages; /* In the PRP list. 0 means small pool in use */
231 int nents; /* Used in scatterlist */
232 dma_addr_t first_dma;
233 unsigned int dma_len; /* length of single DMA segment mapping */
235 struct scatterlist *sg;
238 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
240 return dev->nr_allocated_queues * 8 * dev->db_stride;
243 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
245 unsigned int mem_size = nvme_dbbuf_size(dev);
250 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
251 &dev->dbbuf_dbs_dma_addr,
255 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
256 &dev->dbbuf_eis_dma_addr,
258 if (!dev->dbbuf_eis) {
259 dma_free_coherent(dev->dev, mem_size,
260 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
261 dev->dbbuf_dbs = NULL;
268 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
270 unsigned int mem_size = nvme_dbbuf_size(dev);
272 if (dev->dbbuf_dbs) {
273 dma_free_coherent(dev->dev, mem_size,
274 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
275 dev->dbbuf_dbs = NULL;
277 if (dev->dbbuf_eis) {
278 dma_free_coherent(dev->dev, mem_size,
279 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
280 dev->dbbuf_eis = NULL;
284 static void nvme_dbbuf_init(struct nvme_dev *dev,
285 struct nvme_queue *nvmeq, int qid)
287 if (!dev->dbbuf_dbs || !qid)
290 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
291 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
292 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
293 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
296 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
301 nvmeq->dbbuf_sq_db = NULL;
302 nvmeq->dbbuf_cq_db = NULL;
303 nvmeq->dbbuf_sq_ei = NULL;
304 nvmeq->dbbuf_cq_ei = NULL;
307 static void nvme_dbbuf_set(struct nvme_dev *dev)
309 struct nvme_command c = { };
315 c.dbbuf.opcode = nvme_admin_dbbuf;
316 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
317 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
319 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
320 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
321 /* Free memory and continue on */
322 nvme_dbbuf_dma_free(dev);
324 for (i = 1; i <= dev->online_queues; i++)
325 nvme_dbbuf_free(&dev->queues[i]);
329 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
331 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
334 /* Update dbbuf and return true if an MMIO is required */
335 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
336 volatile u32 *dbbuf_ei)
342 * Ensure that the queue is written before updating
343 * the doorbell in memory
347 old_value = *dbbuf_db;
351 * Ensure that the doorbell is updated before reading the event
352 * index from memory. The controller needs to provide similar
353 * ordering to ensure the envent index is updated before reading
358 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
366 * Will slightly overestimate the number of pages needed. This is OK
367 * as it only leads to a small amount of wasted memory for the lifetime of
370 static int nvme_pci_npages_prp(void)
372 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
373 NVME_CTRL_PAGE_SIZE);
374 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
378 * Calculates the number of pages needed for the SGL segments. For example a 4k
379 * page can accommodate 256 SGL descriptors.
381 static int nvme_pci_npages_sgl(void)
383 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
387 static size_t nvme_pci_iod_alloc_size(void)
389 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
391 return sizeof(__le64 *) * npages +
392 sizeof(struct scatterlist) * NVME_MAX_SEGS;
395 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
396 unsigned int hctx_idx)
398 struct nvme_dev *dev = data;
399 struct nvme_queue *nvmeq = &dev->queues[0];
401 WARN_ON(hctx_idx != 0);
402 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
404 hctx->driver_data = nvmeq;
408 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
409 unsigned int hctx_idx)
411 struct nvme_dev *dev = data;
412 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
414 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
415 hctx->driver_data = nvmeq;
419 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
420 unsigned int hctx_idx, unsigned int numa_node)
422 struct nvme_dev *dev = set->driver_data;
423 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
424 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
425 struct nvme_queue *nvmeq = &dev->queues[queue_idx];
430 nvme_req(req)->ctrl = &dev->ctrl;
431 nvme_req(req)->cmd = &iod->cmd;
435 static int queue_irq_offset(struct nvme_dev *dev)
437 /* if we have more than 1 vec, admin queue offsets us by 1 */
438 if (dev->num_vecs > 1)
444 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
446 struct nvme_dev *dev = set->driver_data;
449 offset = queue_irq_offset(dev);
450 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
451 struct blk_mq_queue_map *map = &set->map[i];
453 map->nr_queues = dev->io_queues[i];
454 if (!map->nr_queues) {
455 BUG_ON(i == HCTX_TYPE_DEFAULT);
460 * The poll queue(s) doesn't have an IRQ (and hence IRQ
461 * affinity), so use the regular blk-mq cpu mapping
463 map->queue_offset = qoff;
464 if (i != HCTX_TYPE_POLL && offset)
465 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
467 blk_mq_map_queues(map);
468 qoff += map->nr_queues;
469 offset += map->nr_queues;
476 * Write sq tail if we are asked to, or if the next command would wrap.
478 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
481 u16 next_tail = nvmeq->sq_tail + 1;
483 if (next_tail == nvmeq->q_depth)
485 if (next_tail != nvmeq->last_sq_tail)
489 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
490 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
491 writel(nvmeq->sq_tail, nvmeq->q_db);
492 nvmeq->last_sq_tail = nvmeq->sq_tail;
496 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
497 * @nvmeq: The queue to use
498 * @cmd: The command to send
499 * @write_sq: whether to write to the SQ doorbell
501 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
504 spin_lock(&nvmeq->sq_lock);
505 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
507 if (++nvmeq->sq_tail == nvmeq->q_depth)
509 nvme_write_sq_db(nvmeq, write_sq);
510 spin_unlock(&nvmeq->sq_lock);
513 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
515 struct nvme_queue *nvmeq = hctx->driver_data;
517 spin_lock(&nvmeq->sq_lock);
518 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
519 nvme_write_sq_db(nvmeq, true);
520 spin_unlock(&nvmeq->sq_lock);
523 static void **nvme_pci_iod_list(struct request *req)
525 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
526 return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
529 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
531 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
532 int nseg = blk_rq_nr_phys_segments(req);
533 unsigned int avg_seg_size;
535 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
537 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
539 if (!iod->nvmeq->qid)
541 if (!sgl_threshold || avg_seg_size < sgl_threshold)
546 static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
548 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
549 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
550 dma_addr_t dma_addr = iod->first_dma;
553 for (i = 0; i < iod->npages; i++) {
554 __le64 *prp_list = nvme_pci_iod_list(req)[i];
555 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
557 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
558 dma_addr = next_dma_addr;
562 static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
564 const int last_sg = SGES_PER_PAGE - 1;
565 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
566 dma_addr_t dma_addr = iod->first_dma;
569 for (i = 0; i < iod->npages; i++) {
570 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
571 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
573 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
574 dma_addr = next_dma_addr;
578 static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
580 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
582 if (is_pci_p2pdma_page(sg_page(iod->sg)))
583 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
586 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
589 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
591 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
594 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
599 WARN_ON_ONCE(!iod->nents);
601 nvme_unmap_sg(dev, req);
602 if (iod->npages == 0)
603 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
605 else if (iod->use_sgl)
606 nvme_free_sgls(dev, req);
608 nvme_free_prps(dev, req);
609 mempool_free(iod->sg, dev->iod_mempool);
612 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
615 struct scatterlist *sg;
617 for_each_sg(sgl, sg, nents, i) {
618 dma_addr_t phys = sg_phys(sg);
619 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
620 "dma_address:%pad dma_length:%d\n",
621 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
626 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
627 struct request *req, struct nvme_rw_command *cmnd)
629 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
630 struct dma_pool *pool;
631 int length = blk_rq_payload_bytes(req);
632 struct scatterlist *sg = iod->sg;
633 int dma_len = sg_dma_len(sg);
634 u64 dma_addr = sg_dma_address(sg);
635 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
637 void **list = nvme_pci_iod_list(req);
641 length -= (NVME_CTRL_PAGE_SIZE - offset);
647 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
649 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
652 dma_addr = sg_dma_address(sg);
653 dma_len = sg_dma_len(sg);
656 if (length <= NVME_CTRL_PAGE_SIZE) {
657 iod->first_dma = dma_addr;
661 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
662 if (nprps <= (256 / 8)) {
663 pool = dev->prp_small_pool;
666 pool = dev->prp_page_pool;
670 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
672 iod->first_dma = dma_addr;
674 return BLK_STS_RESOURCE;
677 iod->first_dma = prp_dma;
680 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
681 __le64 *old_prp_list = prp_list;
682 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
685 list[iod->npages++] = prp_list;
686 prp_list[0] = old_prp_list[i - 1];
687 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
690 prp_list[i++] = cpu_to_le64(dma_addr);
691 dma_len -= NVME_CTRL_PAGE_SIZE;
692 dma_addr += NVME_CTRL_PAGE_SIZE;
693 length -= NVME_CTRL_PAGE_SIZE;
698 if (unlikely(dma_len < 0))
701 dma_addr = sg_dma_address(sg);
702 dma_len = sg_dma_len(sg);
705 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
706 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
709 nvme_free_prps(dev, req);
710 return BLK_STS_RESOURCE;
712 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
713 "Invalid SGL for payload:%d nents:%d\n",
714 blk_rq_payload_bytes(req), iod->nents);
715 return BLK_STS_IOERR;
718 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
719 struct scatterlist *sg)
721 sge->addr = cpu_to_le64(sg_dma_address(sg));
722 sge->length = cpu_to_le32(sg_dma_len(sg));
723 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
726 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
727 dma_addr_t dma_addr, int entries)
729 sge->addr = cpu_to_le64(dma_addr);
730 if (entries < SGES_PER_PAGE) {
731 sge->length = cpu_to_le32(entries * sizeof(*sge));
732 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
734 sge->length = cpu_to_le32(PAGE_SIZE);
735 sge->type = NVME_SGL_FMT_SEG_DESC << 4;
739 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
740 struct request *req, struct nvme_rw_command *cmd, int entries)
742 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
743 struct dma_pool *pool;
744 struct nvme_sgl_desc *sg_list;
745 struct scatterlist *sg = iod->sg;
749 /* setting the transfer type as SGL */
750 cmd->flags = NVME_CMD_SGL_METABUF;
753 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
757 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
758 pool = dev->prp_small_pool;
761 pool = dev->prp_page_pool;
765 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
768 return BLK_STS_RESOURCE;
771 nvme_pci_iod_list(req)[0] = sg_list;
772 iod->first_dma = sgl_dma;
774 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
777 if (i == SGES_PER_PAGE) {
778 struct nvme_sgl_desc *old_sg_desc = sg_list;
779 struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
781 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
786 nvme_pci_iod_list(req)[iod->npages++] = sg_list;
787 sg_list[i++] = *link;
788 nvme_pci_sgl_set_seg(link, sgl_dma, entries);
791 nvme_pci_sgl_set_data(&sg_list[i++], sg);
793 } while (--entries > 0);
797 nvme_free_sgls(dev, req);
798 return BLK_STS_RESOURCE;
801 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
802 struct request *req, struct nvme_rw_command *cmnd,
805 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
806 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
807 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
809 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
810 if (dma_mapping_error(dev->dev, iod->first_dma))
811 return BLK_STS_RESOURCE;
812 iod->dma_len = bv->bv_len;
814 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
815 if (bv->bv_len > first_prp_len)
816 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
820 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
821 struct request *req, struct nvme_rw_command *cmnd,
824 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
826 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
827 if (dma_mapping_error(dev->dev, iod->first_dma))
828 return BLK_STS_RESOURCE;
829 iod->dma_len = bv->bv_len;
831 cmnd->flags = NVME_CMD_SGL_METABUF;
832 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
833 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
834 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
838 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
839 struct nvme_command *cmnd)
841 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
842 blk_status_t ret = BLK_STS_RESOURCE;
845 if (blk_rq_nr_phys_segments(req) == 1) {
846 struct bio_vec bv = req_bvec(req);
848 if (!is_pci_p2pdma_page(bv.bv_page)) {
849 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
850 return nvme_setup_prp_simple(dev, req,
853 if (iod->nvmeq->qid && sgl_threshold &&
854 nvme_ctrl_sgl_supported(&dev->ctrl))
855 return nvme_setup_sgl_simple(dev, req,
861 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
863 return BLK_STS_RESOURCE;
864 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
865 iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
869 if (is_pci_p2pdma_page(sg_page(iod->sg)))
870 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
871 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
873 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
874 rq_dma_dir(req), DMA_ATTR_NO_WARN);
878 iod->use_sgl = nvme_pci_use_sgls(dev, req);
880 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
882 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
883 if (ret != BLK_STS_OK)
888 nvme_unmap_sg(dev, req);
890 mempool_free(iod->sg, dev->iod_mempool);
894 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
895 struct nvme_command *cmnd)
897 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
899 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
901 if (dma_mapping_error(dev->dev, iod->meta_dma))
902 return BLK_STS_IOERR;
903 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
908 * NOTE: ns is NULL when called on the admin queue.
910 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
911 const struct blk_mq_queue_data *bd)
913 struct nvme_ns *ns = hctx->queue->queuedata;
914 struct nvme_queue *nvmeq = hctx->driver_data;
915 struct nvme_dev *dev = nvmeq->dev;
916 struct request *req = bd->rq;
917 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
918 struct nvme_command *cmnd = &iod->cmd;
926 * We should not need to do this, but we're still using this to
927 * ensure we can drain requests on a dying queue.
929 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
930 return BLK_STS_IOERR;
932 if (!nvme_check_ready(&dev->ctrl, req, true))
933 return nvme_fail_nonready_command(&dev->ctrl, req);
935 ret = nvme_setup_cmd(ns, req);
939 if (blk_rq_nr_phys_segments(req)) {
940 ret = nvme_map_data(dev, req, cmnd);
945 if (blk_integrity_rq(req)) {
946 ret = nvme_map_metadata(dev, req, cmnd);
951 blk_mq_start_request(req);
952 nvme_submit_cmd(nvmeq, cmnd, bd->last);
955 nvme_unmap_data(dev, req);
957 nvme_cleanup_cmd(req);
961 static void nvme_pci_complete_rq(struct request *req)
963 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
964 struct nvme_dev *dev = iod->nvmeq->dev;
966 if (blk_integrity_rq(req))
967 dma_unmap_page(dev->dev, iod->meta_dma,
968 rq_integrity_vec(req)->bv_len, rq_data_dir(req));
969 if (blk_rq_nr_phys_segments(req))
970 nvme_unmap_data(dev, req);
971 nvme_complete_rq(req);
974 /* We read the CQE phase first to check if the rest of the entry is valid */
975 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
977 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
979 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
982 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
984 u16 head = nvmeq->cq_head;
986 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
988 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
991 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
994 return nvmeq->dev->admin_tagset.tags[0];
995 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
998 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
1000 struct nvme_completion *cqe = &nvmeq->cqes[idx];
1001 __u16 command_id = READ_ONCE(cqe->command_id);
1002 struct request *req;
1005 * AEN requests are special as they don't time out and can
1006 * survive any kind of queue freeze and often don't respond to
1007 * aborts. We don't even bother to allocate a struct request
1008 * for them but rather special case them here.
1010 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1011 nvme_complete_async_event(&nvmeq->dev->ctrl,
1012 cqe->status, &cqe->result);
1016 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
1017 if (unlikely(!req)) {
1018 dev_warn(nvmeq->dev->ctrl.device,
1019 "invalid id %d completed on queue %d\n",
1020 command_id, le16_to_cpu(cqe->sq_id));
1024 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1025 if (!nvme_try_complete_req(req, cqe->status, cqe->result))
1026 nvme_pci_complete_rq(req);
1029 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1031 u32 tmp = nvmeq->cq_head + 1;
1033 if (tmp == nvmeq->q_depth) {
1035 nvmeq->cq_phase ^= 1;
1037 nvmeq->cq_head = tmp;
1041 static inline int nvme_process_cq(struct nvme_queue *nvmeq)
1045 while (nvme_cqe_pending(nvmeq)) {
1048 * load-load control dependency between phase and the rest of
1049 * the cqe requires a full read memory barrier
1052 nvme_handle_cqe(nvmeq, nvmeq->cq_head);
1053 nvme_update_cq_head(nvmeq);
1057 nvme_ring_cq_doorbell(nvmeq);
1061 static irqreturn_t nvme_irq(int irq, void *data)
1063 struct nvme_queue *nvmeq = data;
1065 if (nvme_process_cq(nvmeq))
1070 static irqreturn_t nvme_irq_check(int irq, void *data)
1072 struct nvme_queue *nvmeq = data;
1074 if (nvme_cqe_pending(nvmeq))
1075 return IRQ_WAKE_THREAD;
1080 * Poll for completions for any interrupt driven queue
1081 * Can be called from any context.
1083 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1085 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1087 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1089 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1090 nvme_process_cq(nvmeq);
1091 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1094 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1096 struct nvme_queue *nvmeq = hctx->driver_data;
1099 if (!nvme_cqe_pending(nvmeq))
1102 spin_lock(&nvmeq->cq_poll_lock);
1103 found = nvme_process_cq(nvmeq);
1104 spin_unlock(&nvmeq->cq_poll_lock);
1109 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1111 struct nvme_dev *dev = to_nvme_dev(ctrl);
1112 struct nvme_queue *nvmeq = &dev->queues[0];
1113 struct nvme_command c = { };
1115 c.common.opcode = nvme_admin_async_event;
1116 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1117 nvme_submit_cmd(nvmeq, &c, true);
1120 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1122 struct nvme_command c = { };
1124 c.delete_queue.opcode = opcode;
1125 c.delete_queue.qid = cpu_to_le16(id);
1127 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1130 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1131 struct nvme_queue *nvmeq, s16 vector)
1133 struct nvme_command c = { };
1134 int flags = NVME_QUEUE_PHYS_CONTIG;
1136 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1137 flags |= NVME_CQ_IRQ_ENABLED;
1140 * Note: we (ab)use the fact that the prp fields survive if no data
1141 * is attached to the request.
1143 c.create_cq.opcode = nvme_admin_create_cq;
1144 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1145 c.create_cq.cqid = cpu_to_le16(qid);
1146 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1147 c.create_cq.cq_flags = cpu_to_le16(flags);
1148 c.create_cq.irq_vector = cpu_to_le16(vector);
1150 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1153 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1154 struct nvme_queue *nvmeq)
1156 struct nvme_ctrl *ctrl = &dev->ctrl;
1157 struct nvme_command c = { };
1158 int flags = NVME_QUEUE_PHYS_CONTIG;
1161 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1162 * set. Since URGENT priority is zeroes, it makes all queues
1165 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1166 flags |= NVME_SQ_PRIO_MEDIUM;
1169 * Note: we (ab)use the fact that the prp fields survive if no data
1170 * is attached to the request.
1172 c.create_sq.opcode = nvme_admin_create_sq;
1173 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1174 c.create_sq.sqid = cpu_to_le16(qid);
1175 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1176 c.create_sq.sq_flags = cpu_to_le16(flags);
1177 c.create_sq.cqid = cpu_to_le16(qid);
1179 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1182 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1184 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1187 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1189 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1192 static void abort_endio(struct request *req, blk_status_t error)
1194 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1195 struct nvme_queue *nvmeq = iod->nvmeq;
1197 dev_warn(nvmeq->dev->ctrl.device,
1198 "Abort status: 0x%x", nvme_req(req)->status);
1199 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1200 blk_mq_free_request(req);
1203 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1205 /* If true, indicates loss of adapter communication, possibly by a
1206 * NVMe Subsystem reset.
1208 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1210 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1211 switch (dev->ctrl.state) {
1212 case NVME_CTRL_RESETTING:
1213 case NVME_CTRL_CONNECTING:
1219 /* We shouldn't reset unless the controller is on fatal error state
1220 * _or_ if we lost the communication with it.
1222 if (!(csts & NVME_CSTS_CFS) && !nssro)
1228 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1230 /* Read a config register to help see what died. */
1234 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1236 if (result == PCIBIOS_SUCCESSFUL)
1237 dev_warn(dev->ctrl.device,
1238 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1241 dev_warn(dev->ctrl.device,
1242 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1246 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1248 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1249 struct nvme_queue *nvmeq = iod->nvmeq;
1250 struct nvme_dev *dev = nvmeq->dev;
1251 struct request *abort_req;
1252 struct nvme_command cmd = { };
1253 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1255 /* If PCI error recovery process is happening, we cannot reset or
1256 * the recovery mechanism will surely fail.
1259 if (pci_channel_offline(to_pci_dev(dev->dev)))
1260 return BLK_EH_RESET_TIMER;
1263 * Reset immediately if the controller is failed
1265 if (nvme_should_reset(dev, csts)) {
1266 nvme_warn_reset(dev, csts);
1267 nvme_dev_disable(dev, false);
1268 nvme_reset_ctrl(&dev->ctrl);
1273 * Did we miss an interrupt?
1275 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1276 nvme_poll(req->mq_hctx);
1278 nvme_poll_irqdisable(nvmeq);
1280 if (blk_mq_request_completed(req)) {
1281 dev_warn(dev->ctrl.device,
1282 "I/O %d QID %d timeout, completion polled\n",
1283 req->tag, nvmeq->qid);
1288 * Shutdown immediately if controller times out while starting. The
1289 * reset work will see the pci device disabled when it gets the forced
1290 * cancellation error. All outstanding requests are completed on
1291 * shutdown, so we return BLK_EH_DONE.
1293 switch (dev->ctrl.state) {
1294 case NVME_CTRL_CONNECTING:
1295 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1297 case NVME_CTRL_DELETING:
1298 dev_warn_ratelimited(dev->ctrl.device,
1299 "I/O %d QID %d timeout, disable controller\n",
1300 req->tag, nvmeq->qid);
1301 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1302 nvme_dev_disable(dev, true);
1304 case NVME_CTRL_RESETTING:
1305 return BLK_EH_RESET_TIMER;
1311 * Shutdown the controller immediately and schedule a reset if the
1312 * command was already aborted once before and still hasn't been
1313 * returned to the driver, or if this is the admin queue.
1315 if (!nvmeq->qid || iod->aborted) {
1316 dev_warn(dev->ctrl.device,
1317 "I/O %d QID %d timeout, reset controller\n",
1318 req->tag, nvmeq->qid);
1319 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1320 nvme_dev_disable(dev, false);
1321 nvme_reset_ctrl(&dev->ctrl);
1326 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1327 atomic_inc(&dev->ctrl.abort_limit);
1328 return BLK_EH_RESET_TIMER;
1332 cmd.abort.opcode = nvme_admin_abort_cmd;
1333 cmd.abort.cid = nvme_cid(req);
1334 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1336 dev_warn(nvmeq->dev->ctrl.device,
1337 "I/O %d QID %d timeout, aborting\n",
1338 req->tag, nvmeq->qid);
1340 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1342 if (IS_ERR(abort_req)) {
1343 atomic_inc(&dev->ctrl.abort_limit);
1344 return BLK_EH_RESET_TIMER;
1347 abort_req->end_io_data = NULL;
1348 blk_execute_rq_nowait(NULL, abort_req, 0, abort_endio);
1351 * The aborted req will be completed on receiving the abort req.
1352 * We enable the timer again. If hit twice, it'll cause a device reset,
1353 * as the device then is in a faulty state.
1355 return BLK_EH_RESET_TIMER;
1358 static void nvme_free_queue(struct nvme_queue *nvmeq)
1360 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1361 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1362 if (!nvmeq->sq_cmds)
1365 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1366 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1367 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1369 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1370 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1374 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1378 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1379 dev->ctrl.queue_count--;
1380 nvme_free_queue(&dev->queues[i]);
1385 * nvme_suspend_queue - put queue into suspended state
1386 * @nvmeq: queue to suspend
1388 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1390 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1393 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1396 nvmeq->dev->online_queues--;
1397 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1398 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1399 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1400 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1404 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1408 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1409 nvme_suspend_queue(&dev->queues[i]);
1412 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1414 struct nvme_queue *nvmeq = &dev->queues[0];
1417 nvme_shutdown_ctrl(&dev->ctrl);
1419 nvme_disable_ctrl(&dev->ctrl);
1421 nvme_poll_irqdisable(nvmeq);
1425 * Called only on a device that has been disabled and after all other threads
1426 * that can check this device's completion queues have synced, except
1427 * nvme_poll(). This is the last chance for the driver to see a natural
1428 * completion before nvme_cancel_request() terminates all incomplete requests.
1430 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1434 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1435 spin_lock(&dev->queues[i].cq_poll_lock);
1436 nvme_process_cq(&dev->queues[i]);
1437 spin_unlock(&dev->queues[i].cq_poll_lock);
1441 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1444 int q_depth = dev->q_depth;
1445 unsigned q_size_aligned = roundup(q_depth * entry_size,
1446 NVME_CTRL_PAGE_SIZE);
1448 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1449 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1451 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1452 q_depth = div_u64(mem_per_q, entry_size);
1455 * Ensure the reduced q_depth is above some threshold where it
1456 * would be better to map queues in system memory with the
1466 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1469 struct pci_dev *pdev = to_pci_dev(dev->dev);
1471 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1472 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1473 if (nvmeq->sq_cmds) {
1474 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1476 if (nvmeq->sq_dma_addr) {
1477 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1481 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1485 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1486 &nvmeq->sq_dma_addr, GFP_KERNEL);
1487 if (!nvmeq->sq_cmds)
1492 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1494 struct nvme_queue *nvmeq = &dev->queues[qid];
1496 if (dev->ctrl.queue_count > qid)
1499 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1500 nvmeq->q_depth = depth;
1501 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1502 &nvmeq->cq_dma_addr, GFP_KERNEL);
1506 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1510 spin_lock_init(&nvmeq->sq_lock);
1511 spin_lock_init(&nvmeq->cq_poll_lock);
1513 nvmeq->cq_phase = 1;
1514 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1516 dev->ctrl.queue_count++;
1521 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1522 nvmeq->cq_dma_addr);
1527 static int queue_request_irq(struct nvme_queue *nvmeq)
1529 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1530 int nr = nvmeq->dev->ctrl.instance;
1532 if (use_threaded_interrupts) {
1533 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1534 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1536 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1537 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1541 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1543 struct nvme_dev *dev = nvmeq->dev;
1546 nvmeq->last_sq_tail = 0;
1548 nvmeq->cq_phase = 1;
1549 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1550 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1551 nvme_dbbuf_init(dev, nvmeq, qid);
1552 dev->online_queues++;
1553 wmb(); /* ensure the first interrupt sees the initialization */
1557 * Try getting shutdown_lock while setting up IO queues.
1559 static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1562 * Give up if the lock is being held by nvme_dev_disable.
1564 if (!mutex_trylock(&dev->shutdown_lock))
1568 * Controller is in wrong state, fail early.
1570 if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1571 mutex_unlock(&dev->shutdown_lock);
1578 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1580 struct nvme_dev *dev = nvmeq->dev;
1584 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1587 * A queue's vector matches the queue identifier unless the controller
1588 * has only one vector available.
1591 vector = dev->num_vecs == 1 ? 0 : qid;
1593 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1595 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1599 result = adapter_alloc_sq(dev, qid, nvmeq);
1605 nvmeq->cq_vector = vector;
1607 result = nvme_setup_io_queues_trylock(dev);
1610 nvme_init_queue(nvmeq, qid);
1612 result = queue_request_irq(nvmeq);
1617 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1618 mutex_unlock(&dev->shutdown_lock);
1622 dev->online_queues--;
1623 mutex_unlock(&dev->shutdown_lock);
1624 adapter_delete_sq(dev, qid);
1626 adapter_delete_cq(dev, qid);
1630 static const struct blk_mq_ops nvme_mq_admin_ops = {
1631 .queue_rq = nvme_queue_rq,
1632 .complete = nvme_pci_complete_rq,
1633 .init_hctx = nvme_admin_init_hctx,
1634 .init_request = nvme_init_request,
1635 .timeout = nvme_timeout,
1638 static const struct blk_mq_ops nvme_mq_ops = {
1639 .queue_rq = nvme_queue_rq,
1640 .complete = nvme_pci_complete_rq,
1641 .commit_rqs = nvme_commit_rqs,
1642 .init_hctx = nvme_init_hctx,
1643 .init_request = nvme_init_request,
1644 .map_queues = nvme_pci_map_queues,
1645 .timeout = nvme_timeout,
1649 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1651 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1653 * If the controller was reset during removal, it's possible
1654 * user requests may be waiting on a stopped queue. Start the
1655 * queue to flush these to completion.
1657 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1658 blk_cleanup_queue(dev->ctrl.admin_q);
1659 blk_mq_free_tag_set(&dev->admin_tagset);
1663 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1665 if (!dev->ctrl.admin_q) {
1666 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1667 dev->admin_tagset.nr_hw_queues = 1;
1669 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1670 dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
1671 dev->admin_tagset.numa_node = dev->ctrl.numa_node;
1672 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1673 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1674 dev->admin_tagset.driver_data = dev;
1676 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1678 dev->ctrl.admin_tagset = &dev->admin_tagset;
1680 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1681 if (IS_ERR(dev->ctrl.admin_q)) {
1682 blk_mq_free_tag_set(&dev->admin_tagset);
1683 dev->ctrl.admin_q = NULL;
1686 if (!blk_get_queue(dev->ctrl.admin_q)) {
1687 nvme_dev_remove_admin(dev);
1688 dev->ctrl.admin_q = NULL;
1692 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1697 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1699 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1702 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1704 struct pci_dev *pdev = to_pci_dev(dev->dev);
1706 if (size <= dev->bar_mapped_size)
1708 if (size > pci_resource_len(pdev, 0))
1712 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1714 dev->bar_mapped_size = 0;
1717 dev->bar_mapped_size = size;
1718 dev->dbs = dev->bar + NVME_REG_DBS;
1723 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1727 struct nvme_queue *nvmeq;
1729 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1733 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1734 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1736 if (dev->subsystem &&
1737 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1738 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1740 result = nvme_disable_ctrl(&dev->ctrl);
1744 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1748 dev->ctrl.numa_node = dev_to_node(dev->dev);
1750 nvmeq = &dev->queues[0];
1751 aqa = nvmeq->q_depth - 1;
1754 writel(aqa, dev->bar + NVME_REG_AQA);
1755 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1756 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1758 result = nvme_enable_ctrl(&dev->ctrl);
1762 nvmeq->cq_vector = 0;
1763 nvme_init_queue(nvmeq, 0);
1764 result = queue_request_irq(nvmeq);
1766 dev->online_queues--;
1770 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1774 static int nvme_create_io_queues(struct nvme_dev *dev)
1776 unsigned i, max, rw_queues;
1779 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1780 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1786 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1787 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1788 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1789 dev->io_queues[HCTX_TYPE_READ];
1794 for (i = dev->online_queues; i <= max; i++) {
1795 bool polled = i > rw_queues;
1797 ret = nvme_create_queue(&dev->queues[i], i, polled);
1803 * Ignore failing Create SQ/CQ commands, we can continue with less
1804 * than the desired amount of queues, and even a controller without
1805 * I/O queues can still be used to issue admin commands. This might
1806 * be useful to upgrade a buggy firmware for example.
1808 return ret >= 0 ? 0 : ret;
1811 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1813 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1815 return 1ULL << (12 + 4 * szu);
1818 static u32 nvme_cmb_size(struct nvme_dev *dev)
1820 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1823 static void nvme_map_cmb(struct nvme_dev *dev)
1826 resource_size_t bar_size;
1827 struct pci_dev *pdev = to_pci_dev(dev->dev);
1833 if (NVME_CAP_CMBS(dev->ctrl.cap))
1834 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1836 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1839 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1841 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1842 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1843 bar = NVME_CMB_BIR(dev->cmbloc);
1844 bar_size = pci_resource_len(pdev, bar);
1846 if (offset > bar_size)
1850 * Tell the controller about the host side address mapping the CMB,
1851 * and enable CMB decoding for the NVMe 1.4+ scheme:
1853 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1854 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1855 (pci_bus_address(pdev, bar) + offset),
1856 dev->bar + NVME_REG_CMBMSC);
1860 * Controllers may support a CMB size larger than their BAR,
1861 * for example, due to being behind a bridge. Reduce the CMB to
1862 * the reported size of the BAR
1864 if (size > bar_size - offset)
1865 size = bar_size - offset;
1867 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1868 dev_warn(dev->ctrl.device,
1869 "failed to register the CMB\n");
1873 dev->cmb_size = size;
1874 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1876 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1877 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1878 pci_p2pmem_publish(pdev, true);
1881 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1883 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1884 u64 dma_addr = dev->host_mem_descs_dma;
1885 struct nvme_command c = { };
1888 c.features.opcode = nvme_admin_set_features;
1889 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1890 c.features.dword11 = cpu_to_le32(bits);
1891 c.features.dword12 = cpu_to_le32(host_mem_size);
1892 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1893 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1894 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1896 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1898 dev_warn(dev->ctrl.device,
1899 "failed to set host mem (err %d, flags %#x).\n",
1902 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1907 static void nvme_free_host_mem(struct nvme_dev *dev)
1911 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1912 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1913 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
1915 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1916 le64_to_cpu(desc->addr),
1917 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1920 kfree(dev->host_mem_desc_bufs);
1921 dev->host_mem_desc_bufs = NULL;
1922 dma_free_coherent(dev->dev,
1923 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1924 dev->host_mem_descs, dev->host_mem_descs_dma);
1925 dev->host_mem_descs = NULL;
1926 dev->nr_host_mem_descs = 0;
1929 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1932 struct nvme_host_mem_buf_desc *descs;
1933 u32 max_entries, len;
1934 dma_addr_t descs_dma;
1939 tmp = (preferred + chunk_size - 1);
1940 do_div(tmp, chunk_size);
1943 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1944 max_entries = dev->ctrl.hmmaxd;
1946 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1947 &descs_dma, GFP_KERNEL);
1951 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1953 goto out_free_descs;
1955 for (size = 0; size < preferred && i < max_entries; size += len) {
1956 dma_addr_t dma_addr;
1958 len = min_t(u64, chunk_size, preferred - size);
1959 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1960 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1964 descs[i].addr = cpu_to_le64(dma_addr);
1965 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
1972 dev->nr_host_mem_descs = i;
1973 dev->host_mem_size = size;
1974 dev->host_mem_descs = descs;
1975 dev->host_mem_descs_dma = descs_dma;
1976 dev->host_mem_desc_bufs = bufs;
1981 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
1983 dma_free_attrs(dev->dev, size, bufs[i],
1984 le64_to_cpu(descs[i].addr),
1985 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1990 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1993 dev->host_mem_descs = NULL;
1997 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1999 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2000 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2003 /* start big and work our way down */
2004 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2005 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2006 if (!min || dev->host_mem_size >= min)
2008 nvme_free_host_mem(dev);
2015 static int nvme_setup_host_mem(struct nvme_dev *dev)
2017 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2018 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2019 u64 min = (u64)dev->ctrl.hmmin * 4096;
2020 u32 enable_bits = NVME_HOST_MEM_ENABLE;
2023 preferred = min(preferred, max);
2025 dev_warn(dev->ctrl.device,
2026 "min host memory (%lld MiB) above limit (%d MiB).\n",
2027 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2028 nvme_free_host_mem(dev);
2033 * If we already have a buffer allocated check if we can reuse it.
2035 if (dev->host_mem_descs) {
2036 if (dev->host_mem_size >= min)
2037 enable_bits |= NVME_HOST_MEM_RETURN;
2039 nvme_free_host_mem(dev);
2042 if (!dev->host_mem_descs) {
2043 if (nvme_alloc_host_mem(dev, min, preferred)) {
2044 dev_warn(dev->ctrl.device,
2045 "failed to allocate host memory buffer.\n");
2046 return 0; /* controller must work without HMB */
2049 dev_info(dev->ctrl.device,
2050 "allocated %lld MiB host memory buffer.\n",
2051 dev->host_mem_size >> ilog2(SZ_1M));
2054 ret = nvme_set_host_mem(dev, enable_bits);
2056 nvme_free_host_mem(dev);
2060 static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2063 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2065 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2066 ndev->cmbloc, ndev->cmbsz);
2068 static DEVICE_ATTR_RO(cmb);
2070 static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2073 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2075 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2077 static DEVICE_ATTR_RO(cmbloc);
2079 static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2082 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2084 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2086 static DEVICE_ATTR_RO(cmbsz);
2088 static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2091 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2093 return sysfs_emit(buf, "%d\n", ndev->hmb);
2096 static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2097 const char *buf, size_t count)
2099 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2103 if (strtobool(buf, &new) < 0)
2106 if (new == ndev->hmb)
2110 ret = nvme_setup_host_mem(ndev);
2112 ret = nvme_set_host_mem(ndev, 0);
2114 nvme_free_host_mem(ndev);
2122 static DEVICE_ATTR_RW(hmb);
2124 static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2125 struct attribute *a, int n)
2127 struct nvme_ctrl *ctrl =
2128 dev_get_drvdata(container_of(kobj, struct device, kobj));
2129 struct nvme_dev *dev = to_nvme_dev(ctrl);
2131 if (a == &dev_attr_cmb.attr ||
2132 a == &dev_attr_cmbloc.attr ||
2133 a == &dev_attr_cmbsz.attr) {
2137 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2143 static struct attribute *nvme_pci_attrs[] = {
2145 &dev_attr_cmbloc.attr,
2146 &dev_attr_cmbsz.attr,
2151 static const struct attribute_group nvme_pci_attr_group = {
2152 .attrs = nvme_pci_attrs,
2153 .is_visible = nvme_pci_attrs_are_visible,
2157 * nirqs is the number of interrupts available for write and read
2158 * queues. The core already reserved an interrupt for the admin queue.
2160 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2162 struct nvme_dev *dev = affd->priv;
2163 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2166 * If there is no interrupt available for queues, ensure that
2167 * the default queue is set to 1. The affinity set size is
2168 * also set to one, but the irq core ignores it for this case.
2170 * If only one interrupt is available or 'write_queue' == 0, combine
2171 * write and read queues.
2173 * If 'write_queues' > 0, ensure it leaves room for at least one read
2179 } else if (nrirqs == 1 || !nr_write_queues) {
2181 } else if (nr_write_queues >= nrirqs) {
2184 nr_read_queues = nrirqs - nr_write_queues;
2187 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2188 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2189 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2190 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2191 affd->nr_sets = nr_read_queues ? 2 : 1;
2194 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2196 struct pci_dev *pdev = to_pci_dev(dev->dev);
2197 struct irq_affinity affd = {
2199 .calc_sets = nvme_calc_irq_sets,
2202 unsigned int irq_queues, poll_queues;
2205 * Poll queues don't need interrupts, but we need at least one I/O queue
2206 * left over for non-polled I/O.
2208 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2209 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2212 * Initialize for the single interrupt case, will be updated in
2213 * nvme_calc_irq_sets().
2215 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2216 dev->io_queues[HCTX_TYPE_READ] = 0;
2219 * We need interrupts for the admin queue and each non-polled I/O queue,
2220 * but some Apple controllers require all queues to use the first
2224 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2225 irq_queues += (nr_io_queues - poll_queues);
2226 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2227 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2230 static void nvme_disable_io_queues(struct nvme_dev *dev)
2232 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2233 __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2236 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2239 * If tags are shared with admin queue (Apple bug), then
2240 * make sure we only use one IO queue.
2242 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2244 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2247 static int nvme_setup_io_queues(struct nvme_dev *dev)
2249 struct nvme_queue *adminq = &dev->queues[0];
2250 struct pci_dev *pdev = to_pci_dev(dev->dev);
2251 unsigned int nr_io_queues;
2256 * Sample the module parameters once at reset time so that we have
2257 * stable values to work with.
2259 dev->nr_write_queues = write_queues;
2260 dev->nr_poll_queues = poll_queues;
2262 nr_io_queues = dev->nr_allocated_queues - 1;
2263 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2267 if (nr_io_queues == 0)
2271 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2272 * from set to unset. If there is a window to it is truely freed,
2273 * pci_free_irq_vectors() jumping into this window will crash.
2274 * And take lock to avoid racing with pci_free_irq_vectors() in
2275 * nvme_dev_disable() path.
2277 result = nvme_setup_io_queues_trylock(dev);
2280 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2281 pci_free_irq(pdev, 0, adminq);
2283 if (dev->cmb_use_sqes) {
2284 result = nvme_cmb_qdepth(dev, nr_io_queues,
2285 sizeof(struct nvme_command));
2287 dev->q_depth = result;
2289 dev->cmb_use_sqes = false;
2293 size = db_bar_size(dev, nr_io_queues);
2294 result = nvme_remap_bar(dev, size);
2297 if (!--nr_io_queues) {
2302 adminq->q_db = dev->dbs;
2305 /* Deregister the admin queue's interrupt */
2306 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2307 pci_free_irq(pdev, 0, adminq);
2310 * If we enable msix early due to not intx, disable it again before
2311 * setting up the full range we need.
2313 pci_free_irq_vectors(pdev);
2315 result = nvme_setup_irqs(dev, nr_io_queues);
2321 dev->num_vecs = result;
2322 result = max(result - 1, 1);
2323 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2326 * Should investigate if there's a performance win from allocating
2327 * more queues than interrupt vectors; it might allow the submission
2328 * path to scale better, even if the receive path is limited by the
2329 * number of interrupts.
2331 result = queue_request_irq(adminq);
2334 set_bit(NVMEQ_ENABLED, &adminq->flags);
2335 mutex_unlock(&dev->shutdown_lock);
2337 result = nvme_create_io_queues(dev);
2338 if (result || dev->online_queues < 2)
2341 if (dev->online_queues - 1 < dev->max_qid) {
2342 nr_io_queues = dev->online_queues - 1;
2343 nvme_disable_io_queues(dev);
2344 result = nvme_setup_io_queues_trylock(dev);
2347 nvme_suspend_io_queues(dev);
2350 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2351 dev->io_queues[HCTX_TYPE_DEFAULT],
2352 dev->io_queues[HCTX_TYPE_READ],
2353 dev->io_queues[HCTX_TYPE_POLL]);
2356 mutex_unlock(&dev->shutdown_lock);
2360 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2362 struct nvme_queue *nvmeq = req->end_io_data;
2364 blk_mq_free_request(req);
2365 complete(&nvmeq->delete_done);
2368 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2370 struct nvme_queue *nvmeq = req->end_io_data;
2373 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2375 nvme_del_queue_end(req, error);
2378 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2380 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2381 struct request *req;
2382 struct nvme_command cmd = { };
2384 cmd.delete_queue.opcode = opcode;
2385 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2387 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
2389 return PTR_ERR(req);
2391 req->end_io_data = nvmeq;
2393 init_completion(&nvmeq->delete_done);
2394 blk_execute_rq_nowait(NULL, req, false,
2395 opcode == nvme_admin_delete_cq ?
2396 nvme_del_cq_end : nvme_del_queue_end);
2400 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2402 int nr_queues = dev->online_queues - 1, sent = 0;
2403 unsigned long timeout;
2406 timeout = NVME_ADMIN_TIMEOUT;
2407 while (nr_queues > 0) {
2408 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2414 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2416 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2428 static void nvme_dev_add(struct nvme_dev *dev)
2432 if (!dev->ctrl.tagset) {
2433 dev->tagset.ops = &nvme_mq_ops;
2434 dev->tagset.nr_hw_queues = dev->online_queues - 1;
2435 dev->tagset.nr_maps = 2; /* default + read */
2436 if (dev->io_queues[HCTX_TYPE_POLL])
2437 dev->tagset.nr_maps++;
2438 dev->tagset.timeout = NVME_IO_TIMEOUT;
2439 dev->tagset.numa_node = dev->ctrl.numa_node;
2440 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2441 BLK_MQ_MAX_DEPTH) - 1;
2442 dev->tagset.cmd_size = sizeof(struct nvme_iod);
2443 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2444 dev->tagset.driver_data = dev;
2447 * Some Apple controllers requires tags to be unique
2448 * across admin and IO queue, so reserve the first 32
2449 * tags of the IO queue.
2451 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2452 dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2454 ret = blk_mq_alloc_tag_set(&dev->tagset);
2456 dev_warn(dev->ctrl.device,
2457 "IO queues tagset allocation failed %d\n", ret);
2460 dev->ctrl.tagset = &dev->tagset;
2462 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2464 /* Free previously allocated queues that are no longer usable */
2465 nvme_free_queues(dev, dev->online_queues);
2468 nvme_dbbuf_set(dev);
2471 static int nvme_pci_enable(struct nvme_dev *dev)
2473 int result = -ENOMEM;
2474 struct pci_dev *pdev = to_pci_dev(dev->dev);
2475 int dma_address_bits = 64;
2477 if (pci_enable_device_mem(pdev))
2480 pci_set_master(pdev);
2482 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2483 dma_address_bits = 48;
2484 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
2487 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2493 * Some devices and/or platforms don't advertise or work with INTx
2494 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2495 * adjust this later.
2497 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2501 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2503 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2505 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2506 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2507 dev->dbs = dev->bar + 4096;
2510 * Some Apple controllers require a non-standard SQE size.
2511 * Interestingly they also seem to ignore the CC:IOSQES register
2512 * so we don't bother updating it here.
2514 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2517 dev->io_sqes = NVME_NVM_IOSQES;
2520 * Temporary fix for the Apple controller found in the MacBook8,1 and
2521 * some MacBook7,1 to avoid controller resets and data loss.
2523 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2525 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2526 "set queue depth=%u to work around controller resets\n",
2528 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2529 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2530 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2532 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2533 "set queue depth=%u\n", dev->q_depth);
2537 * Controllers with the shared tags quirk need the IO queue to be
2538 * big enough so that we get 32 tags for the admin queue
2540 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2541 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2542 dev->q_depth = NVME_AQ_DEPTH + 2;
2543 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2550 pci_enable_pcie_error_reporting(pdev);
2551 pci_save_state(pdev);
2555 pci_disable_device(pdev);
2559 static void nvme_dev_unmap(struct nvme_dev *dev)
2563 pci_release_mem_regions(to_pci_dev(dev->dev));
2566 static void nvme_pci_disable(struct nvme_dev *dev)
2568 struct pci_dev *pdev = to_pci_dev(dev->dev);
2570 pci_free_irq_vectors(pdev);
2572 if (pci_is_enabled(pdev)) {
2573 pci_disable_pcie_error_reporting(pdev);
2574 pci_disable_device(pdev);
2578 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2580 bool dead = true, freeze = false;
2581 struct pci_dev *pdev = to_pci_dev(dev->dev);
2583 mutex_lock(&dev->shutdown_lock);
2584 if (pci_is_enabled(pdev)) {
2585 u32 csts = readl(dev->bar + NVME_REG_CSTS);
2587 if (dev->ctrl.state == NVME_CTRL_LIVE ||
2588 dev->ctrl.state == NVME_CTRL_RESETTING) {
2590 nvme_start_freeze(&dev->ctrl);
2592 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2593 pdev->error_state != pci_channel_io_normal);
2597 * Give the controller a chance to complete all entered requests if
2598 * doing a safe shutdown.
2600 if (!dead && shutdown && freeze)
2601 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2603 nvme_stop_queues(&dev->ctrl);
2605 if (!dead && dev->ctrl.queue_count > 0) {
2606 nvme_disable_io_queues(dev);
2607 nvme_disable_admin_queue(dev, shutdown);
2609 nvme_suspend_io_queues(dev);
2610 nvme_suspend_queue(&dev->queues[0]);
2611 nvme_pci_disable(dev);
2612 nvme_reap_pending_cqes(dev);
2614 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2615 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2616 blk_mq_tagset_wait_completed_request(&dev->tagset);
2617 blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
2620 * The driver will not be starting up queues again if shutting down so
2621 * must flush all entered requests to their failed completion to avoid
2622 * deadlocking blk-mq hot-cpu notifier.
2625 nvme_start_queues(&dev->ctrl);
2626 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2627 blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2629 mutex_unlock(&dev->shutdown_lock);
2632 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2634 if (!nvme_wait_reset(&dev->ctrl))
2636 nvme_dev_disable(dev, shutdown);
2640 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2642 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2643 NVME_CTRL_PAGE_SIZE,
2644 NVME_CTRL_PAGE_SIZE, 0);
2645 if (!dev->prp_page_pool)
2648 /* Optimisation for I/Os between 4k and 128k */
2649 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2651 if (!dev->prp_small_pool) {
2652 dma_pool_destroy(dev->prp_page_pool);
2658 static void nvme_release_prp_pools(struct nvme_dev *dev)
2660 dma_pool_destroy(dev->prp_page_pool);
2661 dma_pool_destroy(dev->prp_small_pool);
2664 static void nvme_free_tagset(struct nvme_dev *dev)
2666 if (dev->tagset.tags)
2667 blk_mq_free_tag_set(&dev->tagset);
2668 dev->ctrl.tagset = NULL;
2671 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2673 struct nvme_dev *dev = to_nvme_dev(ctrl);
2675 nvme_dbbuf_dma_free(dev);
2676 nvme_free_tagset(dev);
2677 if (dev->ctrl.admin_q)
2678 blk_put_queue(dev->ctrl.admin_q);
2679 free_opal_dev(dev->ctrl.opal_dev);
2680 mempool_destroy(dev->iod_mempool);
2681 put_device(dev->dev);
2686 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2689 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2690 * may be holding this pci_dev's device lock.
2692 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2693 nvme_get_ctrl(&dev->ctrl);
2694 nvme_dev_disable(dev, false);
2695 nvme_kill_queues(&dev->ctrl);
2696 if (!queue_work(nvme_wq, &dev->remove_work))
2697 nvme_put_ctrl(&dev->ctrl);
2700 static void nvme_reset_work(struct work_struct *work)
2702 struct nvme_dev *dev =
2703 container_of(work, struct nvme_dev, ctrl.reset_work);
2704 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2707 if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2708 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2715 * If we're called to reset a live controller first shut it down before
2718 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2719 nvme_dev_disable(dev, false);
2720 nvme_sync_queues(&dev->ctrl);
2722 mutex_lock(&dev->shutdown_lock);
2723 result = nvme_pci_enable(dev);
2727 result = nvme_pci_configure_admin_queue(dev);
2731 result = nvme_alloc_admin_tags(dev);
2736 * Limit the max command size to prevent iod->sg allocations going
2737 * over a single page.
2739 dev->ctrl.max_hw_sectors = min_t(u32,
2740 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2741 dev->ctrl.max_segments = NVME_MAX_SEGS;
2744 * Don't limit the IOMMU merged segment size.
2746 dma_set_max_seg_size(dev->dev, 0xffffffff);
2747 dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
2749 mutex_unlock(&dev->shutdown_lock);
2752 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2753 * initializing procedure here.
2755 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2756 dev_warn(dev->ctrl.device,
2757 "failed to mark controller CONNECTING\n");
2763 * We do not support an SGL for metadata (yet), so we are limited to a
2764 * single integrity segment for the separate metadata pointer.
2766 dev->ctrl.max_integrity_segments = 1;
2768 result = nvme_init_ctrl_finish(&dev->ctrl);
2772 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2773 if (!dev->ctrl.opal_dev)
2774 dev->ctrl.opal_dev =
2775 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2776 else if (was_suspend)
2777 opal_unlock_from_suspend(dev->ctrl.opal_dev);
2779 free_opal_dev(dev->ctrl.opal_dev);
2780 dev->ctrl.opal_dev = NULL;
2783 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2784 result = nvme_dbbuf_dma_alloc(dev);
2787 "unable to allocate dma for dbbuf\n");
2790 if (dev->ctrl.hmpre) {
2791 result = nvme_setup_host_mem(dev);
2796 result = nvme_setup_io_queues(dev);
2801 * Keep the controller around but remove all namespaces if we don't have
2802 * any working I/O queue.
2804 if (dev->online_queues < 2) {
2805 dev_warn(dev->ctrl.device, "IO queues not created\n");
2806 nvme_kill_queues(&dev->ctrl);
2807 nvme_remove_namespaces(&dev->ctrl);
2808 nvme_free_tagset(dev);
2810 nvme_start_queues(&dev->ctrl);
2811 nvme_wait_freeze(&dev->ctrl);
2813 nvme_unfreeze(&dev->ctrl);
2817 * If only admin queue live, keep it to do further investigation or
2820 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2821 dev_warn(dev->ctrl.device,
2822 "failed to mark controller live state\n");
2827 if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj,
2828 &nvme_pci_attr_group))
2829 dev->attrs_added = true;
2831 nvme_start_ctrl(&dev->ctrl);
2835 mutex_unlock(&dev->shutdown_lock);
2838 dev_warn(dev->ctrl.device,
2839 "Removing after probe failure status: %d\n", result);
2840 nvme_remove_dead_ctrl(dev);
2843 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2845 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2846 struct pci_dev *pdev = to_pci_dev(dev->dev);
2848 if (pci_get_drvdata(pdev))
2849 device_release_driver(&pdev->dev);
2850 nvme_put_ctrl(&dev->ctrl);
2853 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2855 *val = readl(to_nvme_dev(ctrl)->bar + off);
2859 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2861 writel(val, to_nvme_dev(ctrl)->bar + off);
2865 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2867 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2871 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2873 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2875 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2878 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2880 .module = THIS_MODULE,
2881 .flags = NVME_F_METADATA_SUPPORTED |
2883 .reg_read32 = nvme_pci_reg_read32,
2884 .reg_write32 = nvme_pci_reg_write32,
2885 .reg_read64 = nvme_pci_reg_read64,
2886 .free_ctrl = nvme_pci_free_ctrl,
2887 .submit_async_event = nvme_pci_submit_async_event,
2888 .get_address = nvme_pci_get_address,
2891 static int nvme_dev_map(struct nvme_dev *dev)
2893 struct pci_dev *pdev = to_pci_dev(dev->dev);
2895 if (pci_request_mem_regions(pdev, "nvme"))
2898 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2903 pci_release_mem_regions(pdev);
2907 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2909 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2911 * Several Samsung devices seem to drop off the PCIe bus
2912 * randomly when APST is on and uses the deepest sleep state.
2913 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2914 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2915 * 950 PRO 256GB", but it seems to be restricted to two Dell
2918 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2919 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2920 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2921 return NVME_QUIRK_NO_DEEPEST_PS;
2922 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2924 * Samsung SSD 960 EVO drops off the PCIe bus after system
2925 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2926 * within few minutes after bootup on a Coffee Lake board -
2929 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2930 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2931 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2932 return NVME_QUIRK_NO_APST;
2933 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2934 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2935 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2937 * Forcing to use host managed nvme power settings for
2938 * lowest idle power with quick resume latency on
2939 * Samsung and Toshiba SSDs based on suspend behavior
2940 * on Coffee Lake board for LENOVO C640
2942 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2943 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2944 return NVME_QUIRK_SIMPLE_SUSPEND;
2950 static void nvme_async_probe(void *data, async_cookie_t cookie)
2952 struct nvme_dev *dev = data;
2954 flush_work(&dev->ctrl.reset_work);
2955 flush_work(&dev->ctrl.scan_work);
2956 nvme_put_ctrl(&dev->ctrl);
2959 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2961 int node, result = -ENOMEM;
2962 struct nvme_dev *dev;
2963 unsigned long quirks = id->driver_data;
2966 node = dev_to_node(&pdev->dev);
2967 if (node == NUMA_NO_NODE)
2968 set_dev_node(&pdev->dev, first_memory_node);
2970 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2974 dev->nr_write_queues = write_queues;
2975 dev->nr_poll_queues = poll_queues;
2976 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2977 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2978 sizeof(struct nvme_queue), GFP_KERNEL, node);
2982 dev->dev = get_device(&pdev->dev);
2983 pci_set_drvdata(pdev, dev);
2985 result = nvme_dev_map(dev);
2989 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2990 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2991 mutex_init(&dev->shutdown_lock);
2993 result = nvme_setup_prp_pools(dev);
2997 quirks |= check_vendor_combination_bug(pdev);
2999 if (!noacpi && acpi_storage_d3(&pdev->dev)) {
3001 * Some systems use a bios work around to ask for D3 on
3002 * platforms that support kernel managed suspend.
3004 dev_info(&pdev->dev,
3005 "platform quirk: setting simple suspend\n");
3006 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
3010 * Double check that our mempool alloc size will cover the biggest
3011 * command we support.
3013 alloc_size = nvme_pci_iod_alloc_size();
3014 WARN_ON_ONCE(alloc_size > PAGE_SIZE);
3016 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
3018 (void *) alloc_size,
3020 if (!dev->iod_mempool) {
3025 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
3028 goto release_mempool;
3030 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3032 nvme_reset_ctrl(&dev->ctrl);
3033 async_schedule(nvme_async_probe, dev);
3038 mempool_destroy(dev->iod_mempool);
3040 nvme_release_prp_pools(dev);
3042 nvme_dev_unmap(dev);
3044 put_device(dev->dev);
3051 static void nvme_reset_prepare(struct pci_dev *pdev)
3053 struct nvme_dev *dev = pci_get_drvdata(pdev);
3056 * We don't need to check the return value from waiting for the reset
3057 * state as pci_dev device lock is held, making it impossible to race
3060 nvme_disable_prepare_reset(dev, false);
3061 nvme_sync_queues(&dev->ctrl);
3064 static void nvme_reset_done(struct pci_dev *pdev)
3066 struct nvme_dev *dev = pci_get_drvdata(pdev);
3068 if (!nvme_try_sched_reset(&dev->ctrl))
3069 flush_work(&dev->ctrl.reset_work);
3072 static void nvme_shutdown(struct pci_dev *pdev)
3074 struct nvme_dev *dev = pci_get_drvdata(pdev);
3076 nvme_disable_prepare_reset(dev, true);
3079 static void nvme_remove_attrs(struct nvme_dev *dev)
3081 if (dev->attrs_added)
3082 sysfs_remove_group(&dev->ctrl.device->kobj,
3083 &nvme_pci_attr_group);
3087 * The driver's remove may be called on a device in a partially initialized
3088 * state. This function must not have any dependencies on the device state in
3091 static void nvme_remove(struct pci_dev *pdev)
3093 struct nvme_dev *dev = pci_get_drvdata(pdev);
3095 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3096 pci_set_drvdata(pdev, NULL);
3098 if (!pci_device_is_present(pdev)) {
3099 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3100 nvme_dev_disable(dev, true);
3103 flush_work(&dev->ctrl.reset_work);
3104 nvme_stop_ctrl(&dev->ctrl);
3105 nvme_remove_namespaces(&dev->ctrl);
3106 nvme_dev_disable(dev, true);
3107 nvme_remove_attrs(dev);
3108 nvme_free_host_mem(dev);
3109 nvme_dev_remove_admin(dev);
3110 nvme_free_queues(dev, 0);
3111 nvme_release_prp_pools(dev);
3112 nvme_dev_unmap(dev);
3113 nvme_uninit_ctrl(&dev->ctrl);
3116 #ifdef CONFIG_PM_SLEEP
3117 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3119 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3122 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3124 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3127 static int nvme_resume(struct device *dev)
3129 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3130 struct nvme_ctrl *ctrl = &ndev->ctrl;
3132 if (ndev->last_ps == U32_MAX ||
3133 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3135 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3140 return nvme_try_sched_reset(ctrl);
3143 static int nvme_suspend(struct device *dev)
3145 struct pci_dev *pdev = to_pci_dev(dev);
3146 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3147 struct nvme_ctrl *ctrl = &ndev->ctrl;
3150 ndev->last_ps = U32_MAX;
3153 * The platform does not remove power for a kernel managed suspend so
3154 * use host managed nvme power settings for lowest idle power if
3155 * possible. This should have quicker resume latency than a full device
3156 * shutdown. But if the firmware is involved after the suspend or the
3157 * device does not support any non-default power states, shut down the
3160 * If ASPM is not enabled for the device, shut down the device and allow
3161 * the PCI bus layer to put it into D3 in order to take the PCIe link
3162 * down, so as to allow the platform to achieve its minimum low-power
3163 * state (which may not be possible if the link is up).
3165 if (pm_suspend_via_firmware() || !ctrl->npss ||
3166 !pcie_aspm_enabled(pdev) ||
3167 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3168 return nvme_disable_prepare_reset(ndev, true);
3170 nvme_start_freeze(ctrl);
3171 nvme_wait_freeze(ctrl);
3172 nvme_sync_queues(ctrl);
3174 if (ctrl->state != NVME_CTRL_LIVE)
3178 * Host memory access may not be successful in a system suspend state,
3179 * but the specification allows the controller to access memory in a
3180 * non-operational power state.
3183 ret = nvme_set_host_mem(ndev, 0);
3188 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3193 * A saved state prevents pci pm from generically controlling the
3194 * device's power. If we're using protocol specific settings, we don't
3195 * want pci interfering.
3197 pci_save_state(pdev);
3199 ret = nvme_set_power_state(ctrl, ctrl->npss);
3204 /* discard the saved state */
3205 pci_load_saved_state(pdev, NULL);
3208 * Clearing npss forces a controller reset on resume. The
3209 * correct value will be rediscovered then.
3211 ret = nvme_disable_prepare_reset(ndev, true);
3215 nvme_unfreeze(ctrl);
3219 static int nvme_simple_suspend(struct device *dev)
3221 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3223 return nvme_disable_prepare_reset(ndev, true);
3226 static int nvme_simple_resume(struct device *dev)
3228 struct pci_dev *pdev = to_pci_dev(dev);
3229 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3231 return nvme_try_sched_reset(&ndev->ctrl);
3234 static const struct dev_pm_ops nvme_dev_pm_ops = {
3235 .suspend = nvme_suspend,
3236 .resume = nvme_resume,
3237 .freeze = nvme_simple_suspend,
3238 .thaw = nvme_simple_resume,
3239 .poweroff = nvme_simple_suspend,
3240 .restore = nvme_simple_resume,
3242 #endif /* CONFIG_PM_SLEEP */
3244 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3245 pci_channel_state_t state)
3247 struct nvme_dev *dev = pci_get_drvdata(pdev);
3250 * A frozen channel requires a reset. When detected, this method will
3251 * shutdown the controller to quiesce. The controller will be restarted
3252 * after the slot reset through driver's slot_reset callback.
3255 case pci_channel_io_normal:
3256 return PCI_ERS_RESULT_CAN_RECOVER;
3257 case pci_channel_io_frozen:
3258 dev_warn(dev->ctrl.device,
3259 "frozen state error detected, reset controller\n");
3260 nvme_dev_disable(dev, false);
3261 return PCI_ERS_RESULT_NEED_RESET;
3262 case pci_channel_io_perm_failure:
3263 dev_warn(dev->ctrl.device,
3264 "failure state error detected, request disconnect\n");
3265 return PCI_ERS_RESULT_DISCONNECT;
3267 return PCI_ERS_RESULT_NEED_RESET;
3270 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3272 struct nvme_dev *dev = pci_get_drvdata(pdev);
3274 dev_info(dev->ctrl.device, "restart after slot reset\n");
3275 pci_restore_state(pdev);
3276 nvme_reset_ctrl(&dev->ctrl);
3277 return PCI_ERS_RESULT_RECOVERED;
3280 static void nvme_error_resume(struct pci_dev *pdev)
3282 struct nvme_dev *dev = pci_get_drvdata(pdev);
3284 flush_work(&dev->ctrl.reset_work);
3287 static const struct pci_error_handlers nvme_err_handler = {
3288 .error_detected = nvme_error_detected,
3289 .slot_reset = nvme_slot_reset,
3290 .resume = nvme_error_resume,
3291 .reset_prepare = nvme_reset_prepare,
3292 .reset_done = nvme_reset_done,
3295 static const struct pci_device_id nvme_id_table[] = {
3296 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
3297 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3298 NVME_QUIRK_DEALLOCATE_ZEROES, },
3299 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
3300 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3301 NVME_QUIRK_DEALLOCATE_ZEROES, },
3302 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
3303 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3304 NVME_QUIRK_DEALLOCATE_ZEROES |
3305 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3306 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
3307 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3308 NVME_QUIRK_DEALLOCATE_ZEROES, },
3309 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
3310 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3311 NVME_QUIRK_MEDIUM_PRIO_SQ |
3312 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3313 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3314 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3315 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3316 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
3317 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3318 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3319 NVME_QUIRK_BOGUS_NID, },
3320 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */
3321 .driver_data = NVME_QUIRK_BOGUS_NID, },
3322 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3323 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
3324 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3325 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3326 NVME_QUIRK_NO_NS_DESC_LIST, },
3327 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3328 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3329 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3330 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3331 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3332 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3333 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3334 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3335 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3336 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3337 NVME_QUIRK_DISABLE_WRITE_ZEROES|
3338 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3339 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
3340 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3341 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3342 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3343 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3344 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3345 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3346 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3347 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3348 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3349 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3350 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3351 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3352 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3353 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3354 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3355 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3356 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3357 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3358 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3359 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */
3360 .driver_data = NVME_QUIRK_BOGUS_NID, },
3361 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */
3362 .driver_data = NVME_QUIRK_BOGUS_NID, },
3363 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3364 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3365 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3366 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3367 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3368 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3369 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3370 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3371 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3372 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3373 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3374 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3375 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3376 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3377 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3378 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3379 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3380 NVME_QUIRK_128_BYTES_SQES |
3381 NVME_QUIRK_SHARED_TAGS |
3382 NVME_QUIRK_SKIP_CID_GEN },
3383 { PCI_DEVICE(0x144d, 0xa808), /* Samsung X5 */
3384 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY|
3385 NVME_QUIRK_NO_DEEPEST_PS |
3386 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3387 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3390 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3392 static struct pci_driver nvme_driver = {
3394 .id_table = nvme_id_table,
3395 .probe = nvme_probe,
3396 .remove = nvme_remove,
3397 .shutdown = nvme_shutdown,
3398 #ifdef CONFIG_PM_SLEEP
3400 .pm = &nvme_dev_pm_ops,
3403 .sriov_configure = pci_sriov_configure_simple,
3404 .err_handler = &nvme_err_handler,
3407 static int __init nvme_init(void)
3409 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3410 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3411 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3412 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3414 return pci_register_driver(&nvme_driver);
3417 static void __exit nvme_exit(void)
3419 pci_unregister_driver(&nvme_driver);
3420 flush_workqueue(nvme_wq);
3423 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3424 MODULE_LICENSE("GPL");
3425 MODULE_VERSION("1.0");
3426 module_init(nvme_init);
3427 module_exit(nvme_exit);