2 * (C) Copyright 2011 Michal Simek
4 * Michal SIMEK <monstr@monstr.eu>
6 * Based on Xilinx gmac driver:
7 * (C) Copyright 2011 Xilinx
9 * SPDX-License-Identifier: GPL-2.0+
24 #include <asm/system.h>
25 #include <asm/arch/hardware.h>
26 #include <asm/arch/sys_proto.h>
27 #include <asm-generic/errno.h>
29 DECLARE_GLOBAL_DATA_PTR;
31 /* Bit/mask specification */
32 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
33 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
34 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
35 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
36 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
38 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
39 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
40 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
42 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
43 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
44 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
46 /* Wrap bit, last descriptor */
47 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
48 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
49 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
51 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
52 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
53 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
54 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
56 #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */
57 #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
58 #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
59 #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
60 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */
63 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
65 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
68 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
69 ZYNQ_GEM_NWCFG_FDEN | \
70 ZYNQ_GEM_NWCFG_FSREM | \
71 ZYNQ_GEM_NWCFG_MDCCLKDIV)
73 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
75 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
76 /* Use full configured addressable space (8 Kb) */
77 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
78 /* Use full configured addressable space (4 Kb) */
79 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
80 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
81 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000
83 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
84 ZYNQ_GEM_DMACR_RXSIZE | \
85 ZYNQ_GEM_DMACR_TXSIZE | \
88 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
90 /* Use MII register 1 (MII status register) to detect PHY */
91 #define PHY_DETECT_REG 1
93 /* Mask used to verify certain PHY features (or register contents)
94 * in the register above:
95 * 0x1000: 10Mbps full duplex support
96 * 0x0800: 10Mbps half duplex support
97 * 0x0008: Auto-negotiation support
99 #define PHY_DETECT_MASK 0x1808
101 /* TX BD status masks */
102 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
103 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
104 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
106 /* Clock frequencies for different speeds */
107 #define ZYNQ_GEM_FREQUENCY_10 2500000UL
108 #define ZYNQ_GEM_FREQUENCY_100 25000000UL
109 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
111 /* Device registers */
112 struct zynq_gem_regs {
113 u32 nwctrl; /* 0x0 - Network Control reg */
114 u32 nwcfg; /* 0x4 - Network Config reg */
115 u32 nwsr; /* 0x8 - Network Status reg */
117 u32 dmacr; /* 0x10 - DMA Control reg */
118 u32 txsr; /* 0x14 - TX Status reg */
119 u32 rxqbase; /* 0x18 - RX Q Base address reg */
120 u32 txqbase; /* 0x1c - TX Q Base address reg */
121 u32 rxsr; /* 0x20 - RX Status reg */
123 u32 idr; /* 0x2c - Interrupt Disable reg */
125 u32 phymntnc; /* 0x34 - Phy Maintaince reg */
127 u32 hashl; /* 0x80 - Hash Low address reg */
128 u32 hashh; /* 0x84 - Hash High address reg */
131 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
132 u32 match[4]; /* 0xa8 - Type ID1 Match reg */
135 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
137 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
139 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
144 u32 addr; /* Next descriptor pointer */
149 /* Page table entries are set to 1MB, or multiples of 1MB
150 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
152 #define BD_SPACE 0x100000
153 /* BD separation space */
154 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd))
156 /* Setup the first free TX descriptor */
157 #define TX_FREE_DESC 2
159 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
160 struct zynq_gem_priv {
161 struct emac_bd *tx_bd;
162 struct emac_bd *rx_bd;
169 struct zynq_gem_regs *iobase;
170 phy_interface_t interface;
171 struct phy_device *phydev;
175 static inline int mdio_wait(struct zynq_gem_regs *regs)
179 /* Wait till MDIO interface is ready to accept a new transaction. */
181 if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
187 printf("%s: Timeout\n", __func__);
194 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
198 struct zynq_gem_regs *regs = priv->iobase;
203 /* Construct mgtcr mask for the operation */
204 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
205 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
206 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
208 /* Write mgtcr and wait for completion */
209 writel(mgtcr, ®s->phymntnc);
214 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
215 *data = readl(®s->phymntnc);
220 static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr,
221 u32 regnum, u16 *val)
225 ret = phy_setup_op(priv, phy_addr, regnum,
226 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
229 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
230 phy_addr, regnum, *val);
235 static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
236 u32 regnum, u16 data)
238 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
241 return phy_setup_op(priv, phy_addr, regnum,
242 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
245 static int phy_detection(struct udevice *dev)
249 struct zynq_gem_priv *priv = dev->priv;
251 if (priv->phyaddr != -1) {
252 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg);
253 if ((phyreg != 0xFFFF) &&
254 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
255 /* Found a valid PHY address */
256 debug("Default phy address %d is valid\n",
260 debug("PHY address is not setup correctly %d\n",
266 debug("detecting phy address\n");
267 if (priv->phyaddr == -1) {
268 /* detect the PHY address */
269 for (i = 31; i >= 0; i--) {
270 phyread(priv, i, PHY_DETECT_REG, &phyreg);
271 if ((phyreg != 0xFFFF) &&
272 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
273 /* Found a valid PHY address */
275 debug("Found valid phy address, %d\n", i);
280 printf("PHY is not detected\n");
284 static int zynq_gem_setup_mac(struct udevice *dev)
286 u32 i, macaddrlow, macaddrhigh;
287 struct eth_pdata *pdata = dev_get_platdata(dev);
288 struct zynq_gem_priv *priv = dev_get_priv(dev);
289 struct zynq_gem_regs *regs = priv->iobase;
291 /* Set the MAC bits [31:0] in BOT */
292 macaddrlow = pdata->enetaddr[0];
293 macaddrlow |= pdata->enetaddr[1] << 8;
294 macaddrlow |= pdata->enetaddr[2] << 16;
295 macaddrlow |= pdata->enetaddr[3] << 24;
297 /* Set MAC bits [47:32] in TOP */
298 macaddrhigh = pdata->enetaddr[4];
299 macaddrhigh |= pdata->enetaddr[5] << 8;
301 for (i = 0; i < 4; i++) {
302 writel(0, ®s->laddr[i][LADDR_LOW]);
303 writel(0, ®s->laddr[i][LADDR_HIGH]);
304 /* Do not use MATCHx register */
305 writel(0, ®s->match[i]);
308 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]);
309 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]);
314 static int zynq_phy_init(struct udevice *dev)
317 struct zynq_gem_priv *priv = dev_get_priv(dev);
318 struct zynq_gem_regs *regs = priv->iobase;
319 const u32 supported = SUPPORTED_10baseT_Half |
320 SUPPORTED_10baseT_Full |
321 SUPPORTED_100baseT_Half |
322 SUPPORTED_100baseT_Full |
323 SUPPORTED_1000baseT_Half |
324 SUPPORTED_1000baseT_Full;
326 /* Enable only MDIO bus */
327 writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl);
329 ret = phy_detection(dev);
331 printf("GEM PHY init failed\n");
335 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
340 priv->phydev->supported = supported | ADVERTISED_Pause |
341 ADVERTISED_Asym_Pause;
342 priv->phydev->advertising = priv->phydev->supported;
343 phy_config(priv->phydev);
348 static int zynq_gem_init(struct udevice *dev)
351 unsigned long clk_rate = 0;
352 struct zynq_gem_priv *priv = dev_get_priv(dev);
353 struct zynq_gem_regs *regs = priv->iobase;
354 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
355 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
358 /* Disable all interrupts */
359 writel(0xFFFFFFFF, ®s->idr);
361 /* Disable the receiver & transmitter */
362 writel(0, ®s->nwctrl);
363 writel(0, ®s->txsr);
364 writel(0, ®s->rxsr);
365 writel(0, ®s->phymntnc);
367 /* Clear the Hash registers for the mac address
368 * pointed by AddressPtr
370 writel(0x0, ®s->hashl);
371 /* Write bits [63:32] in TOP */
372 writel(0x0, ®s->hashh);
374 /* Clear all counters */
375 for (i = 0; i < STAT_SIZE; i++)
376 readl(®s->stat[i]);
378 /* Setup RxBD space */
379 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
381 for (i = 0; i < RX_BUF; i++) {
382 priv->rx_bd[i].status = 0xF0000000;
383 priv->rx_bd[i].addr =
384 ((ulong)(priv->rxbuffers) +
385 (i * PKTSIZE_ALIGN));
387 /* WRAP bit to last BD */
388 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
389 /* Write RxBDs to IP */
390 writel((ulong)priv->rx_bd, ®s->rxqbase);
392 /* Setup for DMA Configuration register */
393 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr);
395 /* Setup for Network Control register, MDIO, Rx and Tx enable */
396 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
398 /* Disable the second priority queue */
399 dummy_tx_bd->addr = 0;
400 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
401 ZYNQ_GEM_TXBUF_LAST_MASK|
402 ZYNQ_GEM_TXBUF_USED_MASK;
404 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
405 ZYNQ_GEM_RXBUF_NEW_MASK;
406 dummy_rx_bd->status = 0;
407 flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd +
408 sizeof(dummy_tx_bd));
409 flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd +
410 sizeof(dummy_rx_bd));
412 writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr);
413 writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr);
418 phy_startup(priv->phydev);
420 if (!priv->phydev->link) {
421 printf("%s: No link.\n", priv->phydev->dev->name);
425 switch (priv->phydev->speed) {
427 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
429 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
432 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100,
434 clk_rate = ZYNQ_GEM_FREQUENCY_100;
437 clk_rate = ZYNQ_GEM_FREQUENCY_10;
441 /* Change the rclk and clk only not using EMIO interface */
443 zynq_slcr_gem_clk_setup((ulong)priv->iobase !=
444 ZYNQ_GEM_BASEADDR0, clk_rate);
446 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
447 ZYNQ_GEM_NWCTRL_TXEN_MASK);
452 static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
455 struct zynq_gem_priv *priv = dev_get_priv(dev);
456 struct zynq_gem_regs *regs = priv->iobase;
457 struct emac_bd *current_bd = &priv->tx_bd[1];
460 memset(priv->tx_bd, 0, sizeof(struct emac_bd));
462 priv->tx_bd->addr = (ulong)ptr;
463 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
464 ZYNQ_GEM_TXBUF_LAST_MASK;
465 /* Dummy descriptor to mark it as the last in descriptor chain */
466 current_bd->addr = 0x0;
467 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
468 ZYNQ_GEM_TXBUF_LAST_MASK|
469 ZYNQ_GEM_TXBUF_USED_MASK;
472 writel((ulong)priv->tx_bd, ®s->txqbase);
475 addr &= ~(ARCH_DMA_MINALIGN - 1);
476 size = roundup(len, ARCH_DMA_MINALIGN);
477 flush_dcache_range(addr, addr + size);
479 addr = (ulong)priv->rxbuffers;
480 addr &= ~(ARCH_DMA_MINALIGN - 1);
481 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
482 flush_dcache_range(addr, addr + size);
486 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
488 /* Read TX BD status */
489 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
490 printf("TX buffers exhausted in mid frame\n");
492 return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE,
496 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
497 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
501 struct zynq_gem_priv *priv = dev_get_priv(dev);
502 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
504 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
507 if (!(current_bd->status &
508 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
509 printf("GEM: SOF or EOF not set for last buffer received!\n");
513 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
515 printf("%s: Zero size packet?\n", __func__);
519 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
520 addr &= ~(ARCH_DMA_MINALIGN - 1);
521 *packetp = (uchar *)(uintptr_t)addr;
526 static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
528 struct zynq_gem_priv *priv = dev_get_priv(dev);
529 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
530 struct emac_bd *first_bd;
532 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
533 priv->rx_first_buf = priv->rxbd_current;
535 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
536 current_bd->status = 0xF0000000; /* FIXME */
539 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
540 first_bd = &priv->rx_bd[priv->rx_first_buf];
541 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
542 first_bd->status = 0xF0000000;
545 if ((++priv->rxbd_current) >= RX_BUF)
546 priv->rxbd_current = 0;
551 static void zynq_gem_halt(struct udevice *dev)
553 struct zynq_gem_priv *priv = dev_get_priv(dev);
554 struct zynq_gem_regs *regs = priv->iobase;
556 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
557 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
560 static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
563 struct zynq_gem_priv *priv = bus->priv;
567 ret = phyread(priv, addr, reg, &val);
568 debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
572 static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
575 struct zynq_gem_priv *priv = bus->priv;
577 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
578 return phywrite(priv, addr, reg, value);
581 static int zynq_gem_probe(struct udevice *dev)
584 struct zynq_gem_priv *priv = dev_get_priv(dev);
587 /* Align rxbuffers to ARCH_DMA_MINALIGN */
588 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
589 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
591 /* Align bd_space to MMU_SECTION_SHIFT */
592 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
593 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
594 BD_SPACE, DCACHE_OFF);
596 /* Initialize the bd spaces for tx and rx bd's */
597 priv->tx_bd = (struct emac_bd *)bd_space;
598 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
600 priv->bus = mdio_alloc();
601 priv->bus->read = zynq_gem_miiphy_read;
602 priv->bus->write = zynq_gem_miiphy_write;
603 priv->bus->priv = priv;
604 strcpy(priv->bus->name, "gem");
606 ret = mdio_register(priv->bus);
615 static int zynq_gem_remove(struct udevice *dev)
617 struct zynq_gem_priv *priv = dev_get_priv(dev);
620 mdio_unregister(priv->bus);
621 mdio_free(priv->bus);
626 static const struct eth_ops zynq_gem_ops = {
627 .start = zynq_gem_init,
628 .send = zynq_gem_send,
629 .recv = zynq_gem_recv,
630 .free_pkt = zynq_gem_free_pkt,
631 .stop = zynq_gem_halt,
632 .write_hwaddr = zynq_gem_setup_mac,
635 static int zynq_gem_ofdata_to_platdata(struct udevice *dev)
637 struct eth_pdata *pdata = dev_get_platdata(dev);
638 struct zynq_gem_priv *priv = dev_get_priv(dev);
640 const char *phy_mode;
642 pdata->iobase = (phys_addr_t)dev_get_addr(dev);
643 priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
644 /* Hardcode for now */
648 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
651 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
653 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
655 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
656 if (pdata->phy_interface == -1) {
657 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
660 priv->interface = pdata->phy_interface;
662 printf("ZYNQ GEM: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
663 priv->phyaddr, phy_string_for_interface(priv->interface));
668 static const struct udevice_id zynq_gem_ids[] = {
669 { .compatible = "cdns,zynqmp-gem" },
670 { .compatible = "cdns,zynq-gem" },
671 { .compatible = "cdns,gem" },
675 U_BOOT_DRIVER(zynq_gem) = {
678 .of_match = zynq_gem_ids,
679 .ofdata_to_platdata = zynq_gem_ofdata_to_platdata,
680 .probe = zynq_gem_probe,
681 .remove = zynq_gem_remove,
682 .ops = &zynq_gem_ops,
683 .priv_auto_alloc_size = sizeof(struct zynq_gem_priv),
684 .platdata_auto_alloc_size = sizeof(struct eth_pdata),