2 * (C) Copyright 2011 Michal Simek
4 * Michal SIMEK <monstr@monstr.eu>
6 * Based on Xilinx gmac driver:
7 * (C) Copyright 2011 Xilinx
9 * SPDX-License-Identifier: GPL-2.0+
23 #include <asm/system.h>
24 #include <asm/arch/hardware.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm-generic/errno.h>
28 #if !defined(CONFIG_PHYLIB)
29 # error XILINX_GEM_ETHERNET requires PHYLIB
32 /* Bit/mask specification */
33 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
34 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
35 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
36 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
37 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
39 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
40 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
41 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
43 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
44 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
45 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
47 /* Wrap bit, last descriptor */
48 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
49 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
50 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
52 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
53 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
54 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
55 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
57 #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */
58 #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
59 #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
60 #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
61 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */
64 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
66 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
69 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
70 ZYNQ_GEM_NWCFG_FDEN | \
71 ZYNQ_GEM_NWCFG_FSREM | \
72 ZYNQ_GEM_NWCFG_MDCCLKDIV)
74 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
76 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
77 /* Use full configured addressable space (8 Kb) */
78 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
79 /* Use full configured addressable space (4 Kb) */
80 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
81 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
82 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000
84 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
85 ZYNQ_GEM_DMACR_RXSIZE | \
86 ZYNQ_GEM_DMACR_TXSIZE | \
89 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
91 /* Use MII register 1 (MII status register) to detect PHY */
92 #define PHY_DETECT_REG 1
94 /* Mask used to verify certain PHY features (or register contents)
95 * in the register above:
96 * 0x1000: 10Mbps full duplex support
97 * 0x0800: 10Mbps half duplex support
98 * 0x0008: Auto-negotiation support
100 #define PHY_DETECT_MASK 0x1808
102 /* TX BD status masks */
103 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
104 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
105 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
107 /* Clock frequencies for different speeds */
108 #define ZYNQ_GEM_FREQUENCY_10 2500000UL
109 #define ZYNQ_GEM_FREQUENCY_100 25000000UL
110 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
112 /* Device registers */
113 struct zynq_gem_regs {
114 u32 nwctrl; /* 0x0 - Network Control reg */
115 u32 nwcfg; /* 0x4 - Network Config reg */
116 u32 nwsr; /* 0x8 - Network Status reg */
118 u32 dmacr; /* 0x10 - DMA Control reg */
119 u32 txsr; /* 0x14 - TX Status reg */
120 u32 rxqbase; /* 0x18 - RX Q Base address reg */
121 u32 txqbase; /* 0x1c - TX Q Base address reg */
122 u32 rxsr; /* 0x20 - RX Status reg */
124 u32 idr; /* 0x2c - Interrupt Disable reg */
126 u32 phymntnc; /* 0x34 - Phy Maintaince reg */
128 u32 hashl; /* 0x80 - Hash Low address reg */
129 u32 hashh; /* 0x84 - Hash High address reg */
132 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
133 u32 match[4]; /* 0xa8 - Type ID1 Match reg */
136 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
138 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
140 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
145 u32 addr; /* Next descriptor pointer */
150 /* Page table entries are set to 1MB, or multiples of 1MB
151 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
153 #define BD_SPACE 0x100000
154 /* BD separation space */
155 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd))
157 /* Setup the first free TX descriptor */
158 #define TX_FREE_DESC 2
160 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
161 struct zynq_gem_priv {
162 struct emac_bd *tx_bd;
163 struct emac_bd *rx_bd;
170 phy_interface_t interface;
171 struct phy_device *phydev;
175 static inline int mdio_wait(struct eth_device *dev)
177 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
180 /* Wait till MDIO interface is ready to accept a new transaction. */
182 if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
188 printf("%s: Timeout\n", __func__);
195 static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
199 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
204 /* Construct mgtcr mask for the operation */
205 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
206 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
207 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
209 /* Write mgtcr and wait for completion */
210 writel(mgtcr, ®s->phymntnc);
215 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
216 *data = readl(®s->phymntnc);
221 static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val)
225 ret = phy_setup_op(dev, phy_addr, regnum,
226 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
229 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
230 phy_addr, regnum, *val);
235 static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data)
237 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
240 return phy_setup_op(dev, phy_addr, regnum,
241 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
244 static void phy_detection(struct eth_device *dev)
248 struct zynq_gem_priv *priv = dev->priv;
250 if (priv->phyaddr != -1) {
251 phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg);
252 if ((phyreg != 0xFFFF) &&
253 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
254 /* Found a valid PHY address */
255 debug("Default phy address %d is valid\n",
259 debug("PHY address is not setup correctly %d\n",
265 debug("detecting phy address\n");
266 if (priv->phyaddr == -1) {
267 /* detect the PHY address */
268 for (i = 31; i >= 0; i--) {
269 phyread(dev, i, PHY_DETECT_REG, &phyreg);
270 if ((phyreg != 0xFFFF) &&
271 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
272 /* Found a valid PHY address */
274 debug("Found valid phy address, %d\n", i);
279 printf("PHY is not detected\n");
282 static int zynq_gem_setup_mac(struct eth_device *dev)
284 u32 i, macaddrlow, macaddrhigh;
285 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
287 /* Set the MAC bits [31:0] in BOT */
288 macaddrlow = dev->enetaddr[0];
289 macaddrlow |= dev->enetaddr[1] << 8;
290 macaddrlow |= dev->enetaddr[2] << 16;
291 macaddrlow |= dev->enetaddr[3] << 24;
293 /* Set MAC bits [47:32] in TOP */
294 macaddrhigh = dev->enetaddr[4];
295 macaddrhigh |= dev->enetaddr[5] << 8;
297 for (i = 0; i < 4; i++) {
298 writel(0, ®s->laddr[i][LADDR_LOW]);
299 writel(0, ®s->laddr[i][LADDR_HIGH]);
300 /* Do not use MATCHx register */
301 writel(0, ®s->match[i]);
304 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]);
305 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]);
310 static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
313 unsigned long clk_rate = 0;
314 struct phy_device *phydev;
315 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
316 struct zynq_gem_priv *priv = dev->priv;
317 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
318 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
319 const u32 supported = SUPPORTED_10baseT_Half |
320 SUPPORTED_10baseT_Full |
321 SUPPORTED_100baseT_Half |
322 SUPPORTED_100baseT_Full |
323 SUPPORTED_1000baseT_Half |
324 SUPPORTED_1000baseT_Full;
327 /* Disable all interrupts */
328 writel(0xFFFFFFFF, ®s->idr);
330 /* Disable the receiver & transmitter */
331 writel(0, ®s->nwctrl);
332 writel(0, ®s->txsr);
333 writel(0, ®s->rxsr);
334 writel(0, ®s->phymntnc);
336 /* Clear the Hash registers for the mac address
337 * pointed by AddressPtr
339 writel(0x0, ®s->hashl);
340 /* Write bits [63:32] in TOP */
341 writel(0x0, ®s->hashh);
343 /* Clear all counters */
344 for (i = 0; i < STAT_SIZE; i++)
345 readl(®s->stat[i]);
347 /* Setup RxBD space */
348 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
350 for (i = 0; i < RX_BUF; i++) {
351 priv->rx_bd[i].status = 0xF0000000;
352 priv->rx_bd[i].addr =
353 ((ulong)(priv->rxbuffers) +
354 (i * PKTSIZE_ALIGN));
356 /* WRAP bit to last BD */
357 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
358 /* Write RxBDs to IP */
359 writel((ulong)priv->rx_bd, ®s->rxqbase);
361 /* Setup for DMA Configuration register */
362 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr);
364 /* Setup for Network Control register, MDIO, Rx and Tx enable */
365 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
367 /* Disable the second priority queue */
368 dummy_tx_bd->addr = 0;
369 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
370 ZYNQ_GEM_TXBUF_LAST_MASK|
371 ZYNQ_GEM_TXBUF_USED_MASK;
373 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
374 ZYNQ_GEM_RXBUF_NEW_MASK;
375 dummy_rx_bd->status = 0;
376 flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd +
377 sizeof(dummy_tx_bd));
378 flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd +
379 sizeof(dummy_rx_bd));
381 writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr);
382 writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr);
389 /* interface - look at tsec */
390 phydev = phy_connect(priv->bus, priv->phyaddr, dev,
393 phydev->supported = supported | ADVERTISED_Pause |
394 ADVERTISED_Asym_Pause;
395 phydev->advertising = phydev->supported;
396 priv->phydev = phydev;
401 printf("%s: No link.\n", phydev->dev->name);
405 switch (phydev->speed) {
407 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
409 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
412 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100,
414 clk_rate = ZYNQ_GEM_FREQUENCY_100;
417 clk_rate = ZYNQ_GEM_FREQUENCY_10;
421 /* Change the rclk and clk only not using EMIO interface */
423 zynq_slcr_gem_clk_setup(dev->iobase !=
424 ZYNQ_GEM_BASEADDR0, clk_rate);
426 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
427 ZYNQ_GEM_NWCTRL_TXEN_MASK);
432 static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
433 bool set, unsigned int timeout)
436 unsigned long start = get_timer(0);
444 if ((val & mask) == mask)
447 if (get_timer(start) > timeout)
453 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
454 func, reg, mask, set);
459 static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
462 struct zynq_gem_priv *priv = dev->priv;
463 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
464 struct emac_bd *current_bd = &priv->tx_bd[1];
467 memset(priv->tx_bd, 0, sizeof(struct emac_bd));
469 priv->tx_bd->addr = (ulong)ptr;
470 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
471 ZYNQ_GEM_TXBUF_LAST_MASK;
472 /* Dummy descriptor to mark it as the last in descriptor chain */
473 current_bd->addr = 0x0;
474 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
475 ZYNQ_GEM_TXBUF_LAST_MASK|
476 ZYNQ_GEM_TXBUF_USED_MASK;
479 writel((ulong)priv->tx_bd, ®s->txqbase);
482 addr &= ~(ARCH_DMA_MINALIGN - 1);
483 size = roundup(len, ARCH_DMA_MINALIGN);
484 flush_dcache_range(addr, addr + size);
486 addr = (ulong)priv->rxbuffers;
487 addr &= ~(ARCH_DMA_MINALIGN - 1);
488 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
489 flush_dcache_range(addr, addr + size);
493 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
495 /* Read TX BD status */
496 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
497 printf("TX buffers exhausted in mid frame\n");
499 return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE,
503 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
504 static int zynq_gem_recv(struct eth_device *dev)
507 struct zynq_gem_priv *priv = dev->priv;
508 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
509 struct emac_bd *first_bd;
511 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
514 if (!(current_bd->status &
515 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
516 printf("GEM: SOF or EOF not set for last buffer received!\n");
520 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
522 u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
523 addr &= ~(ARCH_DMA_MINALIGN - 1);
525 net_process_received_packet((u8 *)(ulong)addr, frame_len);
527 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
528 priv->rx_first_buf = priv->rxbd_current;
530 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
531 current_bd->status = 0xF0000000; /* FIXME */
534 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
535 first_bd = &priv->rx_bd[priv->rx_first_buf];
536 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
537 first_bd->status = 0xF0000000;
540 if ((++priv->rxbd_current) >= RX_BUF)
541 priv->rxbd_current = 0;
547 static void zynq_gem_halt(struct eth_device *dev)
549 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
551 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
552 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
555 static int zynq_gem_miiphyread(const char *devname, uchar addr,
556 uchar reg, ushort *val)
558 struct eth_device *dev = eth_get_dev();
561 ret = phyread(dev, addr, reg, val);
562 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
566 static int zynq_gem_miiphy_write(const char *devname, uchar addr,
567 uchar reg, ushort val)
569 struct eth_device *dev = eth_get_dev();
571 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
572 return phywrite(dev, addr, reg, val);
575 int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
576 int phy_addr, u32 emio)
578 struct eth_device *dev;
579 struct zynq_gem_priv *priv;
582 dev = calloc(1, sizeof(*dev));
586 dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
587 if (dev->priv == NULL) {
593 /* Align rxbuffers to ARCH_DMA_MINALIGN */
594 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
595 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
597 /* Align bd_space to MMU_SECTION_SHIFT */
598 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
599 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
600 BD_SPACE, DCACHE_OFF);
602 /* Initialize the bd spaces for tx and rx bd's */
603 priv->tx_bd = (struct emac_bd *)bd_space;
604 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
606 priv->phyaddr = phy_addr;
609 #ifndef CONFIG_ZYNQ_GEM_INTERFACE
610 priv->interface = PHY_INTERFACE_MODE_MII;
612 priv->interface = CONFIG_ZYNQ_GEM_INTERFACE;
615 sprintf(dev->name, "Gem.%lx", base_addr);
617 dev->iobase = base_addr;
619 dev->init = zynq_gem_init;
620 dev->halt = zynq_gem_halt;
621 dev->send = zynq_gem_send;
622 dev->recv = zynq_gem_recv;
623 dev->write_hwaddr = zynq_gem_setup_mac;
627 miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
628 priv->bus = miiphy_get_dev_by_name(dev->name);
633 #if CONFIG_IS_ENABLED(OF_CONTROL)
634 int zynq_gem_of_init(const void *blob)
640 debug("ZYNQ GEM: Initialization\n");
643 offset = fdt_node_offset_by_compatible(blob, offset,
644 "xlnx,ps7-ethernet-1.00.a");
646 reg = fdtdec_get_addr(blob, offset, "reg");
647 if (reg != FDT_ADDR_T_NONE) {
648 offset = fdtdec_lookup_phandle(blob, offset,
651 phy_reg = fdtdec_get_addr(blob, offset,
656 debug("ZYNQ GEM: addr %x, phyaddr %x\n",
659 ret |= zynq_gem_initialize(NULL, reg,
663 debug("ZYNQ GEM: Can't get base address\n");
667 } while (offset != -1);