2 * (C) Copyright 2011 Michal Simek
4 * Michal SIMEK <monstr@monstr.eu>
6 * Based on Xilinx gmac driver:
7 * (C) Copyright 2011 Xilinx
9 * SPDX-License-Identifier: GPL-2.0+
23 #include <asm/system.h>
24 #include <asm/arch/hardware.h>
25 #include <asm/arch/sys_proto.h>
27 #if !defined(CONFIG_PHYLIB)
28 # error XILINX_GEM_ETHERNET requires PHYLIB
31 /* Bit/mask specification */
32 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
33 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
34 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
35 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
36 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
38 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
39 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
40 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
42 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
43 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
44 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
46 /* Wrap bit, last descriptor */
47 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
48 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
50 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
51 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
52 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
53 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
55 #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */
56 #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
57 #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
58 #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
59 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */
60 #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */
63 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
65 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
68 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
69 ZYNQ_GEM_NWCFG_FDEN | \
70 ZYNQ_GEM_NWCFG_FSREM | \
71 ZYNQ_GEM_NWCFG_MDCCLKDIV)
73 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
75 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
76 /* Use full configured addressable space (8 Kb) */
77 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
78 /* Use full configured addressable space (4 Kb) */
79 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
80 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
81 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000
83 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
84 ZYNQ_GEM_DMACR_RXSIZE | \
85 ZYNQ_GEM_DMACR_TXSIZE | \
88 /* Use MII register 1 (MII status register) to detect PHY */
89 #define PHY_DETECT_REG 1
91 /* Mask used to verify certain PHY features (or register contents)
92 * in the register above:
93 * 0x1000: 10Mbps full duplex support
94 * 0x0800: 10Mbps half duplex support
95 * 0x0008: Auto-negotiation support
97 #define PHY_DETECT_MASK 0x1808
99 /* TX BD status masks */
100 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
101 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
102 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
104 /* Clock frequencies for different speeds */
105 #define ZYNQ_GEM_FREQUENCY_10 2500000UL
106 #define ZYNQ_GEM_FREQUENCY_100 25000000UL
107 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
109 /* Device registers */
110 struct zynq_gem_regs {
111 u32 nwctrl; /* 0x0 - Network Control reg */
112 u32 nwcfg; /* 0x4 - Network Config reg */
113 u32 nwsr; /* 0x8 - Network Status reg */
115 u32 dmacr; /* 0x10 - DMA Control reg */
116 u32 txsr; /* 0x14 - TX Status reg */
117 u32 rxqbase; /* 0x18 - RX Q Base address reg */
118 u32 txqbase; /* 0x1c - TX Q Base address reg */
119 u32 rxsr; /* 0x20 - RX Status reg */
121 u32 idr; /* 0x2c - Interrupt Disable reg */
123 u32 phymntnc; /* 0x34 - Phy Maintaince reg */
125 u32 hashl; /* 0x80 - Hash Low address reg */
126 u32 hashh; /* 0x84 - Hash High address reg */
129 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
130 u32 match[4]; /* 0xa8 - Type ID1 Match reg */
132 u32 stat[44]; /* 0x100 - Octects transmitted Low reg - stat start */
137 u32 addr; /* Next descriptor pointer */
142 /* Page table entries are set to 1MB, or multiples of 1MB
143 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
145 #define BD_SPACE 0x100000
146 /* BD separation space */
147 #define BD_SEPRN_SPACE 64
149 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
150 struct zynq_gem_priv {
151 struct emac_bd *tx_bd;
152 struct emac_bd *rx_bd;
159 phy_interface_t interface;
160 struct phy_device *phydev;
164 static inline int mdio_wait(struct eth_device *dev)
166 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
169 /* Wait till MDIO interface is ready to accept a new transaction. */
171 if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
177 printf("%s: Timeout\n", __func__);
184 static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
188 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
193 /* Construct mgtcr mask for the operation */
194 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
195 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
196 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
198 /* Write mgtcr and wait for completion */
199 writel(mgtcr, ®s->phymntnc);
204 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
205 *data = readl(®s->phymntnc);
210 static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val)
214 ret = phy_setup_op(dev, phy_addr, regnum,
215 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
218 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
219 phy_addr, regnum, *val);
224 static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data)
226 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
229 return phy_setup_op(dev, phy_addr, regnum,
230 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
233 static void phy_detection(struct eth_device *dev)
237 struct zynq_gem_priv *priv = dev->priv;
239 if (priv->phyaddr != -1) {
240 phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg);
241 if ((phyreg != 0xFFFF) &&
242 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
243 /* Found a valid PHY address */
244 debug("Default phy address %d is valid\n",
248 debug("PHY address is not setup correctly %d\n",
254 debug("detecting phy address\n");
255 if (priv->phyaddr == -1) {
256 /* detect the PHY address */
257 for (i = 31; i >= 0; i--) {
258 phyread(dev, i, PHY_DETECT_REG, &phyreg);
259 if ((phyreg != 0xFFFF) &&
260 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
261 /* Found a valid PHY address */
263 debug("Found valid phy address, %d\n", i);
268 printf("PHY is not detected\n");
271 static int zynq_gem_setup_mac(struct eth_device *dev)
273 u32 i, macaddrlow, macaddrhigh;
274 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
276 /* Set the MAC bits [31:0] in BOT */
277 macaddrlow = dev->enetaddr[0];
278 macaddrlow |= dev->enetaddr[1] << 8;
279 macaddrlow |= dev->enetaddr[2] << 16;
280 macaddrlow |= dev->enetaddr[3] << 24;
282 /* Set MAC bits [47:32] in TOP */
283 macaddrhigh = dev->enetaddr[4];
284 macaddrhigh |= dev->enetaddr[5] << 8;
286 for (i = 0; i < 4; i++) {
287 writel(0, ®s->laddr[i][LADDR_LOW]);
288 writel(0, ®s->laddr[i][LADDR_HIGH]);
289 /* Do not use MATCHx register */
290 writel(0, ®s->match[i]);
293 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]);
294 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]);
299 static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
302 unsigned long clk_rate = 0;
303 struct phy_device *phydev;
304 const u32 stat_size = (sizeof(struct zynq_gem_regs) -
305 offsetof(struct zynq_gem_regs, stat)) / 4;
306 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
307 struct zynq_gem_priv *priv = dev->priv;
308 const u32 supported = SUPPORTED_10baseT_Half |
309 SUPPORTED_10baseT_Full |
310 SUPPORTED_100baseT_Half |
311 SUPPORTED_100baseT_Full |
312 SUPPORTED_1000baseT_Half |
313 SUPPORTED_1000baseT_Full;
316 /* Disable all interrupts */
317 writel(0xFFFFFFFF, ®s->idr);
319 /* Disable the receiver & transmitter */
320 writel(0, ®s->nwctrl);
321 writel(0, ®s->txsr);
322 writel(0, ®s->rxsr);
323 writel(0, ®s->phymntnc);
325 /* Clear the Hash registers for the mac address
326 * pointed by AddressPtr
328 writel(0x0, ®s->hashl);
329 /* Write bits [63:32] in TOP */
330 writel(0x0, ®s->hashh);
332 /* Clear all counters */
333 for (i = 0; i <= stat_size; i++)
334 readl(®s->stat[i]);
336 /* Setup RxBD space */
337 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
339 for (i = 0; i < RX_BUF; i++) {
340 priv->rx_bd[i].status = 0xF0000000;
341 priv->rx_bd[i].addr =
342 ((ulong)(priv->rxbuffers) +
343 (i * PKTSIZE_ALIGN));
345 /* WRAP bit to last BD */
346 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
347 /* Write RxBDs to IP */
348 writel((ulong)priv->rx_bd, ®s->rxqbase);
350 /* Setup for DMA Configuration register */
351 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr);
353 /* Setup for Network Control register, MDIO, Rx and Tx enable */
354 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
361 /* interface - look at tsec */
362 phydev = phy_connect(priv->bus, priv->phyaddr, dev,
365 phydev->supported = supported | ADVERTISED_Pause |
366 ADVERTISED_Asym_Pause;
367 phydev->advertising = phydev->supported;
368 priv->phydev = phydev;
373 printf("%s: No link.\n", phydev->dev->name);
377 switch (phydev->speed) {
379 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
381 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
384 clrsetbits_le32(®s->nwcfg, ZYNQ_GEM_NWCFG_SPEED1000,
385 ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100);
386 clk_rate = ZYNQ_GEM_FREQUENCY_100;
389 clk_rate = ZYNQ_GEM_FREQUENCY_10;
393 /* Change the rclk and clk only not using EMIO interface */
395 zynq_slcr_gem_clk_setup(dev->iobase !=
396 ZYNQ_GEM_BASEADDR0, clk_rate);
398 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
399 ZYNQ_GEM_NWCTRL_TXEN_MASK);
404 static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
407 struct zynq_gem_priv *priv = dev->priv;
408 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
411 writel((ulong)priv->tx_bd, ®s->txqbase);
414 memset(priv->tx_bd, 0, sizeof(struct emac_bd));
416 priv->tx_bd->addr = (ulong)ptr;
417 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
418 ZYNQ_GEM_TXBUF_LAST_MASK |
419 ZYNQ_GEM_TXBUF_WRAP_MASK;
422 addr &= ~(ARCH_DMA_MINALIGN - 1);
423 size = roundup(len, ARCH_DMA_MINALIGN);
424 flush_dcache_range(addr, addr + size);
426 addr = (ulong)priv->rxbuffers;
427 addr &= ~(ARCH_DMA_MINALIGN - 1);
428 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
429 flush_dcache_range(addr, addr + size);
433 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
435 /* Read TX BD status */
436 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_UNDERRUN)
437 printf("TX underrun\n");
438 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
439 printf("TX buffers exhausted in mid frame\n");
444 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
445 static int zynq_gem_recv(struct eth_device *dev)
448 struct zynq_gem_priv *priv = dev->priv;
449 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
450 struct emac_bd *first_bd;
452 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
455 if (!(current_bd->status &
456 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
457 printf("GEM: SOF or EOF not set for last buffer received!\n");
461 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
463 u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
464 addr &= ~(ARCH_DMA_MINALIGN - 1);
466 net_process_received_packet((u8 *)(ulong)addr, frame_len);
468 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
469 priv->rx_first_buf = priv->rxbd_current;
471 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
472 current_bd->status = 0xF0000000; /* FIXME */
475 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
476 first_bd = &priv->rx_bd[priv->rx_first_buf];
477 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
478 first_bd->status = 0xF0000000;
481 if ((++priv->rxbd_current) >= RX_BUF)
482 priv->rxbd_current = 0;
488 static void zynq_gem_halt(struct eth_device *dev)
490 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
492 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
493 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
496 static int zynq_gem_miiphyread(const char *devname, uchar addr,
497 uchar reg, ushort *val)
499 struct eth_device *dev = eth_get_dev();
502 ret = phyread(dev, addr, reg, val);
503 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
507 static int zynq_gem_miiphy_write(const char *devname, uchar addr,
508 uchar reg, ushort val)
510 struct eth_device *dev = eth_get_dev();
512 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
513 return phywrite(dev, addr, reg, val);
516 int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
517 int phy_addr, u32 emio)
519 struct eth_device *dev;
520 struct zynq_gem_priv *priv;
523 dev = calloc(1, sizeof(*dev));
527 dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
528 if (dev->priv == NULL) {
534 /* Align rxbuffers to ARCH_DMA_MINALIGN */
535 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
536 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
538 /* Align bd_space to MMU_SECTION_SHIFT */
539 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
540 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
541 BD_SPACE, DCACHE_OFF);
543 /* Initialize the bd spaces for tx and rx bd's */
544 priv->tx_bd = (struct emac_bd *)bd_space;
545 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
547 priv->phyaddr = phy_addr;
550 #ifndef CONFIG_ZYNQ_GEM_INTERFACE
551 priv->interface = PHY_INTERFACE_MODE_MII;
553 priv->interface = CONFIG_ZYNQ_GEM_INTERFACE;
556 sprintf(dev->name, "Gem.%lx", base_addr);
558 dev->iobase = base_addr;
560 dev->init = zynq_gem_init;
561 dev->halt = zynq_gem_halt;
562 dev->send = zynq_gem_send;
563 dev->recv = zynq_gem_recv;
564 dev->write_hwaddr = zynq_gem_setup_mac;
568 miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
569 priv->bus = miiphy_get_dev_by_name(dev->name);
574 #if CONFIG_IS_ENABLED(OF_CONTROL)
575 int zynq_gem_of_init(const void *blob)
581 debug("ZYNQ GEM: Initialization\n");
584 offset = fdt_node_offset_by_compatible(blob, offset,
585 "xlnx,ps7-ethernet-1.00.a");
587 reg = fdtdec_get_addr(blob, offset, "reg");
588 if (reg != FDT_ADDR_T_NONE) {
589 offset = fdtdec_lookup_phandle(blob, offset,
592 phy_reg = fdtdec_get_addr(blob, offset,
597 debug("ZYNQ GEM: addr %x, phyaddr %x\n",
600 ret |= zynq_gem_initialize(NULL, reg,
604 debug("ZYNQ GEM: Can't get base address\n");
608 } while (offset != -1);