2 * (C) Copyright 2011 Michal Simek
4 * Michal SIMEK <monstr@monstr.eu>
6 * Based on Xilinx gmac driver:
7 * (C) Copyright 2011 Xilinx
9 * SPDX-License-Identifier: GPL-2.0+
21 #include <asm/system.h>
22 #include <asm/arch/hardware.h>
23 #include <asm/arch/sys_proto.h>
24 #include <asm-generic/errno.h>
26 #if !defined(CONFIG_PHYLIB)
27 # error XILINX_GEM_ETHERNET requires PHYLIB
30 /* Bit/mask specification */
31 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
32 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
33 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
34 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
35 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
37 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
38 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
39 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
41 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
42 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
43 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
45 /* Wrap bit, last descriptor */
46 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
47 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
48 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
50 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
51 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
52 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
53 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
55 #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */
56 #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
57 #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
58 #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
59 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */
62 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
64 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
67 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
68 ZYNQ_GEM_NWCFG_FDEN | \
69 ZYNQ_GEM_NWCFG_FSREM | \
70 ZYNQ_GEM_NWCFG_MDCCLKDIV)
72 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
74 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
75 /* Use full configured addressable space (8 Kb) */
76 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
77 /* Use full configured addressable space (4 Kb) */
78 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
79 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
80 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000
82 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
83 ZYNQ_GEM_DMACR_RXSIZE | \
84 ZYNQ_GEM_DMACR_TXSIZE | \
87 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
89 /* Use MII register 1 (MII status register) to detect PHY */
90 #define PHY_DETECT_REG 1
92 /* Mask used to verify certain PHY features (or register contents)
93 * in the register above:
94 * 0x1000: 10Mbps full duplex support
95 * 0x0800: 10Mbps half duplex support
96 * 0x0008: Auto-negotiation support
98 #define PHY_DETECT_MASK 0x1808
100 /* TX BD status masks */
101 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
102 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
103 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
105 /* Clock frequencies for different speeds */
106 #define ZYNQ_GEM_FREQUENCY_10 2500000UL
107 #define ZYNQ_GEM_FREQUENCY_100 25000000UL
108 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
110 /* Device registers */
111 struct zynq_gem_regs {
112 u32 nwctrl; /* 0x0 - Network Control reg */
113 u32 nwcfg; /* 0x4 - Network Config reg */
114 u32 nwsr; /* 0x8 - Network Status reg */
116 u32 dmacr; /* 0x10 - DMA Control reg */
117 u32 txsr; /* 0x14 - TX Status reg */
118 u32 rxqbase; /* 0x18 - RX Q Base address reg */
119 u32 txqbase; /* 0x1c - TX Q Base address reg */
120 u32 rxsr; /* 0x20 - RX Status reg */
122 u32 idr; /* 0x2c - Interrupt Disable reg */
124 u32 phymntnc; /* 0x34 - Phy Maintaince reg */
126 u32 hashl; /* 0x80 - Hash Low address reg */
127 u32 hashh; /* 0x84 - Hash High address reg */
130 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
131 u32 match[4]; /* 0xa8 - Type ID1 Match reg */
134 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
136 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
138 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
143 u32 addr; /* Next descriptor pointer */
148 /* Page table entries are set to 1MB, or multiples of 1MB
149 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
151 #define BD_SPACE 0x100000
152 /* BD separation space */
153 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd))
155 /* Setup the first free TX descriptor */
156 #define TX_FREE_DESC 2
158 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
159 struct zynq_gem_priv {
160 struct emac_bd *tx_bd;
161 struct emac_bd *rx_bd;
168 struct zynq_gem_regs *iobase;
169 phy_interface_t interface;
170 struct phy_device *phydev;
174 static inline int mdio_wait(struct zynq_gem_regs *regs)
178 /* Wait till MDIO interface is ready to accept a new transaction. */
180 if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
186 printf("%s: Timeout\n", __func__);
193 static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
197 struct zynq_gem_regs *regs = priv->iobase;
202 /* Construct mgtcr mask for the operation */
203 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
204 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
205 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
207 /* Write mgtcr and wait for completion */
208 writel(mgtcr, ®s->phymntnc);
213 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
214 *data = readl(®s->phymntnc);
219 static u32 phyread(struct zynq_gem_priv *priv, u32 phy_addr,
220 u32 regnum, u16 *val)
224 ret = phy_setup_op(priv, phy_addr, regnum,
225 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
228 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
229 phy_addr, regnum, *val);
234 static u32 phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
235 u32 regnum, u16 data)
237 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
240 return phy_setup_op(priv, phy_addr, regnum,
241 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
244 static int phy_detection(struct eth_device *dev)
248 struct zynq_gem_priv *priv = dev->priv;
250 if (priv->phyaddr != -1) {
251 phyread(priv, priv->phyaddr, PHY_DETECT_REG, &phyreg);
252 if ((phyreg != 0xFFFF) &&
253 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
254 /* Found a valid PHY address */
255 debug("Default phy address %d is valid\n",
259 debug("PHY address is not setup correctly %d\n",
265 debug("detecting phy address\n");
266 if (priv->phyaddr == -1) {
267 /* detect the PHY address */
268 for (i = 31; i >= 0; i--) {
269 phyread(priv, i, PHY_DETECT_REG, &phyreg);
270 if ((phyreg != 0xFFFF) &&
271 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
272 /* Found a valid PHY address */
274 debug("Found valid phy address, %d\n", i);
279 printf("PHY is not detected\n");
283 static int zynq_gem_setup_mac(struct eth_device *dev)
285 u32 i, macaddrlow, macaddrhigh;
286 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
288 /* Set the MAC bits [31:0] in BOT */
289 macaddrlow = dev->enetaddr[0];
290 macaddrlow |= dev->enetaddr[1] << 8;
291 macaddrlow |= dev->enetaddr[2] << 16;
292 macaddrlow |= dev->enetaddr[3] << 24;
294 /* Set MAC bits [47:32] in TOP */
295 macaddrhigh = dev->enetaddr[4];
296 macaddrhigh |= dev->enetaddr[5] << 8;
298 for (i = 0; i < 4; i++) {
299 writel(0, ®s->laddr[i][LADDR_LOW]);
300 writel(0, ®s->laddr[i][LADDR_HIGH]);
301 /* Do not use MATCHx register */
302 writel(0, ®s->match[i]);
305 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]);
306 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]);
311 static int zynq_phy_init(struct eth_device *dev)
314 struct zynq_gem_priv *priv = dev->priv;
315 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
316 const u32 supported = SUPPORTED_10baseT_Half |
317 SUPPORTED_10baseT_Full |
318 SUPPORTED_100baseT_Half |
319 SUPPORTED_100baseT_Full |
320 SUPPORTED_1000baseT_Half |
321 SUPPORTED_1000baseT_Full;
323 /* Enable only MDIO bus */
324 writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl);
326 ret = phy_detection(dev);
328 printf("GEM PHY init failed\n");
332 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
337 priv->phydev->supported = supported | ADVERTISED_Pause |
338 ADVERTISED_Asym_Pause;
339 priv->phydev->advertising = priv->phydev->supported;
340 phy_config(priv->phydev);
345 static int zynq_gem_init(struct eth_device *dev, bd_t *bis)
348 unsigned long clk_rate = 0;
349 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
350 struct zynq_gem_priv *priv = dev->priv;
351 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
352 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
355 /* Disable all interrupts */
356 writel(0xFFFFFFFF, ®s->idr);
358 /* Disable the receiver & transmitter */
359 writel(0, ®s->nwctrl);
360 writel(0, ®s->txsr);
361 writel(0, ®s->rxsr);
362 writel(0, ®s->phymntnc);
364 /* Clear the Hash registers for the mac address
365 * pointed by AddressPtr
367 writel(0x0, ®s->hashl);
368 /* Write bits [63:32] in TOP */
369 writel(0x0, ®s->hashh);
371 /* Clear all counters */
372 for (i = 0; i < STAT_SIZE; i++)
373 readl(®s->stat[i]);
375 /* Setup RxBD space */
376 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
378 for (i = 0; i < RX_BUF; i++) {
379 priv->rx_bd[i].status = 0xF0000000;
380 priv->rx_bd[i].addr =
381 ((ulong)(priv->rxbuffers) +
382 (i * PKTSIZE_ALIGN));
384 /* WRAP bit to last BD */
385 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
386 /* Write RxBDs to IP */
387 writel((ulong)priv->rx_bd, ®s->rxqbase);
389 /* Setup for DMA Configuration register */
390 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr);
392 /* Setup for Network Control register, MDIO, Rx and Tx enable */
393 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
395 /* Disable the second priority queue */
396 dummy_tx_bd->addr = 0;
397 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
398 ZYNQ_GEM_TXBUF_LAST_MASK|
399 ZYNQ_GEM_TXBUF_USED_MASK;
401 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
402 ZYNQ_GEM_RXBUF_NEW_MASK;
403 dummy_rx_bd->status = 0;
404 flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd +
405 sizeof(dummy_tx_bd));
406 flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd +
407 sizeof(dummy_rx_bd));
409 writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr);
410 writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr);
415 phy_startup(priv->phydev);
417 if (!priv->phydev->link) {
418 printf("%s: No link.\n", priv->phydev->dev->name);
422 switch (priv->phydev->speed) {
424 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
426 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
429 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100,
431 clk_rate = ZYNQ_GEM_FREQUENCY_100;
434 clk_rate = ZYNQ_GEM_FREQUENCY_10;
438 /* Change the rclk and clk only not using EMIO interface */
440 zynq_slcr_gem_clk_setup(dev->iobase !=
441 ZYNQ_GEM_BASEADDR0, clk_rate);
443 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
444 ZYNQ_GEM_NWCTRL_TXEN_MASK);
449 static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
450 bool set, unsigned int timeout)
453 unsigned long start = get_timer(0);
461 if ((val & mask) == mask)
464 if (get_timer(start) > timeout)
470 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
471 func, reg, mask, set);
476 static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
479 struct zynq_gem_priv *priv = dev->priv;
480 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
481 struct emac_bd *current_bd = &priv->tx_bd[1];
484 memset(priv->tx_bd, 0, sizeof(struct emac_bd));
486 priv->tx_bd->addr = (ulong)ptr;
487 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
488 ZYNQ_GEM_TXBUF_LAST_MASK;
489 /* Dummy descriptor to mark it as the last in descriptor chain */
490 current_bd->addr = 0x0;
491 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
492 ZYNQ_GEM_TXBUF_LAST_MASK|
493 ZYNQ_GEM_TXBUF_USED_MASK;
496 writel((ulong)priv->tx_bd, ®s->txqbase);
499 addr &= ~(ARCH_DMA_MINALIGN - 1);
500 size = roundup(len, ARCH_DMA_MINALIGN);
501 flush_dcache_range(addr, addr + size);
503 addr = (ulong)priv->rxbuffers;
504 addr &= ~(ARCH_DMA_MINALIGN - 1);
505 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
506 flush_dcache_range(addr, addr + size);
510 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
512 /* Read TX BD status */
513 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
514 printf("TX buffers exhausted in mid frame\n");
516 return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE,
520 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
521 static int zynq_gem_recv(struct eth_device *dev)
524 struct zynq_gem_priv *priv = dev->priv;
525 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
526 struct emac_bd *first_bd;
528 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
531 if (!(current_bd->status &
532 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
533 printf("GEM: SOF or EOF not set for last buffer received!\n");
537 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
539 u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
540 addr &= ~(ARCH_DMA_MINALIGN - 1);
542 net_process_received_packet((u8 *)(ulong)addr, frame_len);
544 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
545 priv->rx_first_buf = priv->rxbd_current;
547 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
548 current_bd->status = 0xF0000000; /* FIXME */
551 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
552 first_bd = &priv->rx_bd[priv->rx_first_buf];
553 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
554 first_bd->status = 0xF0000000;
557 if ((++priv->rxbd_current) >= RX_BUF)
558 priv->rxbd_current = 0;
564 static void zynq_gem_halt(struct eth_device *dev)
566 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
568 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
569 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
572 static int zynq_gem_miiphy_read(const char *devname, uchar addr,
573 uchar reg, ushort *val)
575 struct eth_device *dev = eth_get_dev();
576 struct zynq_gem_priv *priv = dev->priv;
579 ret = phyread(priv, addr, reg, val);
580 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
584 static int zynq_gem_miiphy_write(const char *devname, uchar addr,
585 uchar reg, ushort val)
587 struct eth_device *dev = eth_get_dev();
588 struct zynq_gem_priv *priv = dev->priv;
590 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
591 return phywrite(priv, addr, reg, val);
594 int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
595 int phy_addr, u32 emio)
598 struct eth_device *dev;
599 struct zynq_gem_priv *priv;
602 dev = calloc(1, sizeof(*dev));
606 dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
607 if (dev->priv == NULL) {
613 /* Align rxbuffers to ARCH_DMA_MINALIGN */
614 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
615 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
617 /* Align bd_space to MMU_SECTION_SHIFT */
618 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
619 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
620 BD_SPACE, DCACHE_OFF);
622 /* Initialize the bd spaces for tx and rx bd's */
623 priv->tx_bd = (struct emac_bd *)bd_space;
624 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
626 priv->phyaddr = phy_addr;
629 #ifndef CONFIG_ZYNQ_GEM_INTERFACE
630 priv->interface = PHY_INTERFACE_MODE_MII;
632 priv->interface = CONFIG_ZYNQ_GEM_INTERFACE;
635 sprintf(dev->name, "Gem.%lx", base_addr);
637 dev->iobase = base_addr;
638 priv->iobase = (struct zynq_gem_regs *)base_addr;
640 dev->init = zynq_gem_init;
641 dev->halt = zynq_gem_halt;
642 dev->send = zynq_gem_send;
643 dev->recv = zynq_gem_recv;
644 dev->write_hwaddr = zynq_gem_setup_mac;
648 miiphy_register(dev->name, zynq_gem_miiphy_read, zynq_gem_miiphy_write);
649 priv->bus = miiphy_get_dev_by_name(dev->name);
651 ret = zynq_phy_init(dev);