2 * (C) Copyright 2011 Michal Simek
4 * Michal SIMEK <monstr@monstr.eu>
6 * Based on Xilinx gmac driver:
7 * (C) Copyright 2011 Xilinx
9 * SPDX-License-Identifier: GPL-2.0+
23 #include <asm/system.h>
24 #include <asm/arch/hardware.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm-generic/errno.h>
28 #if !defined(CONFIG_PHYLIB)
29 # error XILINX_GEM_ETHERNET requires PHYLIB
32 /* Bit/mask specification */
33 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
34 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
35 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
36 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
37 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
39 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
40 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
41 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
43 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
44 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
45 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
47 /* Wrap bit, last descriptor */
48 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
49 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
50 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
52 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
53 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
54 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
55 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
57 #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */
58 #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
59 #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
60 #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
61 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */
64 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
66 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
69 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
70 ZYNQ_GEM_NWCFG_FDEN | \
71 ZYNQ_GEM_NWCFG_FSREM | \
72 ZYNQ_GEM_NWCFG_MDCCLKDIV)
74 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
76 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
77 /* Use full configured addressable space (8 Kb) */
78 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
79 /* Use full configured addressable space (4 Kb) */
80 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
81 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
82 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000
84 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
85 ZYNQ_GEM_DMACR_RXSIZE | \
86 ZYNQ_GEM_DMACR_TXSIZE | \
89 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
91 /* Use MII register 1 (MII status register) to detect PHY */
92 #define PHY_DETECT_REG 1
94 /* Mask used to verify certain PHY features (or register contents)
95 * in the register above:
96 * 0x1000: 10Mbps full duplex support
97 * 0x0800: 10Mbps half duplex support
98 * 0x0008: Auto-negotiation support
100 #define PHY_DETECT_MASK 0x1808
102 /* TX BD status masks */
103 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
104 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
105 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
107 /* Clock frequencies for different speeds */
108 #define ZYNQ_GEM_FREQUENCY_10 2500000UL
109 #define ZYNQ_GEM_FREQUENCY_100 25000000UL
110 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
112 /* Device registers */
113 struct zynq_gem_regs {
114 u32 nwctrl; /* 0x0 - Network Control reg */
115 u32 nwcfg; /* 0x4 - Network Config reg */
116 u32 nwsr; /* 0x8 - Network Status reg */
118 u32 dmacr; /* 0x10 - DMA Control reg */
119 u32 txsr; /* 0x14 - TX Status reg */
120 u32 rxqbase; /* 0x18 - RX Q Base address reg */
121 u32 txqbase; /* 0x1c - TX Q Base address reg */
122 u32 rxsr; /* 0x20 - RX Status reg */
124 u32 idr; /* 0x2c - Interrupt Disable reg */
126 u32 phymntnc; /* 0x34 - Phy Maintaince reg */
128 u32 hashl; /* 0x80 - Hash Low address reg */
129 u32 hashh; /* 0x84 - Hash High address reg */
132 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
133 u32 match[4]; /* 0xa8 - Type ID1 Match reg */
136 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
138 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
140 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
145 u32 addr; /* Next descriptor pointer */
150 /* Page table entries are set to 1MB, or multiples of 1MB
151 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
153 #define BD_SPACE 0x100000
154 /* BD separation space */
155 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd))
157 /* Setup the first free TX descriptor */
158 #define TX_FREE_DESC 2
160 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
161 struct zynq_gem_priv {
162 struct emac_bd *tx_bd;
163 struct emac_bd *rx_bd;
170 phy_interface_t interface;
171 struct phy_device *phydev;
175 static inline int mdio_wait(struct zynq_gem_regs *regs)
179 /* Wait till MDIO interface is ready to accept a new transaction. */
181 if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
187 printf("%s: Timeout\n", __func__);
194 static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
198 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
203 /* Construct mgtcr mask for the operation */
204 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
205 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
206 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
208 /* Write mgtcr and wait for completion */
209 writel(mgtcr, ®s->phymntnc);
214 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
215 *data = readl(®s->phymntnc);
220 static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val)
224 ret = phy_setup_op(dev, phy_addr, regnum,
225 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
228 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
229 phy_addr, regnum, *val);
234 static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data)
236 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
239 return phy_setup_op(dev, phy_addr, regnum,
240 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
243 static int phy_detection(struct eth_device *dev)
247 struct zynq_gem_priv *priv = dev->priv;
249 if (priv->phyaddr != -1) {
250 phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg);
251 if ((phyreg != 0xFFFF) &&
252 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
253 /* Found a valid PHY address */
254 debug("Default phy address %d is valid\n",
258 debug("PHY address is not setup correctly %d\n",
264 debug("detecting phy address\n");
265 if (priv->phyaddr == -1) {
266 /* detect the PHY address */
267 for (i = 31; i >= 0; i--) {
268 phyread(dev, i, PHY_DETECT_REG, &phyreg);
269 if ((phyreg != 0xFFFF) &&
270 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
271 /* Found a valid PHY address */
273 debug("Found valid phy address, %d\n", i);
278 printf("PHY is not detected\n");
282 static int zynq_gem_setup_mac(struct eth_device *dev)
284 u32 i, macaddrlow, macaddrhigh;
285 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
287 /* Set the MAC bits [31:0] in BOT */
288 macaddrlow = dev->enetaddr[0];
289 macaddrlow |= dev->enetaddr[1] << 8;
290 macaddrlow |= dev->enetaddr[2] << 16;
291 macaddrlow |= dev->enetaddr[3] << 24;
293 /* Set MAC bits [47:32] in TOP */
294 macaddrhigh = dev->enetaddr[4];
295 macaddrhigh |= dev->enetaddr[5] << 8;
297 for (i = 0; i < 4; i++) {
298 writel(0, ®s->laddr[i][LADDR_LOW]);
299 writel(0, ®s->laddr[i][LADDR_HIGH]);
300 /* Do not use MATCHx register */
301 writel(0, ®s->match[i]);
304 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]);
305 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]);
310 static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
314 unsigned long clk_rate = 0;
315 struct phy_device *phydev;
316 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
317 struct zynq_gem_priv *priv = dev->priv;
318 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
319 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
320 const u32 supported = SUPPORTED_10baseT_Half |
321 SUPPORTED_10baseT_Full |
322 SUPPORTED_100baseT_Half |
323 SUPPORTED_100baseT_Full |
324 SUPPORTED_1000baseT_Half |
325 SUPPORTED_1000baseT_Full;
328 /* Disable all interrupts */
329 writel(0xFFFFFFFF, ®s->idr);
331 /* Disable the receiver & transmitter */
332 writel(0, ®s->nwctrl);
333 writel(0, ®s->txsr);
334 writel(0, ®s->rxsr);
335 writel(0, ®s->phymntnc);
337 /* Clear the Hash registers for the mac address
338 * pointed by AddressPtr
340 writel(0x0, ®s->hashl);
341 /* Write bits [63:32] in TOP */
342 writel(0x0, ®s->hashh);
344 /* Clear all counters */
345 for (i = 0; i < STAT_SIZE; i++)
346 readl(®s->stat[i]);
348 /* Setup RxBD space */
349 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
351 for (i = 0; i < RX_BUF; i++) {
352 priv->rx_bd[i].status = 0xF0000000;
353 priv->rx_bd[i].addr =
354 ((ulong)(priv->rxbuffers) +
355 (i * PKTSIZE_ALIGN));
357 /* WRAP bit to last BD */
358 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
359 /* Write RxBDs to IP */
360 writel((ulong)priv->rx_bd, ®s->rxqbase);
362 /* Setup for DMA Configuration register */
363 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr);
365 /* Setup for Network Control register, MDIO, Rx and Tx enable */
366 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
368 /* Disable the second priority queue */
369 dummy_tx_bd->addr = 0;
370 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
371 ZYNQ_GEM_TXBUF_LAST_MASK|
372 ZYNQ_GEM_TXBUF_USED_MASK;
374 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
375 ZYNQ_GEM_RXBUF_NEW_MASK;
376 dummy_rx_bd->status = 0;
377 flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd +
378 sizeof(dummy_tx_bd));
379 flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd +
380 sizeof(dummy_rx_bd));
382 writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr);
383 writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr);
388 ret = phy_detection(dev);
390 printf("GEM PHY init failed\n");
394 /* interface - look at tsec */
395 phydev = phy_connect(priv->bus, priv->phyaddr, dev,
398 phydev->supported = supported | ADVERTISED_Pause |
399 ADVERTISED_Asym_Pause;
400 phydev->advertising = phydev->supported;
401 priv->phydev = phydev;
406 printf("%s: No link.\n", phydev->dev->name);
410 switch (phydev->speed) {
412 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
414 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
417 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100,
419 clk_rate = ZYNQ_GEM_FREQUENCY_100;
422 clk_rate = ZYNQ_GEM_FREQUENCY_10;
426 /* Change the rclk and clk only not using EMIO interface */
428 zynq_slcr_gem_clk_setup(dev->iobase !=
429 ZYNQ_GEM_BASEADDR0, clk_rate);
431 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
432 ZYNQ_GEM_NWCTRL_TXEN_MASK);
437 static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
438 bool set, unsigned int timeout)
441 unsigned long start = get_timer(0);
449 if ((val & mask) == mask)
452 if (get_timer(start) > timeout)
458 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
459 func, reg, mask, set);
464 static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
467 struct zynq_gem_priv *priv = dev->priv;
468 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
469 struct emac_bd *current_bd = &priv->tx_bd[1];
472 memset(priv->tx_bd, 0, sizeof(struct emac_bd));
474 priv->tx_bd->addr = (ulong)ptr;
475 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
476 ZYNQ_GEM_TXBUF_LAST_MASK;
477 /* Dummy descriptor to mark it as the last in descriptor chain */
478 current_bd->addr = 0x0;
479 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
480 ZYNQ_GEM_TXBUF_LAST_MASK|
481 ZYNQ_GEM_TXBUF_USED_MASK;
484 writel((ulong)priv->tx_bd, ®s->txqbase);
487 addr &= ~(ARCH_DMA_MINALIGN - 1);
488 size = roundup(len, ARCH_DMA_MINALIGN);
489 flush_dcache_range(addr, addr + size);
491 addr = (ulong)priv->rxbuffers;
492 addr &= ~(ARCH_DMA_MINALIGN - 1);
493 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
494 flush_dcache_range(addr, addr + size);
498 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
500 /* Read TX BD status */
501 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
502 printf("TX buffers exhausted in mid frame\n");
504 return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE,
508 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
509 static int zynq_gem_recv(struct eth_device *dev)
512 struct zynq_gem_priv *priv = dev->priv;
513 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
514 struct emac_bd *first_bd;
516 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
519 if (!(current_bd->status &
520 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
521 printf("GEM: SOF or EOF not set for last buffer received!\n");
525 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
527 u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
528 addr &= ~(ARCH_DMA_MINALIGN - 1);
530 net_process_received_packet((u8 *)(ulong)addr, frame_len);
532 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
533 priv->rx_first_buf = priv->rxbd_current;
535 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
536 current_bd->status = 0xF0000000; /* FIXME */
539 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
540 first_bd = &priv->rx_bd[priv->rx_first_buf];
541 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
542 first_bd->status = 0xF0000000;
545 if ((++priv->rxbd_current) >= RX_BUF)
546 priv->rxbd_current = 0;
552 static void zynq_gem_halt(struct eth_device *dev)
554 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
556 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
557 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
560 static int zynq_gem_miiphyread(const char *devname, uchar addr,
561 uchar reg, ushort *val)
563 struct eth_device *dev = eth_get_dev();
566 ret = phyread(dev, addr, reg, val);
567 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
571 static int zynq_gem_miiphy_write(const char *devname, uchar addr,
572 uchar reg, ushort val)
574 struct eth_device *dev = eth_get_dev();
576 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
577 return phywrite(dev, addr, reg, val);
580 int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
581 int phy_addr, u32 emio)
583 struct eth_device *dev;
584 struct zynq_gem_priv *priv;
587 dev = calloc(1, sizeof(*dev));
591 dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
592 if (dev->priv == NULL) {
598 /* Align rxbuffers to ARCH_DMA_MINALIGN */
599 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
600 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
602 /* Align bd_space to MMU_SECTION_SHIFT */
603 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
604 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
605 BD_SPACE, DCACHE_OFF);
607 /* Initialize the bd spaces for tx and rx bd's */
608 priv->tx_bd = (struct emac_bd *)bd_space;
609 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
611 priv->phyaddr = phy_addr;
614 #ifndef CONFIG_ZYNQ_GEM_INTERFACE
615 priv->interface = PHY_INTERFACE_MODE_MII;
617 priv->interface = CONFIG_ZYNQ_GEM_INTERFACE;
620 sprintf(dev->name, "Gem.%lx", base_addr);
622 dev->iobase = base_addr;
624 dev->init = zynq_gem_init;
625 dev->halt = zynq_gem_halt;
626 dev->send = zynq_gem_send;
627 dev->recv = zynq_gem_recv;
628 dev->write_hwaddr = zynq_gem_setup_mac;
632 miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
633 priv->bus = miiphy_get_dev_by_name(dev->name);
638 #if CONFIG_IS_ENABLED(OF_CONTROL)
639 int zynq_gem_of_init(const void *blob)
645 debug("ZYNQ GEM: Initialization\n");
648 offset = fdt_node_offset_by_compatible(blob, offset,
649 "xlnx,ps7-ethernet-1.00.a");
651 reg = fdtdec_get_addr(blob, offset, "reg");
652 if (reg != FDT_ADDR_T_NONE) {
653 offset = fdtdec_lookup_phandle(blob, offset,
656 phy_reg = fdtdec_get_addr(blob, offset,
661 debug("ZYNQ GEM: addr %x, phyaddr %x\n",
664 ret |= zynq_gem_initialize(NULL, reg,
668 debug("ZYNQ GEM: Can't get base address\n");
672 } while (offset != -1);