2 * (C) Copyright 2011 Michal Simek
4 * Michal SIMEK <monstr@monstr.eu>
6 * Based on Xilinx gmac driver:
7 * (C) Copyright 2011 Xilinx
9 * SPDX-License-Identifier: GPL-2.0+
23 #include <asm/system.h>
24 #include <asm/arch/hardware.h>
25 #include <asm/arch/sys_proto.h>
26 #include <asm-generic/errno.h>
28 #if !defined(CONFIG_PHYLIB)
29 # error XILINX_GEM_ETHERNET requires PHYLIB
32 /* Bit/mask specification */
33 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
34 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
35 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
36 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
37 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
39 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
40 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
41 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
43 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
44 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
45 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
47 /* Wrap bit, last descriptor */
48 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
49 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
50 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
52 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
53 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
54 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
55 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
57 #define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */
58 #define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */
59 #define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */
60 #define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */
61 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */
62 #define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */
65 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
67 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
70 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
71 ZYNQ_GEM_NWCFG_FDEN | \
72 ZYNQ_GEM_NWCFG_FSREM | \
73 ZYNQ_GEM_NWCFG_MDCCLKDIV)
75 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
77 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
78 /* Use full configured addressable space (8 Kb) */
79 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
80 /* Use full configured addressable space (4 Kb) */
81 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
82 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
83 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000
85 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
86 ZYNQ_GEM_DMACR_RXSIZE | \
87 ZYNQ_GEM_DMACR_TXSIZE | \
90 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
92 /* Use MII register 1 (MII status register) to detect PHY */
93 #define PHY_DETECT_REG 1
95 /* Mask used to verify certain PHY features (or register contents)
96 * in the register above:
97 * 0x1000: 10Mbps full duplex support
98 * 0x0800: 10Mbps half duplex support
99 * 0x0008: Auto-negotiation support
101 #define PHY_DETECT_MASK 0x1808
103 /* TX BD status masks */
104 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
105 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
106 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
108 /* Clock frequencies for different speeds */
109 #define ZYNQ_GEM_FREQUENCY_10 2500000UL
110 #define ZYNQ_GEM_FREQUENCY_100 25000000UL
111 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
113 /* Device registers */
114 struct zynq_gem_regs {
115 u32 nwctrl; /* 0x0 - Network Control reg */
116 u32 nwcfg; /* 0x4 - Network Config reg */
117 u32 nwsr; /* 0x8 - Network Status reg */
119 u32 dmacr; /* 0x10 - DMA Control reg */
120 u32 txsr; /* 0x14 - TX Status reg */
121 u32 rxqbase; /* 0x18 - RX Q Base address reg */
122 u32 txqbase; /* 0x1c - TX Q Base address reg */
123 u32 rxsr; /* 0x20 - RX Status reg */
125 u32 idr; /* 0x2c - Interrupt Disable reg */
127 u32 phymntnc; /* 0x34 - Phy Maintaince reg */
129 u32 hashl; /* 0x80 - Hash Low address reg */
130 u32 hashh; /* 0x84 - Hash High address reg */
133 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
134 u32 match[4]; /* 0xa8 - Type ID1 Match reg */
137 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
139 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
141 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
146 u32 addr; /* Next descriptor pointer */
151 /* Page table entries are set to 1MB, or multiples of 1MB
152 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
154 #define BD_SPACE 0x100000
155 /* BD separation space */
156 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd))
158 /* Setup the first free TX descriptor */
159 #define TX_FREE_DESC 2
161 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
162 struct zynq_gem_priv {
163 struct emac_bd *tx_bd;
164 struct emac_bd *rx_bd;
171 phy_interface_t interface;
172 struct phy_device *phydev;
176 static inline int mdio_wait(struct eth_device *dev)
178 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
181 /* Wait till MDIO interface is ready to accept a new transaction. */
183 if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK)
189 printf("%s: Timeout\n", __func__);
196 static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
200 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
205 /* Construct mgtcr mask for the operation */
206 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
207 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
208 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
210 /* Write mgtcr and wait for completion */
211 writel(mgtcr, ®s->phymntnc);
216 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
217 *data = readl(®s->phymntnc);
222 static u32 phyread(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 *val)
226 ret = phy_setup_op(dev, phy_addr, regnum,
227 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
230 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
231 phy_addr, regnum, *val);
236 static u32 phywrite(struct eth_device *dev, u32 phy_addr, u32 regnum, u16 data)
238 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
241 return phy_setup_op(dev, phy_addr, regnum,
242 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
245 static void phy_detection(struct eth_device *dev)
249 struct zynq_gem_priv *priv = dev->priv;
251 if (priv->phyaddr != -1) {
252 phyread(dev, priv->phyaddr, PHY_DETECT_REG, &phyreg);
253 if ((phyreg != 0xFFFF) &&
254 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
255 /* Found a valid PHY address */
256 debug("Default phy address %d is valid\n",
260 debug("PHY address is not setup correctly %d\n",
266 debug("detecting phy address\n");
267 if (priv->phyaddr == -1) {
268 /* detect the PHY address */
269 for (i = 31; i >= 0; i--) {
270 phyread(dev, i, PHY_DETECT_REG, &phyreg);
271 if ((phyreg != 0xFFFF) &&
272 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
273 /* Found a valid PHY address */
275 debug("Found valid phy address, %d\n", i);
280 printf("PHY is not detected\n");
283 static int zynq_gem_setup_mac(struct eth_device *dev)
285 u32 i, macaddrlow, macaddrhigh;
286 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
288 /* Set the MAC bits [31:0] in BOT */
289 macaddrlow = dev->enetaddr[0];
290 macaddrlow |= dev->enetaddr[1] << 8;
291 macaddrlow |= dev->enetaddr[2] << 16;
292 macaddrlow |= dev->enetaddr[3] << 24;
294 /* Set MAC bits [47:32] in TOP */
295 macaddrhigh = dev->enetaddr[4];
296 macaddrhigh |= dev->enetaddr[5] << 8;
298 for (i = 0; i < 4; i++) {
299 writel(0, ®s->laddr[i][LADDR_LOW]);
300 writel(0, ®s->laddr[i][LADDR_HIGH]);
301 /* Do not use MATCHx register */
302 writel(0, ®s->match[i]);
305 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]);
306 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]);
311 static int zynq_gem_init(struct eth_device *dev, bd_t * bis)
314 unsigned long clk_rate = 0;
315 struct phy_device *phydev;
316 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
317 struct zynq_gem_priv *priv = dev->priv;
318 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
319 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
320 const u32 supported = SUPPORTED_10baseT_Half |
321 SUPPORTED_10baseT_Full |
322 SUPPORTED_100baseT_Half |
323 SUPPORTED_100baseT_Full |
324 SUPPORTED_1000baseT_Half |
325 SUPPORTED_1000baseT_Full;
328 /* Disable all interrupts */
329 writel(0xFFFFFFFF, ®s->idr);
331 /* Disable the receiver & transmitter */
332 writel(0, ®s->nwctrl);
333 writel(0, ®s->txsr);
334 writel(0, ®s->rxsr);
335 writel(0, ®s->phymntnc);
337 /* Clear the Hash registers for the mac address
338 * pointed by AddressPtr
340 writel(0x0, ®s->hashl);
341 /* Write bits [63:32] in TOP */
342 writel(0x0, ®s->hashh);
344 /* Clear all counters */
345 for (i = 0; i < STAT_SIZE; i++)
346 readl(®s->stat[i]);
348 /* Setup RxBD space */
349 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
351 for (i = 0; i < RX_BUF; i++) {
352 priv->rx_bd[i].status = 0xF0000000;
353 priv->rx_bd[i].addr =
354 ((ulong)(priv->rxbuffers) +
355 (i * PKTSIZE_ALIGN));
357 /* WRAP bit to last BD */
358 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
359 /* Write RxBDs to IP */
360 writel((ulong)priv->rx_bd, ®s->rxqbase);
362 /* Setup for DMA Configuration register */
363 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr);
365 /* Setup for Network Control register, MDIO, Rx and Tx enable */
366 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
368 /* Disable the second priority queue */
369 dummy_tx_bd->addr = 0;
370 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
371 ZYNQ_GEM_TXBUF_LAST_MASK|
372 ZYNQ_GEM_TXBUF_USED_MASK;
374 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
375 ZYNQ_GEM_RXBUF_NEW_MASK;
376 dummy_rx_bd->status = 0;
377 flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd +
378 sizeof(dummy_tx_bd));
379 flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd +
380 sizeof(dummy_rx_bd));
382 writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr);
383 writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr);
390 /* interface - look at tsec */
391 phydev = phy_connect(priv->bus, priv->phyaddr, dev,
394 phydev->supported = supported | ADVERTISED_Pause |
395 ADVERTISED_Asym_Pause;
396 phydev->advertising = phydev->supported;
397 priv->phydev = phydev;
402 printf("%s: No link.\n", phydev->dev->name);
406 switch (phydev->speed) {
408 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000,
410 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
413 writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100,
415 clk_rate = ZYNQ_GEM_FREQUENCY_100;
418 clk_rate = ZYNQ_GEM_FREQUENCY_10;
422 /* Change the rclk and clk only not using EMIO interface */
424 zynq_slcr_gem_clk_setup(dev->iobase !=
425 ZYNQ_GEM_BASEADDR0, clk_rate);
427 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
428 ZYNQ_GEM_NWCTRL_TXEN_MASK);
433 static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
434 bool set, unsigned int timeout)
437 unsigned long start = get_timer(0);
445 if ((val & mask) == mask)
448 if (get_timer(start) > timeout)
454 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
455 func, reg, mask, set);
460 static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
463 struct zynq_gem_priv *priv = dev->priv;
464 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
465 struct emac_bd *current_bd = &priv->tx_bd[1];
468 memset(priv->tx_bd, 0, sizeof(struct emac_bd));
470 priv->tx_bd->addr = (ulong)ptr;
471 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
472 ZYNQ_GEM_TXBUF_LAST_MASK;
473 /* Dummy descriptor to mark it as the last in descriptor chain */
474 current_bd->addr = 0x0;
475 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
476 ZYNQ_GEM_TXBUF_LAST_MASK|
477 ZYNQ_GEM_TXBUF_USED_MASK;
480 writel((ulong)priv->tx_bd, ®s->txqbase);
483 addr &= ~(ARCH_DMA_MINALIGN - 1);
484 size = roundup(len, ARCH_DMA_MINALIGN);
485 flush_dcache_range(addr, addr + size);
487 addr = (ulong)priv->rxbuffers;
488 addr &= ~(ARCH_DMA_MINALIGN - 1);
489 size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
490 flush_dcache_range(addr, addr + size);
494 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
496 /* Read TX BD status */
497 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
498 printf("TX buffers exhausted in mid frame\n");
500 return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE,
504 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
505 static int zynq_gem_recv(struct eth_device *dev)
508 struct zynq_gem_priv *priv = dev->priv;
509 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
510 struct emac_bd *first_bd;
512 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
515 if (!(current_bd->status &
516 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
517 printf("GEM: SOF or EOF not set for last buffer received!\n");
521 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
523 u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
524 addr &= ~(ARCH_DMA_MINALIGN - 1);
526 net_process_received_packet((u8 *)(ulong)addr, frame_len);
528 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK)
529 priv->rx_first_buf = priv->rxbd_current;
531 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
532 current_bd->status = 0xF0000000; /* FIXME */
535 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
536 first_bd = &priv->rx_bd[priv->rx_first_buf];
537 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
538 first_bd->status = 0xF0000000;
541 if ((++priv->rxbd_current) >= RX_BUF)
542 priv->rxbd_current = 0;
548 static void zynq_gem_halt(struct eth_device *dev)
550 struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
552 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
553 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
556 static int zynq_gem_miiphyread(const char *devname, uchar addr,
557 uchar reg, ushort *val)
559 struct eth_device *dev = eth_get_dev();
562 ret = phyread(dev, addr, reg, val);
563 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, *val);
567 static int zynq_gem_miiphy_write(const char *devname, uchar addr,
568 uchar reg, ushort val)
570 struct eth_device *dev = eth_get_dev();
572 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val);
573 return phywrite(dev, addr, reg, val);
576 int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
577 int phy_addr, u32 emio)
579 struct eth_device *dev;
580 struct zynq_gem_priv *priv;
583 dev = calloc(1, sizeof(*dev));
587 dev->priv = calloc(1, sizeof(struct zynq_gem_priv));
588 if (dev->priv == NULL) {
594 /* Align rxbuffers to ARCH_DMA_MINALIGN */
595 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
596 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
598 /* Align bd_space to MMU_SECTION_SHIFT */
599 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
600 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
601 BD_SPACE, DCACHE_OFF);
603 /* Initialize the bd spaces for tx and rx bd's */
604 priv->tx_bd = (struct emac_bd *)bd_space;
605 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
607 priv->phyaddr = phy_addr;
610 #ifndef CONFIG_ZYNQ_GEM_INTERFACE
611 priv->interface = PHY_INTERFACE_MODE_MII;
613 priv->interface = CONFIG_ZYNQ_GEM_INTERFACE;
616 sprintf(dev->name, "Gem.%lx", base_addr);
618 dev->iobase = base_addr;
620 dev->init = zynq_gem_init;
621 dev->halt = zynq_gem_halt;
622 dev->send = zynq_gem_send;
623 dev->recv = zynq_gem_recv;
624 dev->write_hwaddr = zynq_gem_setup_mac;
628 miiphy_register(dev->name, zynq_gem_miiphyread, zynq_gem_miiphy_write);
629 priv->bus = miiphy_get_dev_by_name(dev->name);
634 #if CONFIG_IS_ENABLED(OF_CONTROL)
635 int zynq_gem_of_init(const void *blob)
641 debug("ZYNQ GEM: Initialization\n");
644 offset = fdt_node_offset_by_compatible(blob, offset,
645 "xlnx,ps7-ethernet-1.00.a");
647 reg = fdtdec_get_addr(blob, offset, "reg");
648 if (reg != FDT_ADDR_T_NONE) {
649 offset = fdtdec_lookup_phandle(blob, offset,
652 phy_reg = fdtdec_get_addr(blob, offset,
657 debug("ZYNQ GEM: addr %x, phyaddr %x\n",
660 ret |= zynq_gem_initialize(NULL, reg,
664 debug("ZYNQ GEM: Can't get base address\n");
668 } while (offset != -1);