1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2011 Michal Simek
5 * Michal SIMEK <monstr@monstr.eu>
7 * Based on Xilinx gmac driver:
8 * (C) Copyright 2011 Xilinx
15 #include <generic-phy.h>
22 #include <asm/cache.h>
29 #include <asm/system.h>
30 #include <asm/arch/hardware.h>
31 #include <asm/arch/sys_proto.h>
32 #include <dm/device_compat.h>
33 #include <linux/bitops.h>
34 #include <linux/err.h>
35 #include <linux/errno.h>
37 #include <zynqmp_firmware.h>
39 /* Bit/mask specification */
40 #define ZYNQ_GEM_PHYMNTNC_OP_MASK 0x40020000 /* operation mask bits */
41 #define ZYNQ_GEM_PHYMNTNC_OP_R_MASK 0x20000000 /* read operation */
42 #define ZYNQ_GEM_PHYMNTNC_OP_W_MASK 0x10000000 /* write operation */
43 #define ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK 23 /* Shift bits for PHYAD */
44 #define ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK 18 /* Shift bits for PHREG */
46 #define ZYNQ_GEM_RXBUF_EOF_MASK 0x00008000 /* End of frame. */
47 #define ZYNQ_GEM_RXBUF_SOF_MASK 0x00004000 /* Start of frame. */
48 #define ZYNQ_GEM_RXBUF_LEN_MASK 0x00003FFF /* Mask for length field */
50 #define ZYNQ_GEM_RXBUF_WRAP_MASK 0x00000002 /* Wrap bit, last BD */
51 #define ZYNQ_GEM_RXBUF_NEW_MASK 0x00000001 /* Used bit.. */
52 #define ZYNQ_GEM_RXBUF_ADD_MASK 0xFFFFFFFC /* Mask for address */
54 /* Wrap bit, last descriptor */
55 #define ZYNQ_GEM_TXBUF_WRAP_MASK 0x40000000
56 #define ZYNQ_GEM_TXBUF_LAST_MASK 0x00008000 /* Last buffer */
57 #define ZYNQ_GEM_TXBUF_USED_MASK 0x80000000 /* Used by Hw */
59 #define ZYNQ_GEM_NWCTRL_TXEN_MASK 0x00000008 /* Enable transmit */
60 #define ZYNQ_GEM_NWCTRL_RXEN_MASK 0x00000004 /* Enable receive */
61 #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */
62 #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */
64 #define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */
65 #define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */
66 #define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */
67 #define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */
68 #define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */
69 #define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */
71 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */
73 #define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */
77 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
79 # define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
82 #define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
83 ZYNQ_GEM_NWCFG_FDEN | \
84 ZYNQ_GEM_NWCFG_FSREM | \
85 ZYNQ_GEM_NWCFG_MDCCLKDIV)
87 #define ZYNQ_GEM_NWSR_MDIOIDLE_MASK 0x00000004 /* PHY management idle */
89 #define ZYNQ_GEM_DMACR_BLENGTH 0x00000004 /* INCR4 AHB bursts */
90 /* Use full configured addressable space (8 Kb) */
91 #define ZYNQ_GEM_DMACR_RXSIZE 0x00000300
92 /* Use full configured addressable space (4 Kb) */
93 #define ZYNQ_GEM_DMACR_TXSIZE 0x00000400
94 /* Set with binary 00011000 to use 1536 byte(1*max length frame/buffer) */
95 #define ZYNQ_GEM_DMACR_RXBUF 0x00180000
97 #if defined(CONFIG_PHYS_64BIT)
98 # define ZYNQ_GEM_DMA_BUS_WIDTH BIT(30) /* 64 bit bus */
100 # define ZYNQ_GEM_DMA_BUS_WIDTH (0 << 30) /* 32 bit bus */
103 #define ZYNQ_GEM_DMACR_INIT (ZYNQ_GEM_DMACR_BLENGTH | \
104 ZYNQ_GEM_DMACR_RXSIZE | \
105 ZYNQ_GEM_DMACR_TXSIZE | \
106 ZYNQ_GEM_DMACR_RXBUF | \
107 ZYNQ_GEM_DMA_BUS_WIDTH)
109 #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */
111 #define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000
113 #define ZYNQ_GEM_DCFG_DBG6_DMA_64B BIT(23)
115 #define MDIO_IDLE_TIMEOUT_MS 100
117 /* Use MII register 1 (MII status register) to detect PHY */
118 #define PHY_DETECT_REG 1
120 /* Mask used to verify certain PHY features (or register contents)
121 * in the register above:
122 * 0x1000: 10Mbps full duplex support
123 * 0x0800: 10Mbps half duplex support
124 * 0x0008: Auto-negotiation support
126 #define PHY_DETECT_MASK 0x1808
128 /* TX BD status masks */
129 #define ZYNQ_GEM_TXBUF_FRMLEN_MASK 0x000007ff
130 #define ZYNQ_GEM_TXBUF_EXHAUSTED 0x08000000
131 #define ZYNQ_GEM_TXBUF_UNDERRUN 0x10000000
133 /* Clock frequencies for different speeds */
134 #define ZYNQ_GEM_FREQUENCY_10 2500000UL
135 #define ZYNQ_GEM_FREQUENCY_100 25000000UL
136 #define ZYNQ_GEM_FREQUENCY_1000 125000000UL
138 #define RXCLK_EN BIT(0)
140 /* Device registers */
141 struct zynq_gem_regs {
142 u32 nwctrl; /* 0x0 - Network Control reg */
143 u32 nwcfg; /* 0x4 - Network Config reg */
144 u32 nwsr; /* 0x8 - Network Status reg */
146 u32 dmacr; /* 0x10 - DMA Control reg */
147 u32 txsr; /* 0x14 - TX Status reg */
148 u32 rxqbase; /* 0x18 - RX Q Base address reg */
149 u32 txqbase; /* 0x1c - TX Q Base address reg */
150 u32 rxsr; /* 0x20 - RX Status reg */
152 u32 idr; /* 0x2c - Interrupt Disable reg */
154 u32 phymntnc; /* 0x34 - Phy Maintaince reg */
156 u32 hashl; /* 0x80 - Hash Low address reg */
157 u32 hashh; /* 0x84 - Hash High address reg */
160 u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
161 u32 match[4]; /* 0xa8 - Type ID1 Match reg */
164 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
168 u32 dcfg6; /* 0x294 Design config reg6 */
170 u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */
172 u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */
174 u32 upper_txqbase; /* 0x4C8 - Upper tx_q base addr */
176 u32 upper_rxqbase; /* 0x4D4 - Upper rx_q base addr */
181 u32 addr; /* Next descriptor pointer */
183 #if defined(CONFIG_PHYS_64BIT)
189 /* Reduce amount of BUFs if you have limited amount of memory */
191 /* Page table entries are set to 1MB, or multiples of 1MB
192 * (not < 1MB). driver uses less bd's so use 1MB bdspace.
194 #define BD_SPACE 0x100000
195 /* BD separation space */
196 #define BD_SEPRN_SPACE (RX_BUF * sizeof(struct emac_bd))
198 /* Setup the first free TX descriptor */
199 #define TX_FREE_DESC 2
201 /* Initialized, rxbd_current, rx_first_buf must be 0 after init */
202 struct zynq_gem_priv {
203 struct emac_bd *tx_bd;
204 struct emac_bd *rx_bd;
210 struct zynq_gem_regs *iobase;
211 struct zynq_gem_regs *mdiobase;
212 phy_interface_t interface;
213 struct phy_device *phydev;
222 struct reset_ctl_bulk resets;
225 static int phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum,
229 struct zynq_gem_regs *regs = priv->mdiobase;
232 err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
233 true, MDIO_IDLE_TIMEOUT_MS, false);
237 /* Construct mgtcr mask for the operation */
238 mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op |
239 (phy_addr << ZYNQ_GEM_PHYMNTNC_PHYAD_SHIFT_MASK) |
240 (regnum << ZYNQ_GEM_PHYMNTNC_PHREG_SHIFT_MASK) | *data;
242 /* Write mgtcr and wait for completion */
243 writel(mgtcr, ®s->phymntnc);
245 err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK,
246 true, MDIO_IDLE_TIMEOUT_MS, false);
250 if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)
251 *data = readl(®s->phymntnc);
256 static int phyread(struct zynq_gem_priv *priv, u32 phy_addr,
257 u32 regnum, u16 *val)
261 ret = phy_setup_op(priv, phy_addr, regnum,
262 ZYNQ_GEM_PHYMNTNC_OP_R_MASK, val);
265 debug("%s: phy_addr %d, regnum 0x%x, val 0x%x\n", __func__,
266 phy_addr, regnum, *val);
271 static int phywrite(struct zynq_gem_priv *priv, u32 phy_addr,
272 u32 regnum, u16 data)
274 debug("%s: phy_addr %d, regnum 0x%x, data 0x%x\n", __func__, phy_addr,
277 return phy_setup_op(priv, phy_addr, regnum,
278 ZYNQ_GEM_PHYMNTNC_OP_W_MASK, &data);
281 static int zynq_gem_setup_mac(struct udevice *dev)
283 u32 i, macaddrlow, macaddrhigh;
284 struct eth_pdata *pdata = dev_get_plat(dev);
285 struct zynq_gem_priv *priv = dev_get_priv(dev);
286 struct zynq_gem_regs *regs = priv->iobase;
288 /* Set the MAC bits [31:0] in BOT */
289 macaddrlow = pdata->enetaddr[0];
290 macaddrlow |= pdata->enetaddr[1] << 8;
291 macaddrlow |= pdata->enetaddr[2] << 16;
292 macaddrlow |= pdata->enetaddr[3] << 24;
294 /* Set MAC bits [47:32] in TOP */
295 macaddrhigh = pdata->enetaddr[4];
296 macaddrhigh |= pdata->enetaddr[5] << 8;
298 for (i = 0; i < 4; i++) {
299 writel(0, ®s->laddr[i][LADDR_LOW]);
300 writel(0, ®s->laddr[i][LADDR_HIGH]);
301 /* Do not use MATCHx register */
302 writel(0, ®s->match[i]);
305 writel(macaddrlow, ®s->laddr[0][LADDR_LOW]);
306 writel(macaddrhigh, ®s->laddr[0][LADDR_HIGH]);
311 static int zynq_phy_init(struct udevice *dev)
314 struct zynq_gem_priv *priv = dev_get_priv(dev);
315 struct zynq_gem_regs *regs_mdio = priv->mdiobase;
316 const u32 supported = SUPPORTED_10baseT_Half |
317 SUPPORTED_10baseT_Full |
318 SUPPORTED_100baseT_Half |
319 SUPPORTED_100baseT_Full |
320 SUPPORTED_1000baseT_Half |
321 SUPPORTED_1000baseT_Full;
323 /* Enable only MDIO bus */
324 writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s_mdio->nwctrl);
326 if (IS_ENABLED(CONFIG_DM_ETH_PHY))
327 priv->phyaddr = eth_phy_get_addr(dev);
329 priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev,
334 if (priv->max_speed) {
335 ret = phy_set_supported(priv->phydev, priv->max_speed);
340 priv->phydev->supported &= supported | ADVERTISED_Pause |
341 ADVERTISED_Asym_Pause;
343 priv->phydev->advertising = priv->phydev->supported;
344 if (!ofnode_valid(priv->phydev->node))
345 priv->phydev->node = priv->phy_of_node;
347 return phy_config(priv->phydev);
350 static int zynq_gem_init(struct udevice *dev)
354 unsigned long clk_rate = 0;
355 struct zynq_gem_priv *priv = dev_get_priv(dev);
356 struct zynq_gem_regs *regs = priv->iobase;
357 struct zynq_gem_regs *regs_mdio = priv->mdiobase;
358 struct emac_bd *dummy_tx_bd = &priv->tx_bd[TX_FREE_DESC];
359 struct emac_bd *dummy_rx_bd = &priv->tx_bd[TX_FREE_DESC + 2];
361 if (readl(®s->dcfg6) & ZYNQ_GEM_DCFG_DBG6_DMA_64B)
362 priv->dma_64bit = true;
364 priv->dma_64bit = false;
366 #if defined(CONFIG_PHYS_64BIT)
367 if (!priv->dma_64bit) {
368 printf("ERR: %s: Using 64-bit DMA but HW doesn't support it\n",
374 debug("WARN: %s: Not using 64-bit dma even HW supports it\n",
379 /* Disable all interrupts */
380 writel(0xFFFFFFFF, ®s->idr);
382 /* Disable the receiver & transmitter */
383 writel(0, ®s->nwctrl);
384 writel(0, ®s->txsr);
385 writel(0, ®s->rxsr);
386 writel(0, ®s->phymntnc);
388 /* Clear the Hash registers for the mac address
389 * pointed by AddressPtr
391 writel(0x0, ®s->hashl);
392 /* Write bits [63:32] in TOP */
393 writel(0x0, ®s->hashh);
395 /* Clear all counters */
396 for (i = 0; i < STAT_SIZE; i++)
397 readl(®s->stat[i]);
399 /* Setup RxBD space */
400 memset(priv->rx_bd, 0, RX_BUF * sizeof(struct emac_bd));
402 for (i = 0; i < RX_BUF; i++) {
403 priv->rx_bd[i].status = 0xF0000000;
404 priv->rx_bd[i].addr =
405 (lower_32_bits((ulong)(priv->rxbuffers)
406 + (i * PKTSIZE_ALIGN)));
407 #if defined(CONFIG_PHYS_64BIT)
408 priv->rx_bd[i].addr_hi =
409 (upper_32_bits((ulong)(priv->rxbuffers)
410 + (i * PKTSIZE_ALIGN)));
413 /* WRAP bit to last BD */
414 priv->rx_bd[--i].addr |= ZYNQ_GEM_RXBUF_WRAP_MASK;
415 /* Write RxBDs to IP */
416 writel(lower_32_bits((ulong)priv->rx_bd), ®s->rxqbase);
417 #if defined(CONFIG_PHYS_64BIT)
418 writel(upper_32_bits((ulong)priv->rx_bd), ®s->upper_rxqbase);
421 /* Setup for DMA Configuration register */
422 writel(ZYNQ_GEM_DMACR_INIT, ®s->dmacr);
424 /* Setup for Network Control register, MDIO, Rx and Tx enable */
425 setbits_le32(®s_mdio->nwctrl, ZYNQ_GEM_NWCTRL_MDEN_MASK);
427 /* Disable the second priority queue */
428 dummy_tx_bd->addr = 0;
429 #if defined(CONFIG_PHYS_64BIT)
430 dummy_tx_bd->addr_hi = 0;
432 dummy_tx_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
433 ZYNQ_GEM_TXBUF_LAST_MASK|
434 ZYNQ_GEM_TXBUF_USED_MASK;
436 dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK |
437 ZYNQ_GEM_RXBUF_NEW_MASK;
438 #if defined(CONFIG_PHYS_64BIT)
439 dummy_rx_bd->addr_hi = 0;
441 dummy_rx_bd->status = 0;
443 writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr);
444 writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr);
449 ret = phy_startup(priv->phydev);
453 if (!priv->phydev->link) {
454 printf("%s: No link.\n", priv->phydev->dev->name);
458 nwconfig = ZYNQ_GEM_NWCFG_INIT;
461 * Set SGMII enable PCS selection only if internal PCS/PMA
462 * core is used and interface is SGMII.
464 if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
466 nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL |
467 ZYNQ_GEM_NWCFG_PCS_SEL;
470 switch (priv->phydev->speed) {
472 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000,
474 clk_rate = ZYNQ_GEM_FREQUENCY_1000;
477 writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100,
479 clk_rate = ZYNQ_GEM_FREQUENCY_100;
482 clk_rate = ZYNQ_GEM_FREQUENCY_10;
487 if (priv->interface == PHY_INTERFACE_MODE_SGMII &&
490 * Disable AN for fixed link configuration, enable otherwise.
491 * Must be written after PCS_SEL is set in nwconfig,
492 * otherwise writes will not take effect.
494 if (priv->phydev->phy_id != PHY_FIXED_ID)
495 writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
498 writel(readl(®s->pcscntrl) & ~ZYNQ_GEM_PCS_CTL_ANEG_ENBL,
503 ret = clk_set_rate(&priv->tx_clk, clk_rate);
504 if (IS_ERR_VALUE(ret)) {
505 dev_err(dev, "failed to set tx clock rate\n");
509 ret = clk_enable(&priv->tx_clk);
511 dev_err(dev, "failed to enable tx clock\n");
515 if (priv->clk_en_info & RXCLK_EN) {
516 ret = clk_enable(&priv->rx_clk);
518 dev_err(dev, "failed to enable rx clock\n");
522 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
523 ZYNQ_GEM_NWCTRL_TXEN_MASK);
528 static int zynq_gem_send(struct udevice *dev, void *ptr, int len)
532 struct zynq_gem_priv *priv = dev_get_priv(dev);
533 struct zynq_gem_regs *regs = priv->iobase;
534 struct emac_bd *current_bd = &priv->tx_bd[1];
537 memset(priv->tx_bd, 0, sizeof(struct emac_bd));
539 priv->tx_bd->addr = lower_32_bits((ulong)ptr);
540 #if defined(CONFIG_PHYS_64BIT)
541 priv->tx_bd->addr_hi = upper_32_bits((ulong)ptr);
543 priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
544 ZYNQ_GEM_TXBUF_LAST_MASK;
545 /* Dummy descriptor to mark it as the last in descriptor chain */
546 current_bd->addr = 0x0;
547 #if defined(CONFIG_PHYS_64BIT)
548 current_bd->addr_hi = 0x0;
550 current_bd->status = ZYNQ_GEM_TXBUF_WRAP_MASK |
551 ZYNQ_GEM_TXBUF_LAST_MASK|
552 ZYNQ_GEM_TXBUF_USED_MASK;
555 writel(lower_32_bits((ulong)priv->tx_bd), ®s->txqbase);
556 #if defined(CONFIG_PHYS_64BIT)
557 writel(upper_32_bits((ulong)priv->tx_bd), ®s->upper_txqbase);
561 addr &= ~(ARCH_DMA_MINALIGN - 1);
562 size = roundup(len, ARCH_DMA_MINALIGN);
563 flush_dcache_range(addr, addr + size);
567 setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_STARTTX_MASK);
569 /* Read TX BD status */
570 if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED)
571 printf("TX buffers exhausted in mid frame\n");
573 return wait_for_bit_le32(®s->txsr, ZYNQ_GEM_TSR_DONE,
577 /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */
578 static int zynq_gem_recv(struct udevice *dev, int flags, uchar **packetp)
582 struct zynq_gem_priv *priv = dev_get_priv(dev);
583 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
585 if (!(current_bd->addr & ZYNQ_GEM_RXBUF_NEW_MASK))
588 if (!(current_bd->status &
589 (ZYNQ_GEM_RXBUF_SOF_MASK | ZYNQ_GEM_RXBUF_EOF_MASK))) {
590 printf("GEM: SOF or EOF not set for last buffer received!\n");
594 frame_len = current_bd->status & ZYNQ_GEM_RXBUF_LEN_MASK;
596 printf("%s: Zero size packet?\n", __func__);
600 #if defined(CONFIG_PHYS_64BIT)
601 addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK)
602 | ((dma_addr_t)current_bd->addr_hi << 32));
604 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
606 addr &= ~(ARCH_DMA_MINALIGN - 1);
608 *packetp = (uchar *)(uintptr_t)addr;
610 invalidate_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
616 static int zynq_gem_free_pkt(struct udevice *dev, uchar *packet, int length)
618 struct zynq_gem_priv *priv = dev_get_priv(dev);
619 struct emac_bd *current_bd = &priv->rx_bd[priv->rxbd_current];
620 struct emac_bd *first_bd;
623 if (current_bd->status & ZYNQ_GEM_RXBUF_SOF_MASK) {
624 priv->rx_first_buf = priv->rxbd_current;
626 current_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
627 current_bd->status = 0xF0000000; /* FIXME */
630 if (current_bd->status & ZYNQ_GEM_RXBUF_EOF_MASK) {
631 first_bd = &priv->rx_bd[priv->rx_first_buf];
632 first_bd->addr &= ~ZYNQ_GEM_RXBUF_NEW_MASK;
633 first_bd->status = 0xF0000000;
636 /* Flush the cache for the packet as well */
637 #if defined(CONFIG_PHYS_64BIT)
638 addr = (dma_addr_t)((current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK)
639 | ((dma_addr_t)current_bd->addr_hi << 32));
641 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
643 flush_dcache_range(addr, addr + roundup(PKTSIZE_ALIGN,
647 if ((++priv->rxbd_current) >= RX_BUF)
648 priv->rxbd_current = 0;
653 static void zynq_gem_halt(struct udevice *dev)
655 struct zynq_gem_priv *priv = dev_get_priv(dev);
656 struct zynq_gem_regs *regs = priv->iobase;
658 clrsetbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK |
659 ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
662 __weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
667 static int zynq_gem_read_rom_mac(struct udevice *dev)
669 struct eth_pdata *pdata = dev_get_plat(dev);
674 return zynq_board_read_rom_ethaddr(pdata->enetaddr);
677 static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
680 struct zynq_gem_priv *priv = bus->priv;
684 ret = phyread(priv, addr, reg, &val);
685 debug("%s 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, val, ret);
689 static int zynq_gem_miiphy_write(struct mii_dev *bus, int addr, int devad,
692 struct zynq_gem_priv *priv = bus->priv;
694 debug("%s 0x%x, 0x%x, 0x%x\n", __func__, addr, reg, value);
695 return phywrite(priv, addr, reg, value);
698 static int zynq_gem_reset_init(struct udevice *dev)
700 struct zynq_gem_priv *priv = dev_get_priv(dev);
703 ret = reset_get_bulk(dev, &priv->resets);
704 if (ret == -ENOTSUPP || ret == -ENOENT)
709 ret = reset_deassert_bulk(&priv->resets);
711 reset_release_bulk(&priv->resets);
718 static int gem_zynqmp_set_dynamic_config(struct udevice *dev)
723 if (IS_ENABLED(CONFIG_ARCH_ZYNQMP)) {
724 if (!zynqmp_pm_is_function_supported(PM_IOCTL,
725 IOCTL_SET_GEM_CONFIG)) {
726 ret = ofnode_read_u32_array(dev_ofnode(dev),
729 ARRAY_SIZE(pm_info));
732 "Failed to read power-domains info\n");
736 ret = zynqmp_pm_set_gem_config(pm_info[1],
737 GEM_CONFIG_FIXED, 0);
741 ret = zynqmp_pm_set_gem_config(pm_info[1],
742 GEM_CONFIG_SGMII_MODE,
752 static int zynq_gem_probe(struct udevice *dev)
755 struct zynq_gem_priv *priv = dev_get_priv(dev);
759 if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
760 ret = generic_phy_get_by_index(dev, 0, &phy);
762 ret = generic_phy_init(&phy);
765 } else if (ret != -ENOENT) {
766 debug("could not get phy (err %d)\n", ret);
771 ret = zynq_gem_reset_init(dev);
775 /* Align rxbuffers to ARCH_DMA_MINALIGN */
776 priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
777 if (!priv->rxbuffers)
780 memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
781 ulong addr = (ulong)priv->rxbuffers;
782 flush_dcache_range(addr, addr + roundup(RX_BUF * PKTSIZE_ALIGN, ARCH_DMA_MINALIGN));
785 /* Align bd_space to MMU_SECTION_SHIFT */
786 bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
792 mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
793 BD_SPACE, DCACHE_OFF);
795 /* Initialize the bd spaces for tx and rx bd's */
796 priv->tx_bd = (struct emac_bd *)bd_space;
797 priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE);
799 ret = clk_get_by_name(dev, "tx_clk", &priv->tx_clk);
801 dev_err(dev, "failed to get tx_clock\n");
805 if (priv->clk_en_info & RXCLK_EN) {
806 ret = clk_get_by_name(dev, "rx_clk", &priv->rx_clk);
808 dev_err(dev, "failed to get rx_clock\n");
813 if (IS_ENABLED(CONFIG_DM_ETH_PHY))
814 priv->bus = eth_phy_get_mdio_bus(dev);
817 priv->bus = mdio_alloc();
818 priv->bus->read = zynq_gem_miiphy_read;
819 priv->bus->write = zynq_gem_miiphy_write;
820 priv->bus->priv = priv;
822 ret = mdio_register_seq(priv->bus, dev_seq(dev));
827 if (IS_ENABLED(CONFIG_DM_ETH_PHY))
828 eth_phy_set_mdio_bus(dev, priv->bus);
830 ret = zynq_phy_init(dev);
834 if (priv->interface == PHY_INTERFACE_MODE_SGMII && phy.dev) {
835 if (IS_ENABLED(CONFIG_DM_ETH_PHY)) {
836 if (device_is_compatible(dev, "cdns,zynqmp-gem")) {
837 ret = gem_zynqmp_set_dynamic_config(dev);
841 "Failed to set gem dynamic config\n");
846 ret = generic_phy_power_on(&phy);
851 printf("\nZYNQ GEM: %lx, mdio bus %lx, phyaddr %d, interface %s\n",
852 (ulong)priv->iobase, (ulong)priv->mdiobase, priv->phydev->addr,
853 phy_string_for_interface(priv->interface));
858 mdio_unregister(priv->bus);
862 free(priv->rxbuffers);
866 static int zynq_gem_remove(struct udevice *dev)
868 struct zynq_gem_priv *priv = dev_get_priv(dev);
871 mdio_unregister(priv->bus);
872 mdio_free(priv->bus);
877 static const struct eth_ops zynq_gem_ops = {
878 .start = zynq_gem_init,
879 .send = zynq_gem_send,
880 .recv = zynq_gem_recv,
881 .free_pkt = zynq_gem_free_pkt,
882 .stop = zynq_gem_halt,
883 .write_hwaddr = zynq_gem_setup_mac,
884 .read_rom_hwaddr = zynq_gem_read_rom_mac,
887 static int zynq_gem_of_to_plat(struct udevice *dev)
889 struct eth_pdata *pdata = dev_get_plat(dev);
890 struct zynq_gem_priv *priv = dev_get_priv(dev);
891 struct ofnode_phandle_args phandle_args;
893 pdata->iobase = (phys_addr_t)dev_read_addr(dev);
894 priv->iobase = (struct zynq_gem_regs *)pdata->iobase;
895 priv->mdiobase = priv->iobase;
896 /* Hardcode for now */
899 if (!dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
904 debug("phy-handle does exist %s\n", dev->name);
905 if (!(IS_ENABLED(CONFIG_DM_ETH_PHY)))
906 priv->phyaddr = ofnode_read_u32_default
907 (phandle_args.node, "reg", -1);
909 priv->phy_of_node = phandle_args.node;
910 priv->max_speed = ofnode_read_u32_default(phandle_args.node,
914 parent = ofnode_get_parent(phandle_args.node);
915 if (ofnode_name_eq(parent, "mdio"))
916 parent = ofnode_get_parent(parent);
918 addr = ofnode_get_addr(parent);
919 if (addr != FDT_ADDR_T_NONE) {
920 debug("MDIO bus not found %s\n", dev->name);
921 priv->mdiobase = (struct zynq_gem_regs *)addr;
925 pdata->phy_interface = dev_read_phy_mode(dev);
926 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
928 priv->interface = pdata->phy_interface;
930 priv->int_pcs = dev_read_bool(dev, "is-internal-pcspma");
932 priv->clk_en_info = dev_get_driver_data(dev);
937 static const struct udevice_id zynq_gem_ids[] = {
938 { .compatible = "cdns,versal-gem", .data = RXCLK_EN },
939 { .compatible = "cdns,zynqmp-gem" },
940 { .compatible = "cdns,zynq-gem" },
941 { .compatible = "cdns,gem" },
945 U_BOOT_DRIVER(zynq_gem) = {
948 .of_match = zynq_gem_ids,
949 .of_to_plat = zynq_gem_of_to_plat,
950 .probe = zynq_gem_probe,
951 .remove = zynq_gem_remove,
952 .ops = &zynq_gem_ops,
953 .priv_auto = sizeof(struct zynq_gem_priv),
954 .plat_auto = sizeof(struct eth_pdata),