1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2009 Michal Simek
4 * (C) Copyright 2003 Xilinx Inc.
6 * Michal SIMEK <monstr@monstr.eu>
20 #include <linux/delay.h>
21 #include <linux/errno.h>
22 #include <linux/kernel.h>
25 DECLARE_GLOBAL_DATA_PTR;
27 #define ENET_ADDR_LENGTH 6
28 #define ETH_FCS_LEN 4 /* Octets in the FCS */
31 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
32 /* Xmit interrupt enable bit */
33 #define XEL_TSR_XMIT_IE_MASK 0x00000008UL
34 /* Program the MAC address */
35 #define XEL_TSR_PROGRAM_MASK 0x00000002UL
36 /* define for programming the MAC address into the EMAC Lite */
37 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
39 /* Transmit packet length upper byte */
40 #define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
41 /* Transmit packet length lower byte */
42 #define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
45 #define XEL_RSR_RECV_DONE_MASK 0x00000001UL
46 /* Recv interrupt enable bit */
47 #define XEL_RSR_RECV_IE_MASK 0x00000008UL
49 /* MDIO Address Register Bit Masks */
50 #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
51 #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
52 #define XEL_MDIOADDR_PHYADR_SHIFT 5
53 #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
55 /* MDIO Write Data Register Bit Masks */
56 #define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
58 /* MDIO Read Data Register Bit Masks */
59 #define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
61 /* MDIO Control Register Bit Masks */
62 #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
63 #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
65 struct emaclite_regs {
66 u32 tx_ping; /* 0x0 - TX Ping buffer */
68 u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
69 u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
70 u32 mdiord;/* 0x7ec - MDIO Read Data Register */
71 u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
72 u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
73 u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
74 u32 tx_ping_tsr; /* 0x7fc - Tx status */
75 u32 tx_pong; /* 0x800 - TX Pong buffer */
77 u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
78 u32 reserved3; /* 0xff8 */
79 u32 tx_pong_tsr; /* 0xffc - Tx status */
80 u32 rx_ping; /* 0x1000 - Receive Buffer */
82 u32 rx_ping_rsr; /* 0x17fc - Rx status */
83 u32 rx_pong; /* 0x1800 - Receive Buffer */
85 u32 rx_pong_rsr; /* 0x1ffc - Rx status */
89 bool use_rx_pong_buffer_next; /* Next RX buffer to read from */
90 u32 txpp; /* TX ping pong buffer */
91 u32 rxpp; /* RX ping pong buffer */
93 struct emaclite_regs *regs;
94 struct phy_device *phydev;
98 static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */
100 static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
109 from32ptr = (u32 *) srcptr;
111 /* Word aligned buffer, no correction needed. */
112 to32ptr = (u32 *) destptr;
113 while (bytecount > 3) {
114 *to32ptr++ = *from32ptr++;
117 to8ptr = (u8 *) to32ptr;
119 alignbuffer = *from32ptr++;
120 from8ptr = (u8 *) &alignbuffer;
122 for (i = 0; i < bytecount; i++)
123 *to8ptr++ = *from8ptr++;
126 static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount)
130 u32 *to32ptr = (u32 *) destptr;
135 from32ptr = (u32 *) srcptr;
136 while (bytecount > 3) {
138 *to32ptr++ = *from32ptr++;
143 to8ptr = (u8 *) &alignbuffer;
144 from8ptr = (u8 *) from32ptr;
146 for (i = 0; i < bytecount; i++)
147 *to8ptr++ = *from8ptr++;
149 *to32ptr++ = alignbuffer;
152 static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
153 bool set, unsigned int timeout)
156 unsigned long start = get_timer(0);
159 val = __raw_readl(reg);
164 if ((val & mask) == mask)
167 if (get_timer(start) > timeout)
178 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
179 func, reg, mask, set);
184 static int mdio_wait(struct emaclite_regs *regs)
186 return wait_for_bit(__func__, ®s->mdioctrl,
187 XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
190 static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
193 struct emaclite_regs *regs = emaclite->regs;
198 u32 ctrl_reg = __raw_readl(®s->mdioctrl);
199 __raw_writel(XEL_MDIOADDR_OP_MASK
200 | ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
201 | registernum), ®s->mdioaddr);
202 __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, ®s->mdioctrl);
208 *data = __raw_readl(®s->mdiord);
212 static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
215 struct emaclite_regs *regs = emaclite->regs;
221 * Write the PHY address, register number and clear the OP bit in the
222 * MDIO Address register and then write the value into the MDIO Write
223 * Data register. Finally, set the Status bit in the MDIO Control
224 * register to start a MDIO write transaction.
226 u32 ctrl_reg = __raw_readl(®s->mdioctrl);
227 __raw_writel(~XEL_MDIOADDR_OP_MASK
228 & ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
229 | registernum), ®s->mdioaddr);
230 __raw_writel(data, ®s->mdiowr);
231 __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, ®s->mdioctrl);
239 static void emaclite_stop(struct udevice *dev)
244 /* Use MII register 1 (MII status register) to detect PHY */
245 #define PHY_DETECT_REG 1
247 /* Mask used to verify certain PHY features (or register contents)
248 * in the register above:
249 * 0x1000: 10Mbps full duplex support
250 * 0x0800: 10Mbps half duplex support
251 * 0x0008: Auto-negotiation support
253 #define PHY_DETECT_MASK 0x1808
255 static int setup_phy(struct udevice *dev)
259 struct xemaclite *emaclite = dev_get_priv(dev);
260 struct phy_device *phydev;
262 u32 supported = SUPPORTED_10baseT_Half |
263 SUPPORTED_10baseT_Full |
264 SUPPORTED_100baseT_Half |
265 SUPPORTED_100baseT_Full;
267 if (emaclite->phyaddr != -1) {
268 phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
269 if ((phyreg != 0xFFFF) &&
270 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
271 /* Found a valid PHY address */
272 debug("Default phy address %d is valid\n",
275 debug("PHY address is not setup correctly %d\n",
277 emaclite->phyaddr = -1;
281 if (emaclite->phyaddr == -1) {
282 /* detect the PHY address */
283 for (i = 31; i >= 0; i--) {
284 phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
285 if ((phyreg != 0xFFFF) &&
286 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
287 /* Found a valid PHY address */
288 emaclite->phyaddr = i;
289 debug("emaclite: Found valid phy address, %d\n",
296 /* interface - look at tsec */
297 phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
298 PHY_INTERFACE_MODE_MII);
300 * Phy can support 1000baseT but device NOT that's why phydev->supported
301 * must be setup for 1000baseT. phydev->advertising setups what speeds
302 * will be used for autonegotiation where 1000baseT must be disabled.
304 phydev->supported = supported | SUPPORTED_1000baseT_Half |
305 SUPPORTED_1000baseT_Full;
306 phydev->advertising = supported;
307 emaclite->phydev = phydev;
309 ret = phy_startup(phydev);
314 printf("%s: No link.\n", phydev->dev->name);
318 /* Do not setup anything */
322 static int emaclite_start(struct udevice *dev)
324 struct xemaclite *emaclite = dev_get_priv(dev);
325 struct eth_pdata *pdata = dev_get_platdata(dev);
326 struct emaclite_regs *regs = emaclite->regs;
328 debug("EmacLite Initialization Started\n");
331 * TX - TX_PING & TX_PONG initialization
333 /* Restart PING TX */
334 __raw_writel(0, ®s->tx_ping_tsr);
335 /* Copy MAC address */
336 xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_ping,
339 __raw_writel(ENET_ADDR_LENGTH, ®s->tx_ping_tplr);
340 /* Update the MAC address in the EMAC Lite */
341 __raw_writel(XEL_TSR_PROG_MAC_ADDR, ®s->tx_ping_tsr);
342 /* Wait for EMAC Lite to finish with the MAC address update */
343 while ((__raw_readl(®s->tx_ping_tsr) &
344 XEL_TSR_PROG_MAC_ADDR) != 0)
347 if (emaclite->txpp) {
348 /* The same operation with PONG TX */
349 __raw_writel(0, ®s->tx_pong_tsr);
350 xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_pong,
352 __raw_writel(ENET_ADDR_LENGTH, ®s->tx_pong_tplr);
353 __raw_writel(XEL_TSR_PROG_MAC_ADDR, ®s->tx_pong_tsr);
354 while ((__raw_readl(®s->tx_pong_tsr) &
355 XEL_TSR_PROG_MAC_ADDR) != 0)
360 * RX - RX_PING & RX_PONG initialization
362 /* Write out the value to flush the RX buffer */
363 __raw_writel(XEL_RSR_RECV_IE_MASK, ®s->rx_ping_rsr);
366 __raw_writel(XEL_RSR_RECV_IE_MASK, ®s->rx_pong_rsr);
368 __raw_writel(XEL_MDIOCTRL_MDIOEN_MASK, ®s->mdioctrl);
369 if (__raw_readl(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
373 debug("EmacLite Initialization complete\n");
377 static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
380 struct emaclite_regs *regs = emaclite->regs;
383 * Read the other buffer register
384 * and determine if the other buffer is available
386 tmp = ~__raw_readl(®s->tx_ping_tsr);
388 tmp |= ~__raw_readl(®s->tx_pong_tsr);
390 return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
393 static int emaclite_send(struct udevice *dev, void *ptr, int len)
396 struct xemaclite *emaclite = dev_get_priv(dev);
397 struct emaclite_regs *regs = emaclite->regs;
404 while (xemaclite_txbufferavailable(emaclite) && maxtry) {
410 printf("Error: Timeout waiting for ethernet TX buffer\n");
411 /* Restart PING TX */
412 __raw_writel(0, ®s->tx_ping_tsr);
413 if (emaclite->txpp) {
414 __raw_writel(0, ®s->tx_pong_tsr);
419 /* Determine if the expected buffer address is empty */
420 reg = __raw_readl(®s->tx_ping_tsr);
421 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
422 debug("Send packet from tx_ping buffer\n");
423 /* Write the frame to the buffer */
424 xemaclite_alignedwrite(ptr, ®s->tx_ping, len);
426 & (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO),
427 ®s->tx_ping_tplr);
428 reg = __raw_readl(®s->tx_ping_tsr);
429 reg |= XEL_TSR_XMIT_BUSY_MASK;
430 __raw_writel(reg, ®s->tx_ping_tsr);
434 if (emaclite->txpp) {
435 /* Determine if the expected buffer address is empty */
436 reg = __raw_readl(®s->tx_pong_tsr);
437 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
438 debug("Send packet from tx_pong buffer\n");
439 /* Write the frame to the buffer */
440 xemaclite_alignedwrite(ptr, ®s->tx_pong, len);
442 (XEL_TPLR_LENGTH_MASK_HI |
443 XEL_TPLR_LENGTH_MASK_LO),
444 ®s->tx_pong_tplr);
445 reg = __raw_readl(®s->tx_pong_tsr);
446 reg |= XEL_TSR_XMIT_BUSY_MASK;
447 __raw_writel(reg, ®s->tx_pong_tsr);
452 puts("Error while sending frame\n");
456 static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp)
458 u32 length, first_read, reg, attempt = 0;
460 struct xemaclite *emaclite = dev->priv;
461 struct emaclite_regs *regs = emaclite->regs;
462 struct ethernet_hdr *eth;
463 struct ip_udp_hdr *ip;
466 if (!emaclite->use_rx_pong_buffer_next) {
467 reg = __raw_readl(®s->rx_ping_rsr);
468 debug("Testing data at rx_ping\n");
469 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
470 debug("Data found in rx_ping buffer\n");
471 addr = ®s->rx_ping;
472 ack = ®s->rx_ping_rsr;
474 debug("Data not found in rx_ping buffer\n");
475 /* Pong buffer is not available - return immediately */
479 /* Try pong buffer if this is first attempt */
482 emaclite->use_rx_pong_buffer_next =
483 !emaclite->use_rx_pong_buffer_next;
487 reg = __raw_readl(®s->rx_pong_rsr);
488 debug("Testing data at rx_pong\n");
489 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
490 debug("Data found in rx_pong buffer\n");
491 addr = ®s->rx_pong;
492 ack = ®s->rx_pong_rsr;
494 debug("Data not found in rx_pong buffer\n");
495 /* Try ping buffer if this is first attempt */
498 emaclite->use_rx_pong_buffer_next =
499 !emaclite->use_rx_pong_buffer_next;
504 /* Read all bytes for ARP packet with 32bit alignment - 48bytes */
505 first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4);
506 xemaclite_alignedread(addr, etherrxbuff, first_read);
508 /* Detect real packet size */
509 eth = (struct ethernet_hdr *)etherrxbuff;
510 switch (ntohs(eth->et_protlen)) {
513 debug("ARP Packet %x\n", length);
516 ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE);
517 length = ntohs(ip->ip_len);
518 length += ETHER_HDR_SIZE + ETH_FCS_LEN;
519 debug("IP Packet %x\n", length);
522 debug("Other Packet\n");
527 /* Read the rest of the packet which is longer then first read */
528 if (length != first_read)
529 xemaclite_alignedread(addr + first_read,
530 etherrxbuff + first_read,
531 length - first_read);
533 /* Acknowledge the frame */
534 reg = __raw_readl(ack);
535 reg &= ~XEL_RSR_RECV_DONE_MASK;
536 __raw_writel(reg, ack);
538 debug("Packet receive from 0x%p, length %dB\n", addr, length);
539 *packetp = etherrxbuff;
543 static int emaclite_miiphy_read(struct mii_dev *bus, int addr,
549 ret = phyread(bus->priv, addr, reg, &val);
550 debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret);
554 static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad,
557 debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
558 return phywrite(bus->priv, addr, reg, value);
561 static int emaclite_probe(struct udevice *dev)
563 struct xemaclite *emaclite = dev_get_priv(dev);
566 emaclite->bus = mdio_alloc();
567 emaclite->bus->read = emaclite_miiphy_read;
568 emaclite->bus->write = emaclite_miiphy_write;
569 emaclite->bus->priv = emaclite;
571 ret = mdio_register_seq(emaclite->bus, dev->seq);
578 static int emaclite_remove(struct udevice *dev)
580 struct xemaclite *emaclite = dev_get_priv(dev);
582 free(emaclite->phydev);
583 mdio_unregister(emaclite->bus);
584 mdio_free(emaclite->bus);
589 static const struct eth_ops emaclite_ops = {
590 .start = emaclite_start,
591 .send = emaclite_send,
592 .recv = emaclite_recv,
593 .stop = emaclite_stop,
596 static int emaclite_ofdata_to_platdata(struct udevice *dev)
598 struct eth_pdata *pdata = dev_get_platdata(dev);
599 struct xemaclite *emaclite = dev_get_priv(dev);
602 pdata->iobase = (phys_addr_t)devfdt_get_addr(dev);
603 emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase,
606 emaclite->phyaddr = -1;
608 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
611 emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob, offset,
614 emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
615 "xlnx,tx-ping-pong", 0);
616 emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
617 "xlnx,rx-ping-pong", 0);
619 printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
620 emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
625 static const struct udevice_id emaclite_ids[] = {
626 { .compatible = "xlnx,xps-ethernetlite-1.00.a" },
630 U_BOOT_DRIVER(emaclite) = {
633 .of_match = emaclite_ids,
634 .ofdata_to_platdata = emaclite_ofdata_to_platdata,
635 .probe = emaclite_probe,
636 .remove = emaclite_remove,
637 .ops = &emaclite_ops,
638 .priv_auto_alloc_size = sizeof(struct xemaclite),
639 .platdata_auto_alloc_size = sizeof(struct eth_pdata),