1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2009 Michal Simek
4 * (C) Copyright 2003 Xilinx Inc.
6 * Michal SIMEK <monstr@monstr.eu>
16 #include <asm/global_data.h>
21 #include <linux/delay.h>
22 #include <linux/errno.h>
23 #include <linux/kernel.h>
27 DECLARE_GLOBAL_DATA_PTR;
29 #define ENET_ADDR_LENGTH 6
30 #define ETH_FCS_LEN 4 /* Octets in the FCS */
33 #define XEL_TSR_XMIT_BUSY_MASK 0x00000001UL
34 /* Xmit interrupt enable bit */
35 #define XEL_TSR_XMIT_IE_MASK 0x00000008UL
36 /* Program the MAC address */
37 #define XEL_TSR_PROGRAM_MASK 0x00000002UL
38 /* define for programming the MAC address into the EMAC Lite */
39 #define XEL_TSR_PROG_MAC_ADDR (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
41 /* Transmit packet length upper byte */
42 #define XEL_TPLR_LENGTH_MASK_HI 0x0000FF00UL
43 /* Transmit packet length lower byte */
44 #define XEL_TPLR_LENGTH_MASK_LO 0x000000FFUL
47 #define XEL_RSR_RECV_DONE_MASK 0x00000001UL
48 /* Recv interrupt enable bit */
49 #define XEL_RSR_RECV_IE_MASK 0x00000008UL
51 /* MDIO Address Register Bit Masks */
52 #define XEL_MDIOADDR_REGADR_MASK 0x0000001F /* Register Address */
53 #define XEL_MDIOADDR_PHYADR_MASK 0x000003E0 /* PHY Address */
54 #define XEL_MDIOADDR_PHYADR_SHIFT 5
55 #define XEL_MDIOADDR_OP_MASK 0x00000400 /* RD/WR Operation */
57 /* MDIO Write Data Register Bit Masks */
58 #define XEL_MDIOWR_WRDATA_MASK 0x0000FFFF /* Data to be Written */
60 /* MDIO Read Data Register Bit Masks */
61 #define XEL_MDIORD_RDDATA_MASK 0x0000FFFF /* Data to be Read */
63 /* MDIO Control Register Bit Masks */
64 #define XEL_MDIOCTRL_MDIOSTS_MASK 0x00000001 /* MDIO Status Mask */
65 #define XEL_MDIOCTRL_MDIOEN_MASK 0x00000008 /* MDIO Enable */
67 struct emaclite_regs {
68 u32 tx_ping; /* 0x0 - TX Ping buffer */
70 u32 mdioaddr; /* 0x7e4 - MDIO Address Register */
71 u32 mdiowr; /* 0x7e8 - MDIO Write Data Register */
72 u32 mdiord;/* 0x7ec - MDIO Read Data Register */
73 u32 mdioctrl; /* 0x7f0 - MDIO Control Register */
74 u32 tx_ping_tplr; /* 0x7f4 - Tx packet length */
75 u32 global_interrupt; /* 0x7f8 - Global interrupt enable */
76 u32 tx_ping_tsr; /* 0x7fc - Tx status */
77 u32 tx_pong; /* 0x800 - TX Pong buffer */
79 u32 tx_pong_tplr; /* 0xff4 - Tx packet length */
80 u32 reserved3; /* 0xff8 */
81 u32 tx_pong_tsr; /* 0xffc - Tx status */
82 u32 rx_ping; /* 0x1000 - Receive Buffer */
84 u32 rx_ping_rsr; /* 0x17fc - Rx status */
85 u32 rx_pong; /* 0x1800 - Receive Buffer */
87 u32 rx_pong_rsr; /* 0x1ffc - Rx status */
91 bool use_rx_pong_buffer_next; /* Next RX buffer to read from */
92 u32 txpp; /* TX ping pong buffer */
93 u32 rxpp; /* RX ping pong buffer */
95 struct emaclite_regs *regs;
96 struct phy_device *phydev;
100 static uchar etherrxbuff[PKTSIZE_ALIGN]; /* Receive buffer */
102 static void xemaclite_alignedread(u32 *srcptr, void *destptr, u32 bytecount)
111 from32ptr = (u32 *) srcptr;
113 /* Word aligned buffer, no correction needed. */
114 to32ptr = (u32 *) destptr;
115 while (bytecount > 3) {
116 *to32ptr++ = *from32ptr++;
119 to8ptr = (u8 *) to32ptr;
121 alignbuffer = *from32ptr++;
122 from8ptr = (u8 *) &alignbuffer;
124 for (i = 0; i < bytecount; i++)
125 *to8ptr++ = *from8ptr++;
128 static void xemaclite_alignedwrite(void *srcptr, u32 *destptr, u32 bytecount)
132 u32 *to32ptr = (u32 *) destptr;
137 from32ptr = (u32 *) srcptr;
138 while (bytecount > 3) {
140 *to32ptr++ = *from32ptr++;
145 to8ptr = (u8 *) &alignbuffer;
146 from8ptr = (u8 *) from32ptr;
148 for (i = 0; i < bytecount; i++)
149 *to8ptr++ = *from8ptr++;
151 *to32ptr++ = alignbuffer;
154 static int wait_for_bit(const char *func, u32 *reg, const u32 mask,
155 bool set, unsigned int timeout)
158 unsigned long start = get_timer(0);
161 val = __raw_readl(reg);
166 if ((val & mask) == mask)
169 if (get_timer(start) > timeout)
180 debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
181 func, reg, mask, set);
186 static int mdio_wait(struct emaclite_regs *regs)
188 return wait_for_bit(__func__, ®s->mdioctrl,
189 XEL_MDIOCTRL_MDIOSTS_MASK, false, 2000);
192 static u32 phyread(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
195 struct emaclite_regs *regs = emaclite->regs;
200 u32 ctrl_reg = __raw_readl(®s->mdioctrl);
201 __raw_writel(XEL_MDIOADDR_OP_MASK
202 | ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
203 | registernum), ®s->mdioaddr);
204 __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, ®s->mdioctrl);
210 *data = __raw_readl(®s->mdiord);
214 static u32 phywrite(struct xemaclite *emaclite, u32 phyaddress, u32 registernum,
217 struct emaclite_regs *regs = emaclite->regs;
223 * Write the PHY address, register number and clear the OP bit in the
224 * MDIO Address register and then write the value into the MDIO Write
225 * Data register. Finally, set the Status bit in the MDIO Control
226 * register to start a MDIO write transaction.
228 u32 ctrl_reg = __raw_readl(®s->mdioctrl);
229 __raw_writel(~XEL_MDIOADDR_OP_MASK
230 & ((phyaddress << XEL_MDIOADDR_PHYADR_SHIFT)
231 | registernum), ®s->mdioaddr);
232 __raw_writel(data, ®s->mdiowr);
233 __raw_writel(ctrl_reg | XEL_MDIOCTRL_MDIOSTS_MASK, ®s->mdioctrl);
241 static void emaclite_stop(struct udevice *dev)
246 /* Use MII register 1 (MII status register) to detect PHY */
247 #define PHY_DETECT_REG 1
249 /* Mask used to verify certain PHY features (or register contents)
250 * in the register above:
251 * 0x1000: 10Mbps full duplex support
252 * 0x0800: 10Mbps half duplex support
253 * 0x0008: Auto-negotiation support
255 #define PHY_DETECT_MASK 0x1808
257 static int setup_phy(struct udevice *dev)
261 struct xemaclite *emaclite = dev_get_priv(dev);
262 struct phy_device *phydev;
264 u32 supported = SUPPORTED_10baseT_Half |
265 SUPPORTED_10baseT_Full |
266 SUPPORTED_100baseT_Half |
267 SUPPORTED_100baseT_Full;
269 if (emaclite->phyaddr != -1) {
270 phyread(emaclite, emaclite->phyaddr, PHY_DETECT_REG, &phyreg);
271 if ((phyreg != 0xFFFF) &&
272 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
273 /* Found a valid PHY address */
274 debug("Default phy address %d is valid\n",
277 debug("PHY address is not setup correctly %d\n",
279 emaclite->phyaddr = -1;
283 if (emaclite->phyaddr == -1) {
284 /* detect the PHY address */
285 for (i = 31; i >= 0; i--) {
286 phyread(emaclite, i, PHY_DETECT_REG, &phyreg);
287 if ((phyreg != 0xFFFF) &&
288 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
289 /* Found a valid PHY address */
290 emaclite->phyaddr = i;
291 debug("emaclite: Found valid phy address, %d\n",
298 /* interface - look at tsec */
299 phydev = phy_connect(emaclite->bus, emaclite->phyaddr, dev,
300 PHY_INTERFACE_MODE_MII);
302 * Phy can support 1000baseT but device NOT that's why phydev->supported
303 * must be setup for 1000baseT. phydev->advertising setups what speeds
304 * will be used for autonegotiation where 1000baseT must be disabled.
306 phydev->supported = supported | SUPPORTED_1000baseT_Half |
307 SUPPORTED_1000baseT_Full;
308 phydev->advertising = supported;
309 emaclite->phydev = phydev;
311 ret = phy_startup(phydev);
316 printf("%s: No link.\n", phydev->dev->name);
320 /* Do not setup anything */
324 static int emaclite_start(struct udevice *dev)
326 struct xemaclite *emaclite = dev_get_priv(dev);
327 struct eth_pdata *pdata = dev_get_plat(dev);
328 struct emaclite_regs *regs = emaclite->regs;
330 debug("EmacLite Initialization Started\n");
333 * TX - TX_PING & TX_PONG initialization
335 /* Restart PING TX */
336 __raw_writel(0, ®s->tx_ping_tsr);
337 /* Copy MAC address */
338 xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_ping,
341 __raw_writel(ENET_ADDR_LENGTH, ®s->tx_ping_tplr);
342 /* Update the MAC address in the EMAC Lite */
343 __raw_writel(XEL_TSR_PROG_MAC_ADDR, ®s->tx_ping_tsr);
344 /* Wait for EMAC Lite to finish with the MAC address update */
345 while ((__raw_readl(®s->tx_ping_tsr) &
346 XEL_TSR_PROG_MAC_ADDR) != 0)
349 if (emaclite->txpp) {
350 /* The same operation with PONG TX */
351 __raw_writel(0, ®s->tx_pong_tsr);
352 xemaclite_alignedwrite(pdata->enetaddr, ®s->tx_pong,
354 __raw_writel(ENET_ADDR_LENGTH, ®s->tx_pong_tplr);
355 __raw_writel(XEL_TSR_PROG_MAC_ADDR, ®s->tx_pong_tsr);
356 while ((__raw_readl(®s->tx_pong_tsr) &
357 XEL_TSR_PROG_MAC_ADDR) != 0)
362 * RX - RX_PING & RX_PONG initialization
364 /* Write out the value to flush the RX buffer */
365 __raw_writel(XEL_RSR_RECV_IE_MASK, ®s->rx_ping_rsr);
368 __raw_writel(XEL_RSR_RECV_IE_MASK, ®s->rx_pong_rsr);
370 __raw_writel(XEL_MDIOCTRL_MDIOEN_MASK, ®s->mdioctrl);
371 if (__raw_readl(®s->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK)
375 debug("EmacLite Initialization complete\n");
379 static int xemaclite_txbufferavailable(struct xemaclite *emaclite)
382 struct emaclite_regs *regs = emaclite->regs;
385 * Read the other buffer register
386 * and determine if the other buffer is available
388 tmp = ~__raw_readl(®s->tx_ping_tsr);
390 tmp |= ~__raw_readl(®s->tx_pong_tsr);
392 return !(tmp & XEL_TSR_XMIT_BUSY_MASK);
395 static int emaclite_send(struct udevice *dev, void *ptr, int len)
398 struct xemaclite *emaclite = dev_get_priv(dev);
399 struct emaclite_regs *regs = emaclite->regs;
406 while (xemaclite_txbufferavailable(emaclite) && maxtry) {
412 printf("Error: Timeout waiting for ethernet TX buffer\n");
413 /* Restart PING TX */
414 __raw_writel(0, ®s->tx_ping_tsr);
415 if (emaclite->txpp) {
416 __raw_writel(0, ®s->tx_pong_tsr);
421 /* Determine if the expected buffer address is empty */
422 reg = __raw_readl(®s->tx_ping_tsr);
423 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
424 debug("Send packet from tx_ping buffer\n");
425 /* Write the frame to the buffer */
426 xemaclite_alignedwrite(ptr, ®s->tx_ping, len);
428 & (XEL_TPLR_LENGTH_MASK_HI | XEL_TPLR_LENGTH_MASK_LO),
429 ®s->tx_ping_tplr);
430 reg = __raw_readl(®s->tx_ping_tsr);
431 reg |= XEL_TSR_XMIT_BUSY_MASK;
432 __raw_writel(reg, ®s->tx_ping_tsr);
436 if (emaclite->txpp) {
437 /* Determine if the expected buffer address is empty */
438 reg = __raw_readl(®s->tx_pong_tsr);
439 if ((reg & XEL_TSR_XMIT_BUSY_MASK) == 0) {
440 debug("Send packet from tx_pong buffer\n");
441 /* Write the frame to the buffer */
442 xemaclite_alignedwrite(ptr, ®s->tx_pong, len);
444 (XEL_TPLR_LENGTH_MASK_HI |
445 XEL_TPLR_LENGTH_MASK_LO),
446 ®s->tx_pong_tplr);
447 reg = __raw_readl(®s->tx_pong_tsr);
448 reg |= XEL_TSR_XMIT_BUSY_MASK;
449 __raw_writel(reg, ®s->tx_pong_tsr);
454 puts("Error while sending frame\n");
458 static int emaclite_recv(struct udevice *dev, int flags, uchar **packetp)
460 u32 length, first_read, reg, attempt = 0;
462 struct xemaclite *emaclite = dev_get_priv(dev);
463 struct emaclite_regs *regs = emaclite->regs;
464 struct ethernet_hdr *eth;
465 struct ip_udp_hdr *ip;
468 if (!emaclite->use_rx_pong_buffer_next) {
469 reg = __raw_readl(®s->rx_ping_rsr);
470 debug("Testing data at rx_ping\n");
471 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
472 debug("Data found in rx_ping buffer\n");
473 addr = ®s->rx_ping;
474 ack = ®s->rx_ping_rsr;
476 debug("Data not found in rx_ping buffer\n");
477 /* Pong buffer is not available - return immediately */
481 /* Try pong buffer if this is first attempt */
484 emaclite->use_rx_pong_buffer_next =
485 !emaclite->use_rx_pong_buffer_next;
489 reg = __raw_readl(®s->rx_pong_rsr);
490 debug("Testing data at rx_pong\n");
491 if ((reg & XEL_RSR_RECV_DONE_MASK) == XEL_RSR_RECV_DONE_MASK) {
492 debug("Data found in rx_pong buffer\n");
493 addr = ®s->rx_pong;
494 ack = ®s->rx_pong_rsr;
496 debug("Data not found in rx_pong buffer\n");
497 /* Try ping buffer if this is first attempt */
500 emaclite->use_rx_pong_buffer_next =
501 !emaclite->use_rx_pong_buffer_next;
506 /* Read all bytes for ARP packet with 32bit alignment - 48bytes */
507 first_read = ALIGN(ETHER_HDR_SIZE + ARP_HDR_SIZE + ETH_FCS_LEN, 4);
508 xemaclite_alignedread(addr, etherrxbuff, first_read);
510 /* Detect real packet size */
511 eth = (struct ethernet_hdr *)etherrxbuff;
512 switch (ntohs(eth->et_protlen)) {
515 debug("ARP Packet %x\n", length);
518 ip = (struct ip_udp_hdr *)(etherrxbuff + ETHER_HDR_SIZE);
519 length = ntohs(ip->ip_len);
520 length += ETHER_HDR_SIZE + ETH_FCS_LEN;
521 debug("IP Packet %x\n", length);
524 debug("Other Packet\n");
529 /* Read the rest of the packet which is longer then first read */
530 if (length != first_read)
531 xemaclite_alignedread(addr + first_read,
532 etherrxbuff + first_read,
533 length - first_read);
535 /* Acknowledge the frame */
536 reg = __raw_readl(ack);
537 reg &= ~XEL_RSR_RECV_DONE_MASK;
538 __raw_writel(reg, ack);
540 debug("Packet receive from 0x%p, length %dB\n", addr, length);
541 *packetp = etherrxbuff;
545 static int emaclite_miiphy_read(struct mii_dev *bus, int addr,
551 ret = phyread(bus->priv, addr, reg, &val);
552 debug("emaclite: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg, val, ret);
556 static int emaclite_miiphy_write(struct mii_dev *bus, int addr, int devad,
559 debug("emaclite: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
560 return phywrite(bus->priv, addr, reg, value);
563 static int emaclite_probe(struct udevice *dev)
565 struct xemaclite *emaclite = dev_get_priv(dev);
568 if (IS_ENABLED(CONFIG_DM_ETH_PHY))
569 emaclite->bus = eth_phy_get_mdio_bus(dev);
571 if (!emaclite->bus) {
572 emaclite->bus = mdio_alloc();
573 emaclite->bus->read = emaclite_miiphy_read;
574 emaclite->bus->write = emaclite_miiphy_write;
575 emaclite->bus->priv = emaclite;
577 ret = mdio_register_seq(emaclite->bus, dev_seq(dev));
582 if (IS_ENABLED(CONFIG_DM_ETH_PHY)) {
583 eth_phy_set_mdio_bus(dev, emaclite->bus);
584 emaclite->phyaddr = eth_phy_get_addr(dev);
587 printf("EMACLITE: %lx, phyaddr %d, %d/%d\n", (ulong)emaclite->regs,
588 emaclite->phyaddr, emaclite->txpp, emaclite->rxpp);
593 static int emaclite_remove(struct udevice *dev)
595 struct xemaclite *emaclite = dev_get_priv(dev);
597 free(emaclite->phydev);
598 mdio_unregister(emaclite->bus);
599 mdio_free(emaclite->bus);
604 static const struct eth_ops emaclite_ops = {
605 .start = emaclite_start,
606 .send = emaclite_send,
607 .recv = emaclite_recv,
608 .stop = emaclite_stop,
611 static int emaclite_of_to_plat(struct udevice *dev)
613 struct eth_pdata *pdata = dev_get_plat(dev);
614 struct xemaclite *emaclite = dev_get_priv(dev);
617 pdata->iobase = dev_read_addr(dev);
618 emaclite->regs = (struct emaclite_regs *)ioremap_nocache(pdata->iobase,
621 emaclite->phyaddr = -1;
623 if (!(IS_ENABLED(CONFIG_DM_ETH_PHY))) {
624 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
627 emaclite->phyaddr = fdtdec_get_int(gd->fdt_blob,
631 emaclite->txpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
632 "xlnx,tx-ping-pong", 0);
633 emaclite->rxpp = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
634 "xlnx,rx-ping-pong", 0);
639 static const struct udevice_id emaclite_ids[] = {
640 { .compatible = "xlnx,xps-ethernetlite-1.00.a" },
644 U_BOOT_DRIVER(emaclite) = {
647 .of_match = emaclite_ids,
648 .of_to_plat = emaclite_of_to_plat,
649 .probe = emaclite_probe,
650 .remove = emaclite_remove,
651 .ops = &emaclite_ops,
652 .priv_auto = sizeof(struct xemaclite),
653 .plat_auto = sizeof(struct eth_pdata),