2 * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
3 * Copyright (C) 2011 PetaLogix
4 * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
6 * SPDX-License-Identifier: GPL-2.0+
18 DECLARE_GLOBAL_DATA_PTR;
20 #if !defined(CONFIG_PHYLIB)
21 # error AXI_ETHERNET requires PHYLIB
25 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
26 #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
27 #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
28 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
30 /* Interrupt Status/Enable/Mask Registers bit definitions */
31 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
32 #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
34 /* Receive Configuration Word 1 (RCW1) Register bit definitions */
35 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
37 /* Transmitter Configuration (TC) Register bit definitions */
38 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
40 #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
42 /* MDIO Management Configuration (MC) Register bit definitions */
43 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/
45 /* MDIO Management Control Register (MCR) Register bit definitions */
46 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
47 #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
48 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
49 #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
50 #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
51 #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
52 #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
53 #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
55 #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
58 /* Bitmasks of XAXIDMA_CR_OFFSET register */
59 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
60 #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
62 /* Bitmasks of XAXIDMA_SR_OFFSET register */
63 #define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */
65 /* Bitmask for interrupts */
66 #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
67 #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
68 #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
70 /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
71 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
72 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
76 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
78 /* Reflect dma offsets */
80 u32 control; /* DMACR */
81 u32 status; /* DMASR */
82 u32 current; /* CURDESC */
84 u32 tail; /* TAILDESC */
87 /* Private driver structures */
89 struct axidma_reg *dmatx;
90 struct axidma_reg *dmarx;
92 struct axi_regs *iobase;
93 phy_interface_t interface;
94 struct phy_device *phydev;
100 u32 next; /* Next descriptor pointer */
102 u32 phys; /* Buffer address */
106 u32 cntrl; /* Control */
107 u32 status; /* Status */
109 u32 app1; /* TX start << 16 | insert */
110 u32 app2; /* TX csum seed */
118 /* Static BDs - driver uses only one BD */
119 static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
120 static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
124 u32 is; /* 0xC: Interrupt status */
126 u32 ie; /* 0x14: Interrupt enable */
128 u32 rcw1; /* 0x404: Rx Configuration Word 1 */
129 u32 tc; /* 0x408: Tx Configuration */
131 u32 emmc; /* 0x410: EMAC mode configuration */
133 u32 mdio_mc; /* 0x500: MII Management Config */
134 u32 mdio_mcr; /* 0x504: MII Management Control */
135 u32 mdio_mwd; /* 0x508: MII Management Write Data */
136 u32 mdio_mrd; /* 0x50C: MII Management Read Data */
138 u32 uaw0; /* 0x700: Unicast address word 0 */
139 u32 uaw1; /* 0x704: Unicast address word 1 */
142 /* Use MII register 1 (MII status register) to detect PHY */
143 #define PHY_DETECT_REG 1
146 * Mask used to verify certain PHY features (or register contents)
147 * in the register above:
148 * 0x1000: 10Mbps full duplex support
149 * 0x0800: 10Mbps half duplex support
150 * 0x0008: Auto-negotiation support
152 #define PHY_DETECT_MASK 0x1808
154 static inline int mdio_wait(struct axi_regs *regs)
158 /* Wait till MDIO interface is ready to accept a new transaction. */
159 while (timeout && (!(in_be32(®s->mdio_mcr)
160 & XAE_MDIO_MCR_READY_MASK))) {
165 printf("%s: Timeout\n", __func__);
171 static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
174 struct axi_regs *regs = priv->iobase;
180 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
181 XAE_MDIO_MCR_PHYAD_MASK) |
182 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
183 & XAE_MDIO_MCR_REGAD_MASK) |
184 XAE_MDIO_MCR_INITIATE_MASK |
185 XAE_MDIO_MCR_OP_READ_MASK;
187 out_be32(®s->mdio_mcr, mdioctrlreg);
193 *val = in_be32(®s->mdio_mrd);
197 static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
200 struct axi_regs *regs = priv->iobase;
206 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
207 XAE_MDIO_MCR_PHYAD_MASK) |
208 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
209 & XAE_MDIO_MCR_REGAD_MASK) |
210 XAE_MDIO_MCR_INITIATE_MASK |
211 XAE_MDIO_MCR_OP_WRITE_MASK;
214 out_be32(®s->mdio_mwd, data);
216 out_be32(®s->mdio_mcr, mdioctrlreg);
224 static int axiemac_phy_init(struct udevice *dev)
228 struct axidma_priv *priv = dev_get_priv(dev);
229 struct axi_regs *regs = priv->iobase;
230 struct phy_device *phydev;
232 u32 supported = SUPPORTED_10baseT_Half |
233 SUPPORTED_10baseT_Full |
234 SUPPORTED_100baseT_Half |
235 SUPPORTED_100baseT_Full |
236 SUPPORTED_1000baseT_Half |
237 SUPPORTED_1000baseT_Full;
239 /* Set default MDIO divisor */
240 out_be32(®s->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK);
242 if (priv->phyaddr == -1) {
243 /* Detect the PHY address */
244 for (i = 31; i >= 0; i--) {
245 ret = phyread(priv, i, PHY_DETECT_REG, &phyreg);
246 if (!ret && (phyreg != 0xFFFF) &&
247 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
248 /* Found a valid PHY address */
250 debug("axiemac: Found valid phy address, %x\n",
257 /* Interface - look at tsec */
258 phydev = phy_connect(priv->bus, priv->phyaddr, dev, 0);
260 phydev->supported &= supported;
261 phydev->advertising = phydev->supported;
262 priv->phydev = phydev;
268 /* Setting axi emac and phy to proper setting */
269 static int setup_phy(struct udevice *dev)
272 struct axidma_priv *priv = dev_get_priv(dev);
273 struct axi_regs *regs = priv->iobase;
274 struct phy_device *phydev = priv->phydev;
276 if (phy_startup(phydev)) {
277 printf("axiemac: could not initialize PHY %s\n",
282 printf("%s: No link.\n", phydev->dev->name);
286 switch (phydev->speed) {
288 speed = XAE_EMMC_LINKSPD_1000;
291 speed = XAE_EMMC_LINKSPD_100;
294 speed = XAE_EMMC_LINKSPD_10;
300 /* Setup the emac for the phy speed */
301 emmc_reg = in_be32(®s->emmc);
302 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
305 /* Write new speed setting out to Axi Ethernet */
306 out_be32(®s->emmc, emmc_reg);
309 * Setting the operating speed of the MAC needs a delay. There
310 * doesn't seem to be register to poll, so please consider this
311 * during your application design.
318 /* STOP DMA transfers */
319 static void axiemac_halt(struct udevice *dev)
321 struct axidma_priv *priv = dev_get_priv(dev);
324 /* Stop the hardware */
325 temp = in_be32(&priv->dmatx->control);
326 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
327 out_be32(&priv->dmatx->control, temp);
329 temp = in_be32(&priv->dmarx->control);
330 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
331 out_be32(&priv->dmarx->control, temp);
333 debug("axiemac: Halted\n");
336 static int axi_ethernet_init(struct axidma_priv *priv)
338 struct axi_regs *regs = priv->iobase;
342 * Check the status of the MgtRdy bit in the interrupt status
343 * registers. This must be done to allow the MGT clock to become stable
344 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
345 * will be valid until this bit is valid.
346 * The bit is always a 1 for all other PHY interfaces.
348 while (timeout && (!(in_be32(®s->is) & XAE_INT_MGTRDY_MASK))) {
353 printf("%s: Timeout\n", __func__);
357 /* Stop the device and reset HW */
358 /* Disable interrupts */
359 out_be32(®s->ie, 0);
361 /* Disable the receiver */
362 out_be32(®s->rcw1, in_be32(®s->rcw1) & ~XAE_RCW1_RX_MASK);
365 * Stopping the receiver in mid-packet causes a dropped packet
366 * indication from HW. Clear it.
368 /* Set the interrupt status register to clear the interrupt */
369 out_be32(®s->is, XAE_INT_RXRJECT_MASK);
372 /* Set default MDIO divisor */
373 out_be32(®s->mdio_mc, XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK);
375 debug("axiemac: InitHw done\n");
379 static int axiemac_setup_mac(struct udevice *dev)
381 struct eth_pdata *pdata = dev_get_platdata(dev);
382 struct axidma_priv *priv = dev_get_priv(dev);
383 struct axi_regs *regs = priv->iobase;
385 /* Set the MAC address */
386 int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
387 (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
388 out_be32(®s->uaw0, val);
390 val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
391 val |= in_be32(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
392 out_be32(®s->uaw1, val);
396 /* Reset DMA engine */
397 static void axi_dma_init(struct axidma_priv *priv)
401 /* Reset the engine so the hardware starts from a known state */
402 out_be32(&priv->dmatx->control, XAXIDMA_CR_RESET_MASK);
403 out_be32(&priv->dmarx->control, XAXIDMA_CR_RESET_MASK);
405 /* At the initialization time, hardware should finish reset quickly */
407 /* Check transmit/receive channel */
408 /* Reset is done when the reset bit is low */
409 if (!((in_be32(&priv->dmatx->control) |
410 in_be32(&priv->dmarx->control))
411 & XAXIDMA_CR_RESET_MASK)) {
416 printf("%s: Timeout\n", __func__);
419 static int axiemac_init(struct udevice *dev)
421 struct axidma_priv *priv = dev_get_priv(dev);
422 struct axi_regs *regs = priv->iobase;
425 debug("axiemac: Init started\n");
427 * Initialize AXIDMA engine. AXIDMA engine must be initialized before
428 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
429 * reset, and since AXIDMA reset line is connected to AxiEthernet, this
430 * would ensure a reset of AxiEthernet.
434 /* Initialize AxiEthernet hardware. */
435 if (axi_ethernet_init(priv))
438 /* Disable all RX interrupts before RxBD space setup */
439 temp = in_be32(&priv->dmarx->control);
440 temp &= ~XAXIDMA_IRQ_ALL_MASK;
441 out_be32(&priv->dmarx->control, temp);
443 /* Start DMA RX channel. Now it's ready to receive data.*/
444 out_be32(&priv->dmarx->current, (u32)&rx_bd);
447 memset(&rx_bd, 0, sizeof(rx_bd));
448 rx_bd.next = (u32)&rx_bd;
449 rx_bd.phys = (u32)&rxframe;
450 rx_bd.cntrl = sizeof(rxframe);
451 /* Flush the last BD so DMA core could see the updates */
452 flush_cache((u32)&rx_bd, sizeof(rx_bd));
454 /* It is necessary to flush rxframe because if you don't do it
455 * then cache can contain uninitialized data */
456 flush_cache((u32)&rxframe, sizeof(rxframe));
458 /* Start the hardware */
459 temp = in_be32(&priv->dmarx->control);
460 temp |= XAXIDMA_CR_RUNSTOP_MASK;
461 out_be32(&priv->dmarx->control, temp);
463 /* Rx BD is ready - start */
464 out_be32(&priv->dmarx->tail, (u32)&rx_bd);
467 out_be32(®s->tc, XAE_TC_TX_MASK);
469 out_be32(®s->rcw1, XAE_RCW1_RX_MASK);
472 if (!setup_phy(dev)) {
477 debug("axiemac: Init complete\n");
481 static int axiemac_send(struct udevice *dev, void *ptr, int len)
483 struct axidma_priv *priv = dev_get_priv(dev);
486 if (len > PKTSIZE_ALIGN)
489 /* Flush packet to main memory to be trasfered by DMA */
490 flush_cache((u32)ptr, len);
493 memset(&tx_bd, 0, sizeof(tx_bd));
494 /* At the end of the ring, link the last BD back to the top */
495 tx_bd.next = (u32)&tx_bd;
496 tx_bd.phys = (u32)ptr;
498 tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
499 XAXIDMA_BD_CTRL_TXEOF_MASK;
501 /* Flush the last BD so DMA core could see the updates */
502 flush_cache((u32)&tx_bd, sizeof(tx_bd));
504 if (in_be32(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
506 out_be32(&priv->dmatx->current, (u32)&tx_bd);
507 /* Start the hardware */
508 temp = in_be32(&priv->dmatx->control);
509 temp |= XAXIDMA_CR_RUNSTOP_MASK;
510 out_be32(&priv->dmatx->control, temp);
514 out_be32(&priv->dmatx->tail, (u32)&tx_bd);
516 /* Wait for transmission to complete */
517 debug("axiemac: Waiting for tx to be done\n");
519 while (timeout && (!(in_be32(&priv->dmatx->status) &
520 (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
525 printf("%s: Timeout\n", __func__);
529 debug("axiemac: Sending complete\n");
533 static int isrxready(struct axidma_priv *priv)
537 /* Read pending interrupts */
538 status = in_be32(&priv->dmarx->status);
540 /* Acknowledge pending interrupts */
541 out_be32(&priv->dmarx->status, status & XAXIDMA_IRQ_ALL_MASK);
544 * If Reception done interrupt is asserted, call RX call back function
545 * to handle the processed BDs and then raise the according flag.
547 if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
553 static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
556 struct axidma_priv *priv = dev_get_priv(dev);
559 /* Wait for an incoming packet */
560 if (!isrxready(priv))
563 debug("axiemac: RX data ready\n");
565 /* Disable IRQ for a moment till packet is handled */
566 temp = in_be32(&priv->dmarx->control);
567 temp &= ~XAXIDMA_IRQ_ALL_MASK;
568 out_be32(&priv->dmarx->control, temp);
570 length = rx_bd.app4 & 0xFFFF; /* max length mask */
572 print_buffer(&rxframe, &rxframe[0], 1, length, 16);
579 static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
581 struct axidma_priv *priv = dev_get_priv(dev);
584 /* It is useful to clear buffer to be sure that it is consistent */
585 memset(rxframe, 0, sizeof(rxframe));
588 /* Clear the whole buffer and setup it again - all flags are cleared */
589 memset(&rx_bd, 0, sizeof(rx_bd));
590 rx_bd.next = (u32)&rx_bd;
591 rx_bd.phys = (u32)&rxframe;
592 rx_bd.cntrl = sizeof(rxframe);
595 flush_cache((u32)&rx_bd, sizeof(rx_bd));
597 /* It is necessary to flush rxframe because if you don't do it
598 * then cache will contain previous packet */
599 flush_cache((u32)&rxframe, sizeof(rxframe));
601 /* Rx BD is ready - start again */
602 out_be32(&priv->dmarx->tail, (u32)&rx_bd);
604 debug("axiemac: RX completed, framelength = %d\n", length);
609 static int axiemac_miiphy_read(struct mii_dev *bus, int addr,
615 ret = phyread(bus->priv, addr, reg, &value);
616 debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg,
621 static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad,
624 debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
625 return phywrite(bus->priv, addr, reg, value);
628 static int axi_emac_probe(struct udevice *dev)
630 struct axidma_priv *priv = dev_get_priv(dev);
633 priv->bus = mdio_alloc();
634 priv->bus->read = axiemac_miiphy_read;
635 priv->bus->write = axiemac_miiphy_write;
636 priv->bus->priv = priv;
637 strcpy(priv->bus->name, "axi_emac");
639 ret = mdio_register(priv->bus);
643 axiemac_phy_init(dev);
648 static int axi_emac_remove(struct udevice *dev)
650 struct axidma_priv *priv = dev_get_priv(dev);
653 mdio_unregister(priv->bus);
654 mdio_free(priv->bus);
659 static const struct eth_ops axi_emac_ops = {
660 .start = axiemac_init,
661 .send = axiemac_send,
662 .recv = axiemac_recv,
663 .free_pkt = axiemac_free_pkt,
664 .stop = axiemac_halt,
665 .write_hwaddr = axiemac_setup_mac,
668 static int axi_emac_ofdata_to_platdata(struct udevice *dev)
670 struct eth_pdata *pdata = dev_get_platdata(dev);
671 struct axidma_priv *priv = dev_get_priv(dev);
673 const char *phy_mode;
675 pdata->iobase = (phys_addr_t)dev_get_addr(dev);
676 priv->iobase = (struct axi_regs *)pdata->iobase;
678 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
679 "axistream-connected");
681 printf("%s: axistream is not found\n", __func__);
684 priv->dmatx = (struct axidma_reg *)fdtdec_get_int(gd->fdt_blob,
687 printf("%s: axi_dma register space not found\n", __func__);
690 /* RX channel offset is 0x30 */
691 priv->dmarx = (struct axidma_reg *)((u32)priv->dmatx + 0x30);
695 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
698 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
700 phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
702 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
703 if (pdata->phy_interface == -1) {
704 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
707 priv->interface = pdata->phy_interface;
709 printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
710 priv->phyaddr, phy_string_for_interface(priv->interface));
715 static const struct udevice_id axi_emac_ids[] = {
716 { .compatible = "xlnx,axi-ethernet-1.00.a" },
720 U_BOOT_DRIVER(axi_emac) = {
723 .of_match = axi_emac_ids,
724 .ofdata_to_platdata = axi_emac_ofdata_to_platdata,
725 .probe = axi_emac_probe,
726 .remove = axi_emac_remove,
727 .ops = &axi_emac_ops,
728 .priv_auto_alloc_size = sizeof(struct axidma_priv),
729 .platdata_auto_alloc_size = sizeof(struct eth_pdata),