1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2011 PetaLogix
5 * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
19 #include <linux/delay.h>
21 DECLARE_GLOBAL_DATA_PTR;
24 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
25 #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
26 #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
27 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
29 /* Interrupt Status/Enable/Mask Registers bit definitions */
30 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
31 #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
33 /* Receive Configuration Word 1 (RCW1) Register bit definitions */
34 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
36 /* Transmitter Configuration (TC) Register bit definitions */
37 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
39 #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
41 /* MDIO Management Configuration (MC) Register bit definitions */
42 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/
44 /* MDIO Management Control Register (MCR) Register bit definitions */
45 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
46 #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
47 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
48 #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
49 #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
50 #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
51 #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
52 #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
54 #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
56 #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */
59 /* Bitmasks of XAXIDMA_CR_OFFSET register */
60 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
61 #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
63 /* Bitmasks of XAXIDMA_SR_OFFSET register */
64 #define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */
66 /* Bitmask for interrupts */
67 #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
68 #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
69 #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
71 /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
72 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
73 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
77 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
79 /* Reflect dma offsets */
81 u32 control; /* DMACR */
82 u32 status; /* DMASR */
83 u32 current; /* CURDESC low 32 bit */
84 u32 current_hi; /* CURDESC high 32 bit */
85 u32 tail; /* TAILDESC low 32 bit */
86 u32 tail_hi; /* TAILDESC high 32 bit */
89 /* Private driver structures */
91 struct axidma_reg *dmatx;
92 struct axidma_reg *dmarx;
94 struct axi_regs *iobase;
95 phy_interface_t interface;
96 struct phy_device *phydev;
104 u32 next_desc; /* Next descriptor pointer */
106 u32 buf_addr; /* Buffer address */
110 u32 cntrl; /* Control */
111 u32 status; /* Status */
113 u32 app1; /* TX start << 16 | insert */
114 u32 app2; /* TX csum seed */
122 /* Static BDs - driver uses only one BD */
123 static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
124 static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
128 u32 is; /* 0xC: Interrupt status */
130 u32 ie; /* 0x14: Interrupt enable */
132 u32 rcw1; /* 0x404: Rx Configuration Word 1 */
133 u32 tc; /* 0x408: Tx Configuration */
135 u32 emmc; /* 0x410: EMAC mode configuration */
137 u32 mdio_mc; /* 0x500: MII Management Config */
138 u32 mdio_mcr; /* 0x504: MII Management Control */
139 u32 mdio_mwd; /* 0x508: MII Management Write Data */
140 u32 mdio_mrd; /* 0x50C: MII Management Read Data */
142 u32 uaw0; /* 0x700: Unicast address word 0 */
143 u32 uaw1; /* 0x704: Unicast address word 1 */
146 /* Use MII register 1 (MII status register) to detect PHY */
147 #define PHY_DETECT_REG 1
150 * Mask used to verify certain PHY features (or register contents)
151 * in the register above:
152 * 0x1000: 10Mbps full duplex support
153 * 0x0800: 10Mbps half duplex support
154 * 0x0008: Auto-negotiation support
156 #define PHY_DETECT_MASK 0x1808
158 static inline int mdio_wait(struct axi_regs *regs)
162 /* Wait till MDIO interface is ready to accept a new transaction. */
163 while (timeout && (!(readl(®s->mdio_mcr)
164 & XAE_MDIO_MCR_READY_MASK))) {
169 printf("%s: Timeout\n", __func__);
176 * axienet_dma_write - Memory mapped Axi DMA register Buffer Descriptor write.
177 * @bd: pointer to BD descriptor structure
178 * @desc: Address offset of DMA descriptors
180 * This function writes the value into the corresponding Axi DMA register.
182 static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc)
184 #if defined(CONFIG_PHYS_64BIT)
185 writeq((unsigned long)bd, desc);
187 writel((u32)bd, desc);
191 static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
194 struct axi_regs *regs = priv->iobase;
200 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
201 XAE_MDIO_MCR_PHYAD_MASK) |
202 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
203 & XAE_MDIO_MCR_REGAD_MASK) |
204 XAE_MDIO_MCR_INITIATE_MASK |
205 XAE_MDIO_MCR_OP_READ_MASK;
207 writel(mdioctrlreg, ®s->mdio_mcr);
213 *val = readl(®s->mdio_mrd);
217 static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
220 struct axi_regs *regs = priv->iobase;
226 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
227 XAE_MDIO_MCR_PHYAD_MASK) |
228 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
229 & XAE_MDIO_MCR_REGAD_MASK) |
230 XAE_MDIO_MCR_INITIATE_MASK |
231 XAE_MDIO_MCR_OP_WRITE_MASK;
234 writel(data, ®s->mdio_mwd);
236 writel(mdioctrlreg, ®s->mdio_mcr);
244 static int axiemac_phy_init(struct udevice *dev)
249 struct axidma_priv *priv = dev_get_priv(dev);
250 struct axi_regs *regs = priv->iobase;
251 struct phy_device *phydev;
253 u32 supported = SUPPORTED_10baseT_Half |
254 SUPPORTED_10baseT_Full |
255 SUPPORTED_100baseT_Half |
256 SUPPORTED_100baseT_Full |
257 SUPPORTED_1000baseT_Half |
258 SUPPORTED_1000baseT_Full;
260 /* Set default MDIO divisor */
261 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
263 if (priv->phyaddr == -1) {
264 /* Detect the PHY address */
265 for (i = 31; i >= 0; i--) {
266 ret = phyread(priv, i, PHY_DETECT_REG, &phyreg);
267 if (!ret && (phyreg != 0xFFFF) &&
268 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
269 /* Found a valid PHY address */
271 debug("axiemac: Found valid phy address, %x\n",
278 /* Interface - look at tsec */
279 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
281 phydev->supported &= supported;
282 phydev->advertising = phydev->supported;
283 priv->phydev = phydev;
284 if (priv->phy_of_handle)
285 priv->phydev->node = offset_to_ofnode(priv->phy_of_handle);
291 /* Setting axi emac and phy to proper setting */
292 static int setup_phy(struct udevice *dev)
295 u32 speed, emmc_reg, ret;
296 struct axidma_priv *priv = dev_get_priv(dev);
297 struct axi_regs *regs = priv->iobase;
298 struct phy_device *phydev = priv->phydev;
300 if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
302 * In SGMII cases the isolate bit might set
303 * after DMA and ethernet resets and hence
304 * check and clear if set.
306 ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp);
309 if (temp & BMCR_ISOLATE) {
310 temp &= ~BMCR_ISOLATE;
311 ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp);
317 if (phy_startup(phydev)) {
318 printf("axiemac: could not initialize PHY %s\n",
323 printf("%s: No link.\n", phydev->dev->name);
327 switch (phydev->speed) {
329 speed = XAE_EMMC_LINKSPD_1000;
332 speed = XAE_EMMC_LINKSPD_100;
335 speed = XAE_EMMC_LINKSPD_10;
341 /* Setup the emac for the phy speed */
342 emmc_reg = readl(®s->emmc);
343 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
346 /* Write new speed setting out to Axi Ethernet */
347 writel(emmc_reg, ®s->emmc);
350 * Setting the operating speed of the MAC needs a delay. There
351 * doesn't seem to be register to poll, so please consider this
352 * during your application design.
359 /* STOP DMA transfers */
360 static void axiemac_stop(struct udevice *dev)
362 struct axidma_priv *priv = dev_get_priv(dev);
365 /* Stop the hardware */
366 temp = readl(&priv->dmatx->control);
367 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
368 writel(temp, &priv->dmatx->control);
370 temp = readl(&priv->dmarx->control);
371 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
372 writel(temp, &priv->dmarx->control);
374 debug("axiemac: Halted\n");
377 static int axi_ethernet_init(struct axidma_priv *priv)
379 struct axi_regs *regs = priv->iobase;
383 * Check the status of the MgtRdy bit in the interrupt status
384 * registers. This must be done to allow the MGT clock to become stable
385 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
386 * will be valid until this bit is valid.
387 * The bit is always a 1 for all other PHY interfaces.
388 * Interrupt status and enable registers are not available in non
389 * processor mode and hence bypass in this mode
391 if (!priv->eth_hasnobuf) {
392 err = wait_for_bit_le32(®s->is, XAE_INT_MGTRDY_MASK,
395 printf("%s: Timeout\n", __func__);
400 * Stop the device and reset HW
403 writel(0, ®s->ie);
406 /* Disable the receiver */
407 writel(readl(®s->rcw1) & ~XAE_RCW1_RX_MASK, ®s->rcw1);
410 * Stopping the receiver in mid-packet causes a dropped packet
411 * indication from HW. Clear it.
413 if (!priv->eth_hasnobuf) {
414 /* Set the interrupt status register to clear the interrupt */
415 writel(XAE_INT_RXRJECT_MASK, ®s->is);
419 /* Set default MDIO divisor */
420 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
422 debug("axiemac: InitHw done\n");
426 static int axiemac_write_hwaddr(struct udevice *dev)
428 struct eth_pdata *pdata = dev_get_plat(dev);
429 struct axidma_priv *priv = dev_get_priv(dev);
430 struct axi_regs *regs = priv->iobase;
432 /* Set the MAC address */
433 int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
434 (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
435 writel(val, ®s->uaw0);
437 val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
438 val |= readl(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
439 writel(val, ®s->uaw1);
443 /* Reset DMA engine */
444 static void axi_dma_init(struct axidma_priv *priv)
448 /* Reset the engine so the hardware starts from a known state */
449 writel(XAXIDMA_CR_RESET_MASK, &priv->dmatx->control);
450 writel(XAXIDMA_CR_RESET_MASK, &priv->dmarx->control);
452 /* At the initialization time, hardware should finish reset quickly */
454 /* Check transmit/receive channel */
455 /* Reset is done when the reset bit is low */
456 if (!((readl(&priv->dmatx->control) |
457 readl(&priv->dmarx->control))
458 & XAXIDMA_CR_RESET_MASK)) {
463 printf("%s: Timeout\n", __func__);
466 static int axiemac_start(struct udevice *dev)
468 struct axidma_priv *priv = dev_get_priv(dev);
469 struct axi_regs *regs = priv->iobase;
472 debug("axiemac: Init started\n");
474 * Initialize AXIDMA engine. AXIDMA engine must be initialized before
475 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
476 * reset, and since AXIDMA reset line is connected to AxiEthernet, this
477 * would ensure a reset of AxiEthernet.
481 /* Initialize AxiEthernet hardware. */
482 if (axi_ethernet_init(priv))
485 /* Disable all RX interrupts before RxBD space setup */
486 temp = readl(&priv->dmarx->control);
487 temp &= ~XAXIDMA_IRQ_ALL_MASK;
488 writel(temp, &priv->dmarx->control);
490 /* Start DMA RX channel. Now it's ready to receive data.*/
491 axienet_dma_write(&rx_bd, &priv->dmarx->current);
494 memset(&rx_bd, 0, sizeof(rx_bd));
495 rx_bd.next_desc = lower_32_bits((unsigned long)&rx_bd);
496 rx_bd.buf_addr = lower_32_bits((unsigned long)&rxframe);
497 #if defined(CONFIG_PHYS_64BIT)
498 rx_bd.next_desc_msb = upper_32_bits((unsigned long)&rx_bd);
499 rx_bd.buf_addr_msb = upper_32_bits((unsigned long)&rxframe);
501 rx_bd.cntrl = sizeof(rxframe);
502 /* Flush the last BD so DMA core could see the updates */
503 flush_cache((phys_addr_t)&rx_bd, sizeof(rx_bd));
505 /* It is necessary to flush rxframe because if you don't do it
506 * then cache can contain uninitialized data */
507 flush_cache((phys_addr_t)&rxframe, sizeof(rxframe));
509 /* Start the hardware */
510 temp = readl(&priv->dmarx->control);
511 temp |= XAXIDMA_CR_RUNSTOP_MASK;
512 writel(temp, &priv->dmarx->control);
514 /* Rx BD is ready - start */
515 axienet_dma_write(&rx_bd, &priv->dmarx->tail);
518 writel(XAE_TC_TX_MASK, ®s->tc);
520 writel(XAE_RCW1_RX_MASK, ®s->rcw1);
523 if (!setup_phy(dev)) {
528 debug("axiemac: Init complete\n");
532 static int axiemac_send(struct udevice *dev, void *ptr, int len)
534 struct axidma_priv *priv = dev_get_priv(dev);
537 if (len > PKTSIZE_ALIGN)
540 /* Flush packet to main memory to be trasfered by DMA */
541 flush_cache((phys_addr_t)ptr, len);
544 memset(&tx_bd, 0, sizeof(tx_bd));
545 /* At the end of the ring, link the last BD back to the top */
546 tx_bd.next_desc = lower_32_bits((unsigned long)&tx_bd);
547 tx_bd.buf_addr = lower_32_bits((unsigned long)ptr);
548 #if defined(CONFIG_PHYS_64BIT)
549 tx_bd.next_desc_msb = upper_32_bits((unsigned long)&tx_bd);
550 tx_bd.buf_addr_msb = upper_32_bits((unsigned long)ptr);
553 tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
554 XAXIDMA_BD_CTRL_TXEOF_MASK;
556 /* Flush the last BD so DMA core could see the updates */
557 flush_cache((phys_addr_t)&tx_bd, sizeof(tx_bd));
559 if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
561 axienet_dma_write(&tx_bd, &priv->dmatx->current);
562 /* Start the hardware */
563 temp = readl(&priv->dmatx->control);
564 temp |= XAXIDMA_CR_RUNSTOP_MASK;
565 writel(temp, &priv->dmatx->control);
569 axienet_dma_write(&tx_bd, &priv->dmatx->tail);
571 /* Wait for transmission to complete */
572 debug("axiemac: Waiting for tx to be done\n");
574 while (timeout && (!(readl(&priv->dmatx->status) &
575 (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
580 printf("%s: Timeout\n", __func__);
584 debug("axiemac: Sending complete\n");
588 static int isrxready(struct axidma_priv *priv)
592 /* Read pending interrupts */
593 status = readl(&priv->dmarx->status);
595 /* Acknowledge pending interrupts */
596 writel(status & XAXIDMA_IRQ_ALL_MASK, &priv->dmarx->status);
599 * If Reception done interrupt is asserted, call RX call back function
600 * to handle the processed BDs and then raise the according flag.
602 if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
608 static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
611 struct axidma_priv *priv = dev_get_priv(dev);
614 /* Wait for an incoming packet */
615 if (!isrxready(priv))
618 debug("axiemac: RX data ready\n");
620 /* Disable IRQ for a moment till packet is handled */
621 temp = readl(&priv->dmarx->control);
622 temp &= ~XAXIDMA_IRQ_ALL_MASK;
623 writel(temp, &priv->dmarx->control);
624 if (!priv->eth_hasnobuf)
625 length = rx_bd.app4 & 0xFFFF; /* max length mask */
627 length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
630 print_buffer(&rxframe, &rxframe[0], 1, length, 16);
637 static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
639 struct axidma_priv *priv = dev_get_priv(dev);
642 /* It is useful to clear buffer to be sure that it is consistent */
643 memset(rxframe, 0, sizeof(rxframe));
646 /* Clear the whole buffer and setup it again - all flags are cleared */
647 memset(&rx_bd, 0, sizeof(rx_bd));
648 rx_bd.next_desc = lower_32_bits((unsigned long)&rx_bd);
649 rx_bd.buf_addr = lower_32_bits((unsigned long)&rxframe);
650 #if defined(CONFIG_PHYS_64BIT)
651 rx_bd.next_desc_msb = upper_32_bits((unsigned long)&rx_bd);
652 rx_bd.buf_addr_msb = upper_32_bits((unsigned long)&rxframe);
654 rx_bd.cntrl = sizeof(rxframe);
657 flush_cache((phys_addr_t)&rx_bd, sizeof(rx_bd));
659 /* It is necessary to flush rxframe because if you don't do it
660 * then cache will contain previous packet */
661 flush_cache((phys_addr_t)&rxframe, sizeof(rxframe));
663 /* Rx BD is ready - start again */
664 axienet_dma_write(&rx_bd, &priv->dmarx->tail);
666 debug("axiemac: RX completed, framelength = %d\n", length);
671 static int axiemac_miiphy_read(struct mii_dev *bus, int addr,
677 ret = phyread(bus->priv, addr, reg, &value);
678 debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg,
683 static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad,
686 debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
687 return phywrite(bus->priv, addr, reg, value);
690 static int axi_emac_probe(struct udevice *dev)
692 struct axidma_priv *priv = dev_get_priv(dev);
695 priv->bus = mdio_alloc();
696 priv->bus->read = axiemac_miiphy_read;
697 priv->bus->write = axiemac_miiphy_write;
698 priv->bus->priv = priv;
700 ret = mdio_register_seq(priv->bus, dev->seq);
704 axiemac_phy_init(dev);
709 static int axi_emac_remove(struct udevice *dev)
711 struct axidma_priv *priv = dev_get_priv(dev);
714 mdio_unregister(priv->bus);
715 mdio_free(priv->bus);
720 static const struct eth_ops axi_emac_ops = {
721 .start = axiemac_start,
722 .send = axiemac_send,
723 .recv = axiemac_recv,
724 .free_pkt = axiemac_free_pkt,
725 .stop = axiemac_stop,
726 .write_hwaddr = axiemac_write_hwaddr,
729 static int axi_emac_ofdata_to_platdata(struct udevice *dev)
731 struct eth_pdata *pdata = dev_get_plat(dev);
732 struct axidma_priv *priv = dev_get_priv(dev);
733 int node = dev_of_offset(dev);
735 const char *phy_mode;
737 pdata->iobase = dev_read_addr(dev);
738 priv->iobase = (struct axi_regs *)pdata->iobase;
740 offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
741 "axistream-connected");
743 printf("%s: axistream is not found\n", __func__);
746 priv->dmatx = (struct axidma_reg *)fdtdec_get_addr(gd->fdt_blob,
749 printf("%s: axi_dma register space not found\n", __func__);
752 /* RX channel offset is 0x30 */
753 priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30);
757 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
759 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
760 priv->phy_of_handle = offset;
763 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
765 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
766 if (pdata->phy_interface == -1) {
767 printf("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
770 priv->interface = pdata->phy_interface;
772 priv->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
773 "xlnx,eth-hasnobuf");
775 printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase,
776 priv->phyaddr, phy_string_for_interface(priv->interface));
781 static const struct udevice_id axi_emac_ids[] = {
782 { .compatible = "xlnx,axi-ethernet-1.00.a" },
786 U_BOOT_DRIVER(axi_emac) = {
789 .of_match = axi_emac_ids,
790 .ofdata_to_platdata = axi_emac_ofdata_to_platdata,
791 .probe = axi_emac_probe,
792 .remove = axi_emac_remove,
793 .ops = &axi_emac_ops,
794 .priv_auto = sizeof(struct axidma_priv),
795 .plat_auto = sizeof(struct eth_pdata),