1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2021 Waymo LLC
4 * Copyright (C) 2011 Michal Simek <monstr@monstr.eu>
5 * Copyright (C) 2011 PetaLogix
6 * Copyright (C) 2010 Xilinx, Inc. All rights reserved.
16 #include <asm/global_data.h>
21 #include <linux/delay.h>
24 DECLARE_GLOBAL_DATA_PTR;
27 #define XAE_EMMC_LINKSPEED_MASK 0xC0000000 /* Link speed */
28 #define XAE_EMMC_LINKSPD_10 0x00000000 /* Link Speed mask for 10 Mbit */
29 #define XAE_EMMC_LINKSPD_100 0x40000000 /* Link Speed mask for 100 Mbit */
30 #define XAE_EMMC_LINKSPD_1000 0x80000000 /* Link Speed mask for 1000 Mbit */
32 /* Interrupt Status/Enable/Mask Registers bit definitions */
33 #define XAE_INT_RXRJECT_MASK 0x00000008 /* Rx frame rejected */
34 #define XAE_INT_MGTRDY_MASK 0x00000080 /* MGT clock Lock */
36 /* Receive Configuration Word 1 (RCW1) Register bit definitions */
37 #define XAE_RCW1_RX_MASK 0x10000000 /* Receiver enable */
39 /* Transmitter Configuration (TC) Register bit definitions */
40 #define XAE_TC_TX_MASK 0x10000000 /* Transmitter enable */
42 #define XAE_UAW1_UNICASTADDR_MASK 0x0000FFFF
44 /* MDIO Management Configuration (MC) Register bit definitions */
45 #define XAE_MDIO_MC_MDIOEN_MASK 0x00000040 /* MII management enable*/
47 /* MDIO Management Control Register (MCR) Register bit definitions */
48 #define XAE_MDIO_MCR_PHYAD_MASK 0x1F000000 /* Phy Address Mask */
49 #define XAE_MDIO_MCR_PHYAD_SHIFT 24 /* Phy Address Shift */
50 #define XAE_MDIO_MCR_REGAD_MASK 0x001F0000 /* Reg Address Mask */
51 #define XAE_MDIO_MCR_REGAD_SHIFT 16 /* Reg Address Shift */
52 #define XAE_MDIO_MCR_OP_READ_MASK 0x00008000 /* Op Code Read Mask */
53 #define XAE_MDIO_MCR_OP_WRITE_MASK 0x00004000 /* Op Code Write Mask */
54 #define XAE_MDIO_MCR_INITIATE_MASK 0x00000800 /* Ready Mask */
55 #define XAE_MDIO_MCR_READY_MASK 0x00000080 /* Ready Mask */
57 #define XAE_MDIO_DIV_DFT 29 /* Default MDIO clock divisor */
59 #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK 0x007FFFFF /* Actual len */
62 /* Bitmasks of XAXIDMA_CR_OFFSET register */
63 #define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /* Start/stop DMA channel */
64 #define XAXIDMA_CR_RESET_MASK 0x00000004 /* Reset DMA engine */
66 /* Bitmasks of XAXIDMA_SR_OFFSET register */
67 #define XAXIDMA_HALTED_MASK 0x00000001 /* DMA channel halted */
69 /* Bitmask for interrupts */
70 #define XAXIDMA_IRQ_IOC_MASK 0x00001000 /* Completion intr */
71 #define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /* Delay interrupt */
72 #define XAXIDMA_IRQ_ALL_MASK 0x00007000 /* All interrupts */
74 /* Bitmasks of XAXIDMA_BD_CTRL_OFFSET register */
75 #define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /* First tx packet */
76 #define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /* Last tx packet */
78 /* Bitmasks for XXV Ethernet MAC */
79 #define XXV_TC_TX_MASK 0x00000001
80 #define XXV_TC_FCS_MASK 0x00000002
81 #define XXV_RCW1_RX_MASK 0x00000001
82 #define XXV_RCW1_FCS_MASK 0x00000002
85 #define XXV_MIN_PKT_SIZE 60
87 static u8 rxframe[PKTSIZE_ALIGN] __attribute((aligned(DMAALIGN)));
88 static u8 txminframe[XXV_MIN_PKT_SIZE] __attribute((aligned(DMAALIGN)));
95 /* Reflect dma offsets */
97 u32 control; /* DMACR */
98 u32 status; /* DMASR */
99 u32 current; /* CURDESC low 32 bit */
100 u32 current_hi; /* CURDESC high 32 bit */
101 u32 tail; /* TAILDESC low 32 bit */
102 u32 tail_hi; /* TAILDESC high 32 bit */
105 /* Platform data structures */
107 struct eth_pdata eth_pdata;
108 struct axidma_reg *dmatx;
109 struct axidma_reg *dmarx;
113 enum emac_variant mactype;
116 /* Private driver structures */
118 struct axidma_reg *dmatx;
119 struct axidma_reg *dmarx;
121 struct axi_regs *iobase;
122 phy_interface_t interface;
123 struct phy_device *phydev;
127 enum emac_variant mactype;
132 u32 next_desc; /* Next descriptor pointer */
134 u32 buf_addr; /* Buffer address */
138 u32 cntrl; /* Control */
139 u32 status; /* Status */
141 u32 app1; /* TX start << 16 | insert */
142 u32 app2; /* TX csum seed */
150 /* Static BDs - driver uses only one BD */
151 static struct axidma_bd tx_bd __attribute((aligned(DMAALIGN)));
152 static struct axidma_bd rx_bd __attribute((aligned(DMAALIGN)));
156 u32 is; /* 0xC: Interrupt status */
158 u32 ie; /* 0x14: Interrupt enable */
160 u32 rcw1; /* 0x404: Rx Configuration Word 1 */
161 u32 tc; /* 0x408: Tx Configuration */
163 u32 emmc; /* 0x410: EMAC mode configuration */
165 u32 mdio_mc; /* 0x500: MII Management Config */
166 u32 mdio_mcr; /* 0x504: MII Management Control */
167 u32 mdio_mwd; /* 0x508: MII Management Write Data */
168 u32 mdio_mrd; /* 0x50C: MII Management Read Data */
170 u32 uaw0; /* 0x700: Unicast address word 0 */
171 u32 uaw1; /* 0x704: Unicast address word 1 */
174 struct xxv_axi_regs {
175 u32 gt_reset; /* 0x0 */
177 u32 tc; /* 0xC: Tx Configuration */
179 u32 rcw1; /* 0x14: Rx Configuration Word 1 */
182 /* Use MII register 1 (MII status register) to detect PHY */
183 #define PHY_DETECT_REG 1
186 * Mask used to verify certain PHY features (or register contents)
187 * in the register above:
188 * 0x1000: 10Mbps full duplex support
189 * 0x0800: 10Mbps half duplex support
190 * 0x0008: Auto-negotiation support
192 #define PHY_DETECT_MASK 0x1808
194 static inline int mdio_wait(struct axi_regs *regs)
198 /* Wait till MDIO interface is ready to accept a new transaction. */
199 while (timeout && (!(readl(®s->mdio_mcr)
200 & XAE_MDIO_MCR_READY_MASK))) {
205 printf("%s: Timeout\n", __func__);
212 * axienet_dma_write - Memory mapped Axi DMA register Buffer Descriptor write.
213 * @bd: pointer to BD descriptor structure
214 * @desc: Address offset of DMA descriptors
216 * This function writes the value into the corresponding Axi DMA register.
218 static inline void axienet_dma_write(struct axidma_bd *bd, u32 *desc)
220 #if defined(CONFIG_PHYS_64BIT)
221 writeq((unsigned long)bd, desc);
223 writel((u32)bd, desc);
227 static u32 phyread(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
230 struct axi_regs *regs = priv->iobase;
236 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
237 XAE_MDIO_MCR_PHYAD_MASK) |
238 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
239 & XAE_MDIO_MCR_REGAD_MASK) |
240 XAE_MDIO_MCR_INITIATE_MASK |
241 XAE_MDIO_MCR_OP_READ_MASK;
243 writel(mdioctrlreg, ®s->mdio_mcr);
249 *val = readl(®s->mdio_mrd);
253 static u32 phywrite(struct axidma_priv *priv, u32 phyaddress, u32 registernum,
256 struct axi_regs *regs = priv->iobase;
262 mdioctrlreg = ((phyaddress << XAE_MDIO_MCR_PHYAD_SHIFT) &
263 XAE_MDIO_MCR_PHYAD_MASK) |
264 ((registernum << XAE_MDIO_MCR_REGAD_SHIFT)
265 & XAE_MDIO_MCR_REGAD_MASK) |
266 XAE_MDIO_MCR_INITIATE_MASK |
267 XAE_MDIO_MCR_OP_WRITE_MASK;
270 writel(data, ®s->mdio_mwd);
272 writel(mdioctrlreg, ®s->mdio_mcr);
280 static int axiemac_phy_init(struct udevice *dev)
285 struct axidma_priv *priv = dev_get_priv(dev);
286 struct axi_regs *regs = priv->iobase;
287 struct phy_device *phydev;
289 u32 supported = SUPPORTED_10baseT_Half |
290 SUPPORTED_10baseT_Full |
291 SUPPORTED_100baseT_Half |
292 SUPPORTED_100baseT_Full |
293 SUPPORTED_1000baseT_Half |
294 SUPPORTED_1000baseT_Full;
296 /* Set default MDIO divisor */
297 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
299 if (IS_ENABLED(CONFIG_DM_ETH_PHY))
300 priv->phyaddr = eth_phy_get_addr(dev);
302 if (priv->phyaddr == -1) {
303 /* Detect the PHY address */
304 for (i = 31; i >= 0; i--) {
305 ret = phyread(priv, i, PHY_DETECT_REG, &phyreg);
306 if (!ret && (phyreg != 0xFFFF) &&
307 ((phyreg & PHY_DETECT_MASK) == PHY_DETECT_MASK)) {
308 /* Found a valid PHY address */
310 debug("axiemac: Found valid phy address, %x\n",
317 /* Interface - look at tsec */
318 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
320 phydev->supported &= supported;
321 phydev->advertising = phydev->supported;
322 priv->phydev = phydev;
323 if (priv->phy_of_handle)
324 priv->phydev->node = offset_to_ofnode(priv->phy_of_handle);
330 /* Setting axi emac and phy to proper setting */
331 static int setup_phy(struct udevice *dev)
334 u32 speed, emmc_reg, ret;
335 struct axidma_priv *priv = dev_get_priv(dev);
336 struct axi_regs *regs = priv->iobase;
337 struct phy_device *phydev = priv->phydev;
339 if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
341 * In SGMII cases the isolate bit might set
342 * after DMA and ethernet resets and hence
343 * check and clear if set.
345 ret = phyread(priv, priv->phyaddr, MII_BMCR, &temp);
348 if (temp & BMCR_ISOLATE) {
349 temp &= ~BMCR_ISOLATE;
350 ret = phywrite(priv, priv->phyaddr, MII_BMCR, temp);
356 if (phy_startup(phydev)) {
357 printf("axiemac: could not initialize PHY %s\n",
362 printf("%s: No link.\n", phydev->dev->name);
366 switch (phydev->speed) {
368 speed = XAE_EMMC_LINKSPD_1000;
371 speed = XAE_EMMC_LINKSPD_100;
374 speed = XAE_EMMC_LINKSPD_10;
380 /* Setup the emac for the phy speed */
381 emmc_reg = readl(®s->emmc);
382 emmc_reg &= ~XAE_EMMC_LINKSPEED_MASK;
385 /* Write new speed setting out to Axi Ethernet */
386 writel(emmc_reg, ®s->emmc);
389 * Setting the operating speed of the MAC needs a delay. There
390 * doesn't seem to be register to poll, so please consider this
391 * during your application design.
398 /* STOP DMA transfers */
399 static void axiemac_stop(struct udevice *dev)
401 struct axidma_priv *priv = dev_get_priv(dev);
404 /* Stop the hardware */
405 temp = readl(&priv->dmatx->control);
406 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
407 writel(temp, &priv->dmatx->control);
409 temp = readl(&priv->dmarx->control);
410 temp &= ~XAXIDMA_CR_RUNSTOP_MASK;
411 writel(temp, &priv->dmarx->control);
413 debug("axiemac: Halted\n");
416 static int xxv_axi_ethernet_init(struct axidma_priv *priv)
418 struct xxv_axi_regs *regs = (struct xxv_axi_regs *)priv->iobase;
420 writel(readl(®s->rcw1) | XXV_RCW1_FCS_MASK, ®s->rcw1);
421 writel(readl(®s->tc) | XXV_TC_FCS_MASK, ®s->tc);
422 writel(readl(®s->tc) | XXV_TC_TX_MASK, ®s->tc);
423 writel(readl(®s->rcw1) | XXV_RCW1_RX_MASK, ®s->rcw1);
428 static int axi_ethernet_init(struct axidma_priv *priv)
430 struct axi_regs *regs = priv->iobase;
434 * Check the status of the MgtRdy bit in the interrupt status
435 * registers. This must be done to allow the MGT clock to become stable
436 * for the Sgmii and 1000BaseX PHY interfaces. No other register reads
437 * will be valid until this bit is valid.
438 * The bit is always a 1 for all other PHY interfaces.
439 * Interrupt status and enable registers are not available in non
440 * processor mode and hence bypass in this mode
442 if (!priv->eth_hasnobuf) {
443 err = wait_for_bit_le32(®s->is, XAE_INT_MGTRDY_MASK,
446 printf("%s: Timeout\n", __func__);
451 * Stop the device and reset HW
454 writel(0, ®s->ie);
457 /* Disable the receiver */
458 writel(readl(®s->rcw1) & ~XAE_RCW1_RX_MASK, ®s->rcw1);
461 * Stopping the receiver in mid-packet causes a dropped packet
462 * indication from HW. Clear it.
464 if (!priv->eth_hasnobuf) {
465 /* Set the interrupt status register to clear the interrupt */
466 writel(XAE_INT_RXRJECT_MASK, ®s->is);
470 /* Set default MDIO divisor */
471 writel(XAE_MDIO_DIV_DFT | XAE_MDIO_MC_MDIOEN_MASK, ®s->mdio_mc);
473 debug("axiemac: InitHw done\n");
477 static int axiemac_write_hwaddr(struct udevice *dev)
479 struct eth_pdata *pdata = dev_get_plat(dev);
480 struct axidma_priv *priv = dev_get_priv(dev);
481 struct axi_regs *regs = priv->iobase;
483 if (priv->mactype != EMAC_1G)
486 /* Set the MAC address */
487 int val = ((pdata->enetaddr[3] << 24) | (pdata->enetaddr[2] << 16) |
488 (pdata->enetaddr[1] << 8) | (pdata->enetaddr[0]));
489 writel(val, ®s->uaw0);
491 val = (pdata->enetaddr[5] << 8) | pdata->enetaddr[4];
492 val |= readl(®s->uaw1) & ~XAE_UAW1_UNICASTADDR_MASK;
493 writel(val, ®s->uaw1);
497 /* Reset DMA engine */
498 static void axi_dma_init(struct axidma_priv *priv)
502 /* Reset the engine so the hardware starts from a known state */
503 writel(XAXIDMA_CR_RESET_MASK, &priv->dmatx->control);
504 writel(XAXIDMA_CR_RESET_MASK, &priv->dmarx->control);
506 /* At the initialization time, hardware should finish reset quickly */
508 /* Check transmit/receive channel */
509 /* Reset is done when the reset bit is low */
510 if (!((readl(&priv->dmatx->control) |
511 readl(&priv->dmarx->control))
512 & XAXIDMA_CR_RESET_MASK)) {
517 printf("%s: Timeout\n", __func__);
520 static int axiemac_start(struct udevice *dev)
522 struct axidma_priv *priv = dev_get_priv(dev);
525 debug("axiemac: Init started\n");
527 * Initialize AXIDMA engine. AXIDMA engine must be initialized before
528 * AxiEthernet. During AXIDMA engine initialization, AXIDMA hardware is
529 * reset, and since AXIDMA reset line is connected to AxiEthernet, this
530 * would ensure a reset of AxiEthernet.
534 /* Initialize AxiEthernet hardware. */
535 if (priv->mactype == EMAC_1G) {
536 if (axi_ethernet_init(priv))
539 if (xxv_axi_ethernet_init(priv))
543 /* Disable all RX interrupts before RxBD space setup */
544 temp = readl(&priv->dmarx->control);
545 temp &= ~XAXIDMA_IRQ_ALL_MASK;
546 writel(temp, &priv->dmarx->control);
548 /* Start DMA RX channel. Now it's ready to receive data.*/
549 axienet_dma_write(&rx_bd, &priv->dmarx->current);
552 memset(&rx_bd, 0, sizeof(rx_bd));
553 rx_bd.next_desc = lower_32_bits((unsigned long)&rx_bd);
554 rx_bd.buf_addr = lower_32_bits((unsigned long)&rxframe);
555 #if defined(CONFIG_PHYS_64BIT)
556 rx_bd.next_desc_msb = upper_32_bits((unsigned long)&rx_bd);
557 rx_bd.buf_addr_msb = upper_32_bits((unsigned long)&rxframe);
559 rx_bd.cntrl = sizeof(rxframe);
560 /* Flush the last BD so DMA core could see the updates */
561 flush_cache((phys_addr_t)&rx_bd, sizeof(rx_bd));
563 /* It is necessary to flush rxframe because if you don't do it
564 * then cache can contain uninitialized data */
565 flush_cache((phys_addr_t)&rxframe, sizeof(rxframe));
567 /* Start the hardware */
568 temp = readl(&priv->dmarx->control);
569 temp |= XAXIDMA_CR_RUNSTOP_MASK;
570 writel(temp, &priv->dmarx->control);
572 /* Rx BD is ready - start */
573 axienet_dma_write(&rx_bd, &priv->dmarx->tail);
575 if (priv->mactype == EMAC_1G) {
576 struct axi_regs *regs = priv->iobase;
578 writel(XAE_TC_TX_MASK, ®s->tc);
580 writel(XAE_RCW1_RX_MASK, ®s->rcw1);
583 if (!setup_phy(dev)) {
588 struct xxv_axi_regs *regs = (struct xxv_axi_regs *)priv->iobase;
590 writel(readl(®s->tc) | XXV_TC_TX_MASK, ®s->tc);
593 writel(readl(®s->rcw1) | XXV_RCW1_RX_MASK, ®s->rcw1);
596 debug("axiemac: Init complete\n");
600 static int axiemac_send(struct udevice *dev, void *ptr, int len)
602 struct axidma_priv *priv = dev_get_priv(dev);
605 if (len > PKTSIZE_ALIGN)
608 /* If size is less than min packet size, pad to min size */
609 if (priv->mactype == EMAC_10G_25G && len < XXV_MIN_PKT_SIZE) {
610 memset(txminframe, 0, XXV_MIN_PKT_SIZE);
611 memcpy(txminframe, ptr, len);
612 len = XXV_MIN_PKT_SIZE;
616 /* Flush packet to main memory to be trasfered by DMA */
617 flush_cache((phys_addr_t)ptr, len);
620 memset(&tx_bd, 0, sizeof(tx_bd));
621 /* At the end of the ring, link the last BD back to the top */
622 tx_bd.next_desc = lower_32_bits((unsigned long)&tx_bd);
623 tx_bd.buf_addr = lower_32_bits((unsigned long)ptr);
624 #if defined(CONFIG_PHYS_64BIT)
625 tx_bd.next_desc_msb = upper_32_bits((unsigned long)&tx_bd);
626 tx_bd.buf_addr_msb = upper_32_bits((unsigned long)ptr);
629 tx_bd.cntrl = len | XAXIDMA_BD_CTRL_TXSOF_MASK |
630 XAXIDMA_BD_CTRL_TXEOF_MASK;
632 /* Flush the last BD so DMA core could see the updates */
633 flush_cache((phys_addr_t)&tx_bd, sizeof(tx_bd));
635 if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
637 axienet_dma_write(&tx_bd, &priv->dmatx->current);
638 /* Start the hardware */
639 temp = readl(&priv->dmatx->control);
640 temp |= XAXIDMA_CR_RUNSTOP_MASK;
641 writel(temp, &priv->dmatx->control);
645 axienet_dma_write(&tx_bd, &priv->dmatx->tail);
647 /* Wait for transmission to complete */
648 debug("axiemac: Waiting for tx to be done\n");
650 while (timeout && (!(readl(&priv->dmatx->status) &
651 (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))) {
656 printf("%s: Timeout\n", __func__);
660 debug("axiemac: Sending complete\n");
664 static int isrxready(struct axidma_priv *priv)
668 /* Read pending interrupts */
669 status = readl(&priv->dmarx->status);
671 /* Acknowledge pending interrupts */
672 writel(status & XAXIDMA_IRQ_ALL_MASK, &priv->dmarx->status);
675 * If Reception done interrupt is asserted, call RX call back function
676 * to handle the processed BDs and then raise the according flag.
678 if ((status & (XAXIDMA_IRQ_DELAY_MASK | XAXIDMA_IRQ_IOC_MASK)))
684 static int axiemac_recv(struct udevice *dev, int flags, uchar **packetp)
687 struct axidma_priv *priv = dev_get_priv(dev);
690 /* Wait for an incoming packet */
691 if (!isrxready(priv))
694 debug("axiemac: RX data ready\n");
696 /* Disable IRQ for a moment till packet is handled */
697 temp = readl(&priv->dmarx->control);
698 temp &= ~XAXIDMA_IRQ_ALL_MASK;
699 writel(temp, &priv->dmarx->control);
700 if (!priv->eth_hasnobuf && priv->mactype == EMAC_1G)
701 length = rx_bd.app4 & 0xFFFF; /* max length mask */
703 length = rx_bd.status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
706 print_buffer(&rxframe, &rxframe[0], 1, length, 16);
713 static int axiemac_free_pkt(struct udevice *dev, uchar *packet, int length)
715 struct axidma_priv *priv = dev_get_priv(dev);
718 /* It is useful to clear buffer to be sure that it is consistent */
719 memset(rxframe, 0, sizeof(rxframe));
722 /* Clear the whole buffer and setup it again - all flags are cleared */
723 memset(&rx_bd, 0, sizeof(rx_bd));
724 rx_bd.next_desc = lower_32_bits((unsigned long)&rx_bd);
725 rx_bd.buf_addr = lower_32_bits((unsigned long)&rxframe);
726 #if defined(CONFIG_PHYS_64BIT)
727 rx_bd.next_desc_msb = upper_32_bits((unsigned long)&rx_bd);
728 rx_bd.buf_addr_msb = upper_32_bits((unsigned long)&rxframe);
730 rx_bd.cntrl = sizeof(rxframe);
733 flush_cache((phys_addr_t)&rx_bd, sizeof(rx_bd));
735 /* It is necessary to flush rxframe because if you don't do it
736 * then cache will contain previous packet */
737 flush_cache((phys_addr_t)&rxframe, sizeof(rxframe));
739 /* Rx BD is ready - start again */
740 axienet_dma_write(&rx_bd, &priv->dmarx->tail);
742 debug("axiemac: RX completed, framelength = %d\n", length);
747 static int axiemac_miiphy_read(struct mii_dev *bus, int addr,
753 ret = phyread(bus->priv, addr, reg, &value);
754 debug("axiemac: Read MII 0x%x, 0x%x, 0x%x, %d\n", addr, reg,
759 static int axiemac_miiphy_write(struct mii_dev *bus, int addr, int devad,
762 debug("axiemac: Write MII 0x%x, 0x%x, 0x%x\n", addr, reg, value);
763 return phywrite(bus->priv, addr, reg, value);
766 static int axi_emac_probe(struct udevice *dev)
768 struct axidma_plat *plat = dev_get_plat(dev);
769 struct eth_pdata *pdata = &plat->eth_pdata;
770 struct axidma_priv *priv = dev_get_priv(dev);
773 priv->iobase = (struct axi_regs *)pdata->iobase;
774 priv->dmatx = plat->dmatx;
775 /* RX channel offset is 0x30 */
776 priv->dmarx = (struct axidma_reg *)((phys_addr_t)priv->dmatx + 0x30);
777 priv->mactype = plat->mactype;
779 if (priv->mactype == EMAC_1G) {
780 priv->eth_hasnobuf = plat->eth_hasnobuf;
781 priv->phyaddr = plat->phyaddr;
782 priv->phy_of_handle = plat->phy_of_handle;
783 priv->interface = pdata->phy_interface;
785 if (IS_ENABLED(CONFIG_DM_ETH_PHY))
786 priv->bus = eth_phy_get_mdio_bus(dev);
789 priv->bus = mdio_alloc();
790 priv->bus->read = axiemac_miiphy_read;
791 priv->bus->write = axiemac_miiphy_write;
792 priv->bus->priv = priv;
794 ret = mdio_register_seq(priv->bus, dev_seq(dev));
799 if (IS_ENABLED(CONFIG_DM_ETH_PHY))
800 eth_phy_set_mdio_bus(dev, priv->bus);
802 axiemac_phy_init(dev);
805 printf("AXI EMAC: %lx, phyaddr %d, interface %s\n", (ulong)pdata->iobase,
806 priv->phyaddr, phy_string_for_interface(pdata->phy_interface));
811 static int axi_emac_remove(struct udevice *dev)
813 struct axidma_priv *priv = dev_get_priv(dev);
815 if (priv->mactype == EMAC_1G) {
817 mdio_unregister(priv->bus);
818 mdio_free(priv->bus);
824 static const struct eth_ops axi_emac_ops = {
825 .start = axiemac_start,
826 .send = axiemac_send,
827 .recv = axiemac_recv,
828 .free_pkt = axiemac_free_pkt,
829 .stop = axiemac_stop,
830 .write_hwaddr = axiemac_write_hwaddr,
833 static int axi_emac_of_to_plat(struct udevice *dev)
835 struct axidma_plat *plat = dev_get_plat(dev);
836 struct eth_pdata *pdata = &plat->eth_pdata;
837 int node = dev_of_offset(dev);
840 pdata->iobase = dev_read_addr(dev);
841 plat->mactype = dev_get_driver_data(dev);
843 offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
844 "axistream-connected");
846 printf("%s: axistream is not found\n", __func__);
849 plat->dmatx = (struct axidma_reg *)fdtdec_get_addr_size_auto_parent
850 (gd->fdt_blob, 0, offset, "reg", 0, NULL, false);
852 printf("%s: axi_dma register space not found\n", __func__);
856 if (plat->mactype == EMAC_1G) {
859 offset = fdtdec_lookup_phandle(gd->fdt_blob, node,
862 if (!(IS_ENABLED(CONFIG_DM_ETH_PHY)))
863 plat->phyaddr = fdtdec_get_int(gd->fdt_blob,
866 plat->phy_of_handle = offset;
869 pdata->phy_interface = dev_read_phy_mode(dev);
870 if (pdata->phy_interface == PHY_INTERFACE_MODE_NA)
873 plat->eth_hasnobuf = fdtdec_get_bool(gd->fdt_blob, node,
874 "xlnx,eth-hasnobuf");
880 static const struct udevice_id axi_emac_ids[] = {
881 { .compatible = "xlnx,axi-ethernet-1.00.a", .data = (uintptr_t)EMAC_1G },
882 { .compatible = "xlnx,xxv-ethernet-1.0", .data = (uintptr_t)EMAC_10G_25G },
886 U_BOOT_DRIVER(axi_emac) = {
889 .of_match = axi_emac_ids,
890 .of_to_plat = axi_emac_of_to_plat,
891 .probe = axi_emac_probe,
892 .remove = axi_emac_remove,
893 .ops = &axi_emac_ops,
894 .priv_auto = sizeof(struct axidma_priv),
895 .plat_auto = sizeof(struct axidma_plat),