2 * This file is part of wl1271
4 * Copyright (C) 2008-2010 Nokia Corporation
6 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/gpio.h>
25 #include <linux/slab.h>
27 #include "wl1271_acx.h"
28 #include "wl1271_reg.h"
29 #include "wl1271_boot.h"
30 #include "wl1271_io.h"
31 #include "wl1271_event.h"
33 static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
40 .start = REGISTERS_BASE,
59 .start = REGISTERS_BASE,
92 static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
96 /* 10.5.0 run the firmware (I) */
97 cpu_ctrl = wl1271_read32(wl, ACX_REG_ECPU_CONTROL);
99 /* 10.5.1 run the firmware (II) */
101 wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
104 static void wl1271_boot_fw_version(struct wl1271 *wl)
106 struct wl1271_static_data static_data;
108 wl1271_read(wl, wl->cmd_box_addr, &static_data, sizeof(static_data),
111 strncpy(wl->chip.fw_ver, static_data.fw_version,
112 sizeof(wl->chip.fw_ver));
114 /* make sure the string is NULL-terminated */
115 wl->chip.fw_ver[sizeof(wl->chip.fw_ver) - 1] = '\0';
118 static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
119 size_t fw_data_len, u32 dest)
121 struct wl1271_partition_set partition;
122 int addr, chunk_num, partition_limit;
125 /* whal_FwCtrl_LoadFwImageSm() */
127 wl1271_debug(DEBUG_BOOT, "starting firmware upload");
129 wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
130 fw_data_len, CHUNK_SIZE);
132 if ((fw_data_len % 4) != 0) {
133 wl1271_error("firmware length not multiple of four");
137 chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
139 wl1271_error("allocation for firmware upload chunk failed");
143 memcpy(&partition, &part_table[PART_DOWN], sizeof(partition));
144 partition.mem.start = dest;
145 wl1271_set_partition(wl, &partition);
147 /* 10.1 set partition limit and chunk num */
149 partition_limit = part_table[PART_DOWN].mem.size;
151 while (chunk_num < fw_data_len / CHUNK_SIZE) {
152 /* 10.2 update partition, if needed */
153 addr = dest + (chunk_num + 2) * CHUNK_SIZE;
154 if (addr > partition_limit) {
155 addr = dest + chunk_num * CHUNK_SIZE;
156 partition_limit = chunk_num * CHUNK_SIZE +
157 part_table[PART_DOWN].mem.size;
158 partition.mem.start = addr;
159 wl1271_set_partition(wl, &partition);
162 /* 10.3 upload the chunk */
163 addr = dest + chunk_num * CHUNK_SIZE;
164 p = buf + chunk_num * CHUNK_SIZE;
165 memcpy(chunk, p, CHUNK_SIZE);
166 wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
168 wl1271_write(wl, addr, chunk, CHUNK_SIZE, false);
173 /* 10.4 upload the last chunk */
174 addr = dest + chunk_num * CHUNK_SIZE;
175 p = buf + chunk_num * CHUNK_SIZE;
176 memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
177 wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
178 fw_data_len % CHUNK_SIZE, p, addr);
179 wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
185 static int wl1271_boot_upload_firmware(struct wl1271 *wl)
187 u32 chunks, addr, len;
192 chunks = be32_to_cpup((__be32 *) fw);
195 wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);
198 addr = be32_to_cpup((__be32 *) fw);
200 len = be32_to_cpup((__be32 *) fw);
204 wl1271_info("firmware chunk too long: %u", len);
207 wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
209 ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
218 static int wl1271_boot_upload_nvs(struct wl1271 *wl)
220 size_t nvs_len, burst_len;
223 u8 *nvs_ptr, *nvs_aligned;
228 /* only the first part of the NVS needs to be uploaded */
229 nvs_len = sizeof(wl->nvs->nvs);
230 nvs_ptr = (u8 *)wl->nvs->nvs;
232 /* update current MAC address to NVS */
233 nvs_ptr[11] = wl->mac_addr[0];
234 nvs_ptr[10] = wl->mac_addr[1];
235 nvs_ptr[6] = wl->mac_addr[2];
236 nvs_ptr[5] = wl->mac_addr[3];
237 nvs_ptr[4] = wl->mac_addr[4];
238 nvs_ptr[3] = wl->mac_addr[5];
241 * Layout before the actual NVS tables:
242 * 1 byte : burst length.
243 * 2 bytes: destination address.
244 * n bytes: data to burst copy.
246 * This is ended by a 0 length, then the NVS tables.
249 /* FIXME: Do we need to check here whether the LSB is 1? */
251 burst_len = nvs_ptr[0];
252 dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
254 /* FIXME: Due to our new wl1271_translate_reg_addr function,
255 we need to add the REGISTER_BASE to the destination */
256 dest_addr += REGISTERS_BASE;
258 /* We move our pointer to the data */
261 for (i = 0; i < burst_len; i++) {
262 val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
263 | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
265 wl1271_debug(DEBUG_BOOT,
266 "nvs burst write 0x%x: 0x%x",
268 wl1271_write32(wl, dest_addr, val);
276 * We've reached the first zero length, the first NVS table
277 * is 7 bytes further.
280 nvs_len -= nvs_ptr - (u8 *)wl->nvs->nvs;
281 nvs_len = ALIGN(nvs_len, 4);
283 /* FIXME: The driver sets the partition here, but this is not needed,
284 since it sets to the same one as currently in use */
285 /* Now we must set the partition correctly */
286 wl1271_set_partition(wl, &part_table[PART_WORK]);
288 /* Copy the NVS tables to a new block to ensure alignment */
289 /* FIXME: We jump 3 more bytes before uploading the NVS. It seems
290 that our NVS files have three extra zeros here. I'm not sure whether
291 the problem is in our NVS generation or we should really jumpt these
295 nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL); if
296 (!nvs_aligned) return -ENOMEM;
298 /* And finally we upload the NVS tables */
299 /* FIXME: In wl1271, we upload everything at once.
300 No endianness handling needed here?! The ref driver doesn't do
301 anything about it at this point */
302 wl1271_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);
308 static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
310 wl1271_enable_interrupts(wl);
311 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
312 WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
313 wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
316 static int wl1271_boot_soft_reset(struct wl1271 *wl)
318 unsigned long timeout;
321 /* perform soft reset */
322 wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
324 /* SOFT_RESET is self clearing */
325 timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
327 boot_data = wl1271_read32(wl, ACX_REG_SLV_SOFT_RESET);
328 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
329 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
332 if (time_after(jiffies, timeout)) {
333 /* 1.2 check pWhalBus->uSelfClearTime if the
334 * timeout was reached */
335 wl1271_error("soft reset timeout");
339 udelay(SOFT_RESET_STALL_TIME);
343 wl1271_write32(wl, ENABLE, 0x0);
345 /* disable auto calibration on start*/
346 wl1271_write32(wl, SPARE_A2, 0xffff);
351 static int wl1271_boot_run_firmware(struct wl1271 *wl)
356 wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
358 chip_id = wl1271_read32(wl, CHIP_ID_B);
360 wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
362 if (chip_id != wl->chip.id) {
363 wl1271_error("chip id doesn't match after firmware boot");
367 /* wait for init to complete */
369 while (loop++ < INIT_LOOP) {
370 udelay(INIT_LOOP_DELAY);
371 intr = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
373 if (intr == 0xffffffff) {
374 wl1271_error("error reading hardware complete "
378 /* check that ACX_INTR_INIT_COMPLETE is enabled */
379 else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) {
380 wl1271_write32(wl, ACX_REG_INTERRUPT_ACK,
381 WL1271_ACX_INTR_INIT_COMPLETE);
386 if (loop > INIT_LOOP) {
387 wl1271_error("timeout waiting for the hardware to "
388 "complete initialization");
392 /* get hardware config command mail box */
393 wl->cmd_box_addr = wl1271_read32(wl, REG_COMMAND_MAILBOX_PTR);
395 /* get hardware config event mail box */
396 wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR);
398 /* set the working partition to its "running" mode offset */
399 wl1271_set_partition(wl, &part_table[PART_WORK]);
401 wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
402 wl->cmd_box_addr, wl->event_box_addr);
404 wl1271_boot_fw_version(wl);
407 * in case of full asynchronous mode the firmware event must be
408 * ready to receive event from the command mailbox
411 /* unmask required mbox events */
412 wl->event_mask = BSS_LOSE_EVENT_ID |
413 SCAN_COMPLETE_EVENT_ID |
415 JOIN_EVENT_COMPLETE_ID |
416 DISCONNECT_EVENT_COMPLETE_ID |
417 RSSI_SNR_TRIGGER_0_EVENT_ID |
418 PSPOLL_DELIVERY_FAILURE_EVENT_ID |
419 SOFT_GEMINI_SENSE_EVENT_ID;
421 ret = wl1271_event_unmask(wl);
423 wl1271_error("EVENT mask setting failed");
427 wl1271_event_mbox_config(wl);
429 /* firmware startup completed */
433 static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
437 polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY);
439 /* We use HIGH polarity, so unset the LOW bit */
440 polarity &= ~POLARITY_LOW;
441 wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity);
446 static void wl1271_boot_hw_version(struct wl1271 *wl)
450 fuse = wl1271_top_reg_read(wl, REG_FUSE_DATA_2_1);
451 fuse = (fuse & PG_VER_MASK) >> PG_VER_OFFSET;
453 wl->hw_pg_ver = (s8)fuse;
456 int wl1271_boot(struct wl1271 *wl)
461 wl1271_boot_hw_version(wl);
463 if (REF_CLOCK == 0 || REF_CLOCK == 2 || REF_CLOCK == 4)
464 /* ref clk: 19.2/38.4/38.4-XTAL */
466 else if (REF_CLOCK == 1 || REF_CLOCK == 3)
470 if (REF_CLOCK != 0) {
472 /* Set clock type (open drain) */
473 val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
474 val &= FREF_CLK_TYPE_BITS;
475 wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
477 /* Set clock pull mode (no pull) */
478 val = wl1271_top_reg_read(wl, OCP_REG_CLK_PULL);
480 wl1271_top_reg_write(wl, OCP_REG_CLK_PULL, val);
483 /* Set clock polarity */
484 val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY);
485 val &= FREF_CLK_POLARITY_BITS;
486 val |= CLK_REQ_OUTN_SEL;
487 wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
490 wl1271_write32(wl, PLL_PARAMETERS, clk);
492 pause = wl1271_read32(wl, PLL_PARAMETERS);
494 wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
496 pause &= ~(WU_COUNTER_PAUSE_VAL); /* FIXME: This should probably be
497 * WU_COUNTER_PAUSE_VAL instead of
498 * 0x3ff (magic number ). How does
500 pause |= WU_COUNTER_PAUSE_VAL;
501 wl1271_write32(wl, WU_COUNTER_PAUSE, pause);
503 /* Continue the ELP wake up sequence */
504 wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
507 wl1271_set_partition(wl, &part_table[PART_DRPW]);
509 /* Read-modify-write DRPW_SCRATCH_START register (see next state)
510 to be used by DRPw FW. The RTRIM value will be added by the FW
511 before taking DRPw out of reset */
513 wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
514 clk = wl1271_read32(wl, DRPW_SCRATCH_START);
516 wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
519 clk |= (REF_CLOCK << 1) << 4;
520 wl1271_write32(wl, DRPW_SCRATCH_START, clk);
522 wl1271_set_partition(wl, &part_table[PART_WORK]);
524 /* Disable interrupts */
525 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
527 ret = wl1271_boot_soft_reset(wl);
531 /* 2. start processing NVS file */
532 ret = wl1271_boot_upload_nvs(wl);
536 /* write firmware's last address (ie. it's length) to
537 * ACX_EEPROMLESS_IND_REG */
538 wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
540 wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
542 tmp = wl1271_read32(wl, CHIP_ID_B);
544 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
546 /* 6. read the EEPROM parameters */
547 tmp = wl1271_read32(wl, SCR_PAD2);
549 ret = wl1271_boot_write_irq_polarity(wl);
553 /* FIXME: Need to check whether this is really what we want */
554 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
555 WL1271_ACX_ALL_EVENTS_VECTOR);
557 /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
560 ret = wl1271_boot_upload_firmware(wl);
564 /* 10.5 start firmware */
565 ret = wl1271_boot_run_firmware(wl);
569 /* Enable firmware interrupts now */
570 wl1271_boot_enable_interrupts(wl);
572 /* set the wl1271 default filters */
573 wl->rx_config = WL1271_DEFAULT_RX_CONFIG;
574 wl->rx_filter = WL1271_DEFAULT_RX_FILTER;
576 wl1271_event_mbox_config(wl);