2 * This file is part of wlcore
4 * Copyright (C) 2011 Texas Instruments Inc.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
25 #include <linux/platform_device.h>
31 /* The maximum number of Tx descriptors in all chip families */
32 #define WLCORE_MAX_TX_DESCRIPTORS 32
34 /* forward declaration */
35 struct wl1271_tx_hw_descr;
37 struct wl1271_rx_descriptor;
40 int (*identify_chip)(struct wl1271 *wl);
41 int (*identify_fw)(struct wl1271 *wl);
42 int (*boot)(struct wl1271 *wl);
43 int (*plt_init)(struct wl1271 *wl);
44 void (*trigger_cmd)(struct wl1271 *wl, int cmd_box_addr,
45 void *buf, size_t len);
46 void (*ack_event)(struct wl1271 *wl);
47 u32 (*calc_tx_blocks)(struct wl1271 *wl, u32 len, u32 spare_blks);
48 void (*set_tx_desc_blocks)(struct wl1271 *wl,
49 struct wl1271_tx_hw_descr *desc,
50 u32 blks, u32 spare_blks);
51 void (*set_tx_desc_data_len)(struct wl1271 *wl,
52 struct wl1271_tx_hw_descr *desc,
54 enum wl_rx_buf_align (*get_rx_buf_align)(struct wl1271 *wl,
56 void (*prepare_read)(struct wl1271 *wl, u32 rx_desc, u32 len);
57 u32 (*get_rx_packet_len)(struct wl1271 *wl, void *rx_data,
59 void (*tx_delayed_compl)(struct wl1271 *wl);
60 void (*tx_immediate_compl)(struct wl1271 *wl);
61 int (*hw_init)(struct wl1271 *wl);
62 int (*init_vif)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
63 u32 (*sta_get_ap_rate_mask)(struct wl1271 *wl,
64 struct wl12xx_vif *wlvif);
65 s8 (*get_pg_ver)(struct wl1271 *wl);
66 void (*get_mac)(struct wl1271 *wl);
67 void (*set_tx_desc_csum)(struct wl1271 *wl,
68 struct wl1271_tx_hw_descr *desc,
70 void (*set_rx_csum)(struct wl1271 *wl,
71 struct wl1271_rx_descriptor *desc,
73 u32 (*ap_get_mimo_wide_rate_mask)(struct wl1271 *wl,
74 struct wl12xx_vif *wlvif);
75 int (*debugfs_init)(struct wl1271 *wl, struct dentry *rootdir);
76 int (*handle_static_data)(struct wl1271 *wl,
77 struct wl1271_static_data *static_data);
78 int (*get_spare_blocks)(struct wl1271 *wl, bool is_gem);
81 enum wlcore_partitions {
86 PART_TOP_PRCM_ELP_SOC,
92 struct wlcore_partition {
97 struct wlcore_partition_set {
98 struct wlcore_partition mem;
99 struct wlcore_partition reg;
100 struct wlcore_partition mem2;
101 struct wlcore_partition mem3;
104 enum wlcore_registers {
105 /* register addresses, used with partition translation */
107 REG_INTERRUPT_NO_CLEAR,
109 REG_COMMAND_MAILBOX_PTR,
110 REG_EVENT_MAILBOX_PTR,
115 REG_CMD_MBOX_ADDRESS,
117 /* data access memory addresses, used with partition translation */
121 /* raw data access memory addresses */
122 REG_RAW_FW_STATUS_ADDR,
127 struct wl1271_stats {
129 unsigned long fw_stats_update;
132 unsigned int retry_count;
133 unsigned int excessive_retries;
137 struct ieee80211_hw *hw;
138 bool mac80211_registered;
144 struct wl1271_if_operations *if_ops;
146 void (*set_power)(bool enable);
151 enum wl1271_state state;
152 enum wl12xx_fw_type fw_type;
159 struct wlcore_partition_set curr_part;
161 struct wl1271_chip chip;
172 /* address read from the fuse ROM */
176 /* we have up to 2 MAC addresses */
177 struct mac_address addresses[2];
181 unsigned long links_map[BITS_TO_LONGS(WL12XX_MAX_LINKS)];
182 unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
183 unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
184 unsigned long rate_policies_map[
185 BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)];
187 struct list_head wlvif_list;
192 struct wl1271_acx_mem_map *target_mem_map;
194 /* Accounting for allocated / available TX blocks on HW */
196 u32 tx_blocks_available;
197 u32 tx_allocated_blocks;
198 u32 tx_results_count;
200 /* Accounting for allocated / available Tx packets in HW */
201 u32 tx_pkts_freed[NUM_TX_QUEUES];
202 u32 tx_allocated_pkts[NUM_TX_QUEUES];
204 /* Transmitted TX packets counter for chipset interface */
205 u32 tx_packets_count;
207 /* Time-offset between host and chipset clocks */
210 /* Frames scheduled for transmission, not handled yet */
211 int tx_queue_count[NUM_TX_QUEUES];
212 unsigned long queue_stop_reasons[NUM_TX_QUEUES];
214 /* Frames received, not handled yet by mac80211 */
215 struct sk_buff_head deferred_rx_queue;
217 /* Frames sent, not returned yet to mac80211 */
218 struct sk_buff_head deferred_tx_queue;
220 struct work_struct tx_work;
221 struct workqueue_struct *freezable_wq;
223 /* Pending TX frames */
224 unsigned long tx_frames_map[BITS_TO_LONGS(WLCORE_MAX_TX_DESCRIPTORS)];
225 struct sk_buff *tx_frames[WLCORE_MAX_TX_DESCRIPTORS];
231 /* Intermediate buffer, used for packet aggregation */
234 /* Reusable dummy packet template */
235 struct sk_buff *dummy_packet;
237 /* Network stack work */
238 struct work_struct netstack_work;
243 /* Number of valid bytes in the FW log buffer */
246 /* Sysfs FW log entry readers wait queue */
247 wait_queue_head_t fwlog_waitq;
249 /* Hardware recovery work */
250 struct work_struct recovery_work;
252 /* Pointer that holds DMA-friendly block for the mailbox */
253 struct event_mailbox *mbox;
255 /* The mbox event mask */
258 /* Mailbox pointers */
261 /* Are we currently scanning */
262 struct ieee80211_vif *scan_vif;
263 struct wl1271_scan scan;
264 struct delayed_work scan_complete_work;
266 /* Connection loss work */
267 struct delayed_work connection_loss_work;
271 /* The current band */
272 enum ieee80211_band band;
274 struct completion *elp_compl;
275 struct delayed_work elp_work;
280 struct wl1271_stats stats;
284 u32 buffer_busyword[WL1271_BUSY_WORD_CNT];
286 struct wl_fw_status_1 *fw_status_1;
287 struct wl_fw_status_2 *fw_status_2;
288 struct wl1271_tx_hw_res_if *tx_res_if;
290 /* Current chipset configuration */
291 struct wlcore_conf conf;
297 /* Most recently reported noise in dBm */
300 /* bands supported by this instance of wl12xx */
301 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
304 * wowlan trigger was configured during suspend.
305 * (currently, only "ANY" trigger is supported)
308 bool irq_wake_enabled;
311 * AP-mode - links indexed by HLID. The global and broadcast links
314 struct wl1271_link links[WL12XX_MAX_LINKS];
316 /* AP-mode - a bitmap of links currently in PS mode according to FW */
319 /* AP-mode - a bitmap of links currently in PS mode in mac80211 */
320 unsigned long ap_ps_map;
322 /* Quirks of specific hardware revisions */
325 /* Platform limitations */
326 unsigned int platform_quirks;
328 /* number of currently active RX BA sessions */
329 int ba_rx_session_count;
331 /* AP-mode - number of currently connected stations */
332 int active_sta_count;
334 /* last wlvif we transmitted from */
335 struct wl12xx_vif *last_wlvif;
337 /* work to fire when Tx is stuck */
338 struct delayed_work tx_watchdog_work;
340 struct wlcore_ops *ops;
341 /* pointer to the lower driver partition table */
342 const struct wlcore_partition_set *ptable;
343 /* pointer to the lower driver register table */
345 /* name of the firmwares to load - for PLT, single role, multi-role */
346 const char *plt_fw_name;
347 const char *sr_fw_name;
348 const char *mr_fw_name;
350 /* per-chip-family private structure */
353 /* number of TX descriptors the HW supports. */
355 /* number of RX descriptors the HW supports. */
358 /* translate HW Tx rates to standard rate-indices */
359 const u8 **band_rate_to_idx;
361 /* size of table for HW rates that can be received from chip */
362 u8 hw_tx_rate_tbl_size;
364 /* this HW rate and below are considered HT rates for this chip */
367 /* HW HT (11n) capabilities */
368 struct ieee80211_sta_ht_cap ht_cap[IEEE80211_NUM_BANDS];
370 /* size of the private FW status data */
371 size_t fw_status_priv_len;
373 /* RX Data filter rule state - enabled/disabled */
374 bool rx_filter_enabled[WL1271_MAX_RX_FILTERS];
376 /* size of the private static data */
377 size_t static_data_priv_len;
379 /* the current channel type */
380 enum nl80211_channel_type channel_type;
383 int __devinit wlcore_probe(struct wl1271 *wl, struct platform_device *pdev);
384 int __devexit wlcore_remove(struct platform_device *pdev);
385 struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size);
386 int wlcore_free_hw(struct wl1271 *wl);
388 /* Firmware image load chunk size */
389 #define CHUNK_SIZE 16384
393 /* Each RX/TX transaction requires an end-of-transaction transfer */
394 #define WLCORE_QUIRK_END_OF_TRANSACTION BIT(0)
396 /* wl127x and SPI don't support SDIO block size alignment */
397 #define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN BIT(2)
399 /* means aggregated Rx packets are aligned to a SDIO block */
400 #define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN BIT(3)
402 /* Older firmwares did not implement the FW logger over bus feature */
403 #define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED BIT(4)
405 /* Older firmwares use an old NVS format */
406 #define WLCORE_QUIRK_LEGACY_NVS BIT(5)
408 /* Some firmwares may not support ELP */
409 #define WLCORE_QUIRK_NO_ELP BIT(6)
411 /* extra header space is required for TKIP */
412 #define WLCORE_QUIRK_TKIP_HEADER_SPACE BIT(8)
414 /* TODO: move to the lower drivers when all usages are abstracted */
415 #define CHIP_ID_1271_PG10 (0x4030101)
416 #define CHIP_ID_1271_PG20 (0x4030111)
417 #define CHIP_ID_1283_PG10 (0x05030101)
418 #define CHIP_ID_1283_PG20 (0x05030111)
420 /* TODO: move all these common registers and values elsewhere */
421 #define HW_ACCESS_ELP_CTRL_REG 0x1FFFC
423 /* ELP register commands */
424 #define ELPCTRL_WAKE_UP 0x1
425 #define ELPCTRL_WAKE_UP_WLAN_READY 0x5
426 #define ELPCTRL_SLEEP 0x0
427 /* ELP WLAN_READY bit */
428 #define ELPCTRL_WLAN_READY 0x2
430 /*************************************************************************
432 Interrupt Trigger Register (Host -> WiLink)
434 **************************************************************************/
436 /* Hardware to Embedded CPU Interrupts - first 32-bit register set */
439 * The host sets this bit to inform the Wlan
440 * FW that a TX packet is in the XFER
443 #define INTR_TRIG_TX_PROC0 BIT(2)
446 * The host sets this bit to inform the FW
447 * that it read a packet from RX XFER
450 #define INTR_TRIG_RX_PROC0 BIT(3)
452 #define INTR_TRIG_DEBUG_ACK BIT(4)
454 #define INTR_TRIG_STATE_CHANGED BIT(5)
456 /* Hardware to Embedded CPU Interrupts - second 32-bit register set */
459 * The host sets this bit to inform the FW
460 * that it read a packet from RX XFER
463 #define INTR_TRIG_RX_PROC1 BIT(17)
466 * The host sets this bit to inform the Wlan
467 * hardware that a TX packet is in the XFER
470 #define INTR_TRIG_TX_PROC1 BIT(18)
472 #define ACX_SLV_SOFT_RESET_BIT BIT(1)
473 #define SOFT_RESET_MAX_TIME 1000000
474 #define SOFT_RESET_STALL_TIME 1000
476 #define ECPU_CONTROL_HALT 0x00000101
478 #define WELP_ARM_COMMAND_VAL 0x4
480 #endif /* __WLCORE_H__ */