2 * This file is part of wlcore
4 * Copyright (C) 2011 Texas Instruments Inc.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
25 #include <linux/platform_device.h>
31 /* The maximum number of Tx descriptors in all chip families */
32 #define WLCORE_MAX_TX_DESCRIPTORS 32
35 * We always allocate this number of mac addresses. If we don't
36 * have enough allocated addresses, the LAA bit is used
38 #define WLCORE_NUM_MAC_ADDRESSES 3
40 /* forward declaration */
41 struct wl1271_tx_hw_descr;
43 struct wl1271_rx_descriptor;
46 int (*setup)(struct wl1271 *wl);
47 int (*identify_chip)(struct wl1271 *wl);
48 int (*identify_fw)(struct wl1271 *wl);
49 int (*boot)(struct wl1271 *wl);
50 int (*plt_init)(struct wl1271 *wl);
51 int (*trigger_cmd)(struct wl1271 *wl, int cmd_box_addr,
52 void *buf, size_t len);
53 int (*ack_event)(struct wl1271 *wl);
54 int (*wait_for_event)(struct wl1271 *wl, enum wlcore_wait_event event,
56 int (*process_mailbox_events)(struct wl1271 *wl);
57 u32 (*calc_tx_blocks)(struct wl1271 *wl, u32 len, u32 spare_blks);
58 void (*set_tx_desc_blocks)(struct wl1271 *wl,
59 struct wl1271_tx_hw_descr *desc,
60 u32 blks, u32 spare_blks);
61 void (*set_tx_desc_data_len)(struct wl1271 *wl,
62 struct wl1271_tx_hw_descr *desc,
64 enum wl_rx_buf_align (*get_rx_buf_align)(struct wl1271 *wl,
66 int (*prepare_read)(struct wl1271 *wl, u32 rx_desc, u32 len);
67 u32 (*get_rx_packet_len)(struct wl1271 *wl, void *rx_data,
69 int (*tx_delayed_compl)(struct wl1271 *wl);
70 void (*tx_immediate_compl)(struct wl1271 *wl);
71 int (*hw_init)(struct wl1271 *wl);
72 int (*init_vif)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
73 u32 (*sta_get_ap_rate_mask)(struct wl1271 *wl,
74 struct wl12xx_vif *wlvif);
75 int (*get_pg_ver)(struct wl1271 *wl, s8 *ver);
76 int (*get_mac)(struct wl1271 *wl);
77 void (*set_tx_desc_csum)(struct wl1271 *wl,
78 struct wl1271_tx_hw_descr *desc,
80 void (*set_rx_csum)(struct wl1271 *wl,
81 struct wl1271_rx_descriptor *desc,
83 u32 (*ap_get_mimo_wide_rate_mask)(struct wl1271 *wl,
84 struct wl12xx_vif *wlvif);
85 int (*debugfs_init)(struct wl1271 *wl, struct dentry *rootdir);
86 int (*handle_static_data)(struct wl1271 *wl,
87 struct wl1271_static_data *static_data);
88 int (*scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
89 struct cfg80211_scan_request *req);
90 int (*scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
91 int (*sched_scan_start)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
92 struct cfg80211_sched_scan_request *req,
93 struct ieee80211_sched_scan_ies *ies);
94 void (*sched_scan_stop)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
95 int (*get_spare_blocks)(struct wl1271 *wl, bool is_gem);
96 int (*set_key)(struct wl1271 *wl, enum set_key_cmd cmd,
97 struct ieee80211_vif *vif,
98 struct ieee80211_sta *sta,
99 struct ieee80211_key_conf *key_conf);
100 int (*channel_switch)(struct wl1271 *wl,
101 struct wl12xx_vif *wlvif,
102 struct ieee80211_channel_switch *ch_switch);
103 u32 (*pre_pkt_send)(struct wl1271 *wl, u32 buf_offset, u32 last_len);
104 void (*sta_rc_update)(struct wl1271 *wl, struct wl12xx_vif *wlvif,
105 struct ieee80211_sta *sta, u32 changed);
108 enum wlcore_partitions {
113 PART_TOP_PRCM_ELP_SOC,
119 struct wlcore_partition {
124 struct wlcore_partition_set {
125 struct wlcore_partition mem;
126 struct wlcore_partition reg;
127 struct wlcore_partition mem2;
128 struct wlcore_partition mem3;
131 enum wlcore_registers {
132 /* register addresses, used with partition translation */
134 REG_INTERRUPT_NO_CLEAR,
136 REG_COMMAND_MAILBOX_PTR,
137 REG_EVENT_MAILBOX_PTR,
142 REG_CMD_MBOX_ADDRESS,
144 /* data access memory addresses, used with partition translation */
148 /* raw data access memory addresses */
149 REG_RAW_FW_STATUS_ADDR,
154 struct wl1271_stats {
156 unsigned long fw_stats_update;
159 unsigned int retry_count;
160 unsigned int excessive_retries;
165 struct ieee80211_hw *hw;
166 bool mac80211_registered;
169 struct platform_device *pdev;
173 struct wl1271_if_operations *if_ops;
175 void (*set_power)(bool enable);
180 enum wlcore_state state;
181 enum wl12xx_fw_type fw_type;
183 enum plt_mode plt_mode;
190 struct wlcore_partition_set curr_part;
192 struct wl1271_chip chip;
203 /* address read from the fuse ROM */
207 /* we have up to 2 MAC addresses */
208 struct mac_address addresses[WLCORE_NUM_MAC_ADDRESSES];
212 unsigned long links_map[BITS_TO_LONGS(WL12XX_MAX_LINKS)];
213 unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
214 unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
215 unsigned long rate_policies_map[
216 BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)];
217 unsigned long klv_templates_map[
218 BITS_TO_LONGS(WLCORE_MAX_KLV_TEMPLATES)];
220 u8 session_ids[WL12XX_MAX_LINKS];
222 struct list_head wlvif_list;
227 struct wl1271_acx_mem_map *target_mem_map;
229 /* Accounting for allocated / available TX blocks on HW */
231 u32 tx_blocks_available;
232 u32 tx_allocated_blocks;
233 u32 tx_results_count;
235 /* Accounting for allocated / available Tx packets in HW */
236 u32 tx_pkts_freed[NUM_TX_QUEUES];
237 u32 tx_allocated_pkts[NUM_TX_QUEUES];
239 /* Transmitted TX packets counter for chipset interface */
240 u32 tx_packets_count;
242 /* Time-offset between host and chipset clocks */
245 /* Frames scheduled for transmission, not handled yet */
246 int tx_queue_count[NUM_TX_QUEUES];
247 unsigned long queue_stop_reasons[NUM_TX_QUEUES];
249 /* Frames received, not handled yet by mac80211 */
250 struct sk_buff_head deferred_rx_queue;
252 /* Frames sent, not returned yet to mac80211 */
253 struct sk_buff_head deferred_tx_queue;
255 struct work_struct tx_work;
256 struct workqueue_struct *freezable_wq;
258 /* Pending TX frames */
259 unsigned long tx_frames_map[BITS_TO_LONGS(WLCORE_MAX_TX_DESCRIPTORS)];
260 struct sk_buff *tx_frames[WLCORE_MAX_TX_DESCRIPTORS];
266 /* Intermediate buffer, used for packet aggregation */
270 /* Reusable dummy packet template */
271 struct sk_buff *dummy_packet;
273 /* Network stack work */
274 struct work_struct netstack_work;
279 /* Number of valid bytes in the FW log buffer */
282 /* Sysfs FW log entry readers wait queue */
283 wait_queue_head_t fwlog_waitq;
285 /* Hardware recovery work */
286 struct work_struct recovery_work;
287 bool watchdog_recovery;
289 /* Reg domain last configuration */
290 u32 reg_ch_conf_last[2];
291 /* Reg domain pending configuration */
292 u32 reg_ch_conf_pending[2];
294 /* Pointer that holds DMA-friendly block for the mailbox */
297 /* The mbox event mask */
300 /* Mailbox pointers */
304 /* Are we currently scanning */
305 struct wl12xx_vif *scan_wlvif;
306 struct wl1271_scan scan;
307 struct delayed_work scan_complete_work;
309 struct ieee80211_vif *roc_vif;
310 struct delayed_work roc_complete_work;
312 struct wl12xx_vif *sched_vif;
314 /* The current band */
315 enum ieee80211_band band;
317 struct completion *elp_compl;
318 struct delayed_work elp_work;
323 struct wl1271_stats stats;
327 u32 buffer_busyword[WL1271_BUSY_WORD_CNT];
329 struct wl_fw_status_1 *fw_status_1;
330 struct wl_fw_status_2 *fw_status_2;
331 struct wl1271_tx_hw_res_if *tx_res_if;
333 /* Current chipset configuration */
334 struct wlcore_conf conf;
342 /* Most recently reported noise in dBm */
345 /* bands supported by this instance of wl12xx */
346 struct ieee80211_supported_band bands[WLCORE_NUM_BANDS];
349 * wowlan trigger was configured during suspend.
350 * (currently, only "ANY" trigger is supported)
353 bool irq_wake_enabled;
356 * AP-mode - links indexed by HLID. The global and broadcast links
359 struct wl1271_link links[WL12XX_MAX_LINKS];
361 /* AP-mode - a bitmap of links currently in PS mode according to FW */
364 /* AP-mode - a bitmap of links currently in PS mode in mac80211 */
365 unsigned long ap_ps_map;
367 /* Quirks of specific hardware revisions */
370 /* Platform limitations */
371 unsigned int platform_quirks;
373 /* number of currently active RX BA sessions */
374 int ba_rx_session_count;
376 /* AP-mode - number of currently connected stations */
377 int active_sta_count;
379 /* last wlvif we transmitted from */
380 struct wl12xx_vif *last_wlvif;
382 /* work to fire when Tx is stuck */
383 struct delayed_work tx_watchdog_work;
385 struct wlcore_ops *ops;
386 /* pointer to the lower driver partition table */
387 const struct wlcore_partition_set *ptable;
388 /* pointer to the lower driver register table */
390 /* name of the firmwares to load - for PLT, single role, multi-role */
391 const char *plt_fw_name;
392 const char *sr_fw_name;
393 const char *mr_fw_name;
395 u8 scan_templ_id_2_4;
397 u8 sched_scan_templ_id_2_4;
398 u8 sched_scan_templ_id_5;
401 /* per-chip-family private structure */
404 /* number of TX descriptors the HW supports. */
406 /* number of RX descriptors the HW supports. */
409 /* translate HW Tx rates to standard rate-indices */
410 const u8 **band_rate_to_idx;
412 /* size of table for HW rates that can be received from chip */
413 u8 hw_tx_rate_tbl_size;
415 /* this HW rate and below are considered HT rates for this chip */
418 /* HW HT (11n) capabilities */
419 struct ieee80211_sta_ht_cap ht_cap[WLCORE_NUM_BANDS];
421 /* size of the private FW status data */
422 size_t fw_status_priv_len;
424 /* RX Data filter rule state - enabled/disabled */
425 bool rx_filter_enabled[WL1271_MAX_RX_FILTERS];
427 /* size of the private static data */
428 size_t static_data_priv_len;
430 /* the current channel type */
431 enum nl80211_channel_type channel_type;
433 /* mutex for protecting the tx_flush function */
434 struct mutex flush_mutex;
436 /* sleep auth value currently configured to FW */
439 /* the number of allocated MAC addresses in this chip */
442 /* the minimum FW version required for the driver to work */
443 unsigned int min_fw_ver[NUM_FW_VER];
445 struct completion nvs_loading_complete;
447 /* number of concurrent channels the HW supports */
451 int __devinit wlcore_probe(struct wl1271 *wl, struct platform_device *pdev);
452 int __devexit wlcore_remove(struct platform_device *pdev);
453 struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size, u32 aggr_buf_size,
455 int wlcore_free_hw(struct wl1271 *wl);
456 int wlcore_set_key(struct wl1271 *wl, enum set_key_cmd cmd,
457 struct ieee80211_vif *vif,
458 struct ieee80211_sta *sta,
459 struct ieee80211_key_conf *key_conf);
460 void wlcore_regdomain_config(struct wl1271 *wl);
463 wlcore_set_ht_cap(struct wl1271 *wl, enum ieee80211_band band,
464 struct ieee80211_sta_ht_cap *ht_cap)
466 memcpy(&wl->ht_cap[band], ht_cap, sizeof(*ht_cap));
470 wlcore_set_min_fw_ver(struct wl1271 *wl, unsigned int chip,
471 unsigned int iftype, unsigned int major,
472 unsigned int subtype, unsigned int minor)
474 wl->min_fw_ver[FW_VER_CHIP] = chip;
475 wl->min_fw_ver[FW_VER_IF_TYPE] = iftype;
476 wl->min_fw_ver[FW_VER_MAJOR] = major;
477 wl->min_fw_ver[FW_VER_SUBTYPE] = subtype;
478 wl->min_fw_ver[FW_VER_MINOR] = minor;
481 /* Firmware image load chunk size */
482 #define CHUNK_SIZE 16384
486 /* Each RX/TX transaction requires an end-of-transaction transfer */
487 #define WLCORE_QUIRK_END_OF_TRANSACTION BIT(0)
489 /* the first start_role(sta) sometimes doesn't work on wl12xx */
490 #define WLCORE_QUIRK_START_STA_FAILS BIT(1)
492 /* wl127x and SPI don't support SDIO block size alignment */
493 #define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN BIT(2)
495 /* means aggregated Rx packets are aligned to a SDIO block */
496 #define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN BIT(3)
498 /* Older firmwares did not implement the FW logger over bus feature */
499 #define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED BIT(4)
501 /* Older firmwares use an old NVS format */
502 #define WLCORE_QUIRK_LEGACY_NVS BIT(5)
504 /* Some firmwares may not support ELP */
505 #define WLCORE_QUIRK_NO_ELP BIT(6)
507 /* pad only the last frame in the aggregate buffer */
508 #define WLCORE_QUIRK_TX_PAD_LAST_FRAME BIT(7)
510 /* extra header space is required for TKIP */
511 #define WLCORE_QUIRK_TKIP_HEADER_SPACE BIT(8)
513 /* Some firmwares not support sched scans while connected */
514 #define WLCORE_QUIRK_NO_SCHED_SCAN_WHILE_CONN BIT(9)
516 /* separate probe response templates for one-shot and sched scans */
517 #define WLCORE_QUIRK_DUAL_PROBE_TMPL BIT(10)
519 /* Firmware requires reg domain configuration for active calibration */
520 #define WLCORE_QUIRK_REGDOMAIN_CONF BIT(11)
523 /* TODO: move to the lower drivers when all usages are abstracted */
524 #define CHIP_ID_1271_PG10 (0x4030101)
525 #define CHIP_ID_1271_PG20 (0x4030111)
526 #define CHIP_ID_1283_PG10 (0x05030101)
527 #define CHIP_ID_1283_PG20 (0x05030111)
529 /* TODO: move all these common registers and values elsewhere */
530 #define HW_ACCESS_ELP_CTRL_REG 0x1FFFC
532 /* ELP register commands */
533 #define ELPCTRL_WAKE_UP 0x1
534 #define ELPCTRL_WAKE_UP_WLAN_READY 0x5
535 #define ELPCTRL_SLEEP 0x0
536 /* ELP WLAN_READY bit */
537 #define ELPCTRL_WLAN_READY 0x2
539 /*************************************************************************
541 Interrupt Trigger Register (Host -> WiLink)
543 **************************************************************************/
545 /* Hardware to Embedded CPU Interrupts - first 32-bit register set */
548 * The host sets this bit to inform the Wlan
549 * FW that a TX packet is in the XFER
552 #define INTR_TRIG_TX_PROC0 BIT(2)
555 * The host sets this bit to inform the FW
556 * that it read a packet from RX XFER
559 #define INTR_TRIG_RX_PROC0 BIT(3)
561 #define INTR_TRIG_DEBUG_ACK BIT(4)
563 #define INTR_TRIG_STATE_CHANGED BIT(5)
565 /* Hardware to Embedded CPU Interrupts - second 32-bit register set */
568 * The host sets this bit to inform the FW
569 * that it read a packet from RX XFER
572 #define INTR_TRIG_RX_PROC1 BIT(17)
575 * The host sets this bit to inform the Wlan
576 * hardware that a TX packet is in the XFER
579 #define INTR_TRIG_TX_PROC1 BIT(18)
581 #define ACX_SLV_SOFT_RESET_BIT BIT(1)
582 #define SOFT_RESET_MAX_TIME 1000000
583 #define SOFT_RESET_STALL_TIME 1000
585 #define ECPU_CONTROL_HALT 0x00000101
587 #define WELP_ARM_COMMAND_VAL 0x4
589 #endif /* __WLCORE_H__ */