drivers/net/wireless/ti/wl18xx/main.c

   1 /*
   2  * This file is part of wl18xx
   3  *
   4  * Copyright (C) 2011 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18  * 02110-1301 USA
  19  *
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/ip.h>
  25
  26 #include "../wlcore/wlcore.h"
  27 #include "../wlcore/debug.h"
  28 #include "../wlcore/io.h"
  29 #include "../wlcore/acx.h"
  30 #include "../wlcore/tx.h"
  31 #include "../wlcore/rx.h"
  32 #include "../wlcore/io.h"
  33 #include "../wlcore/boot.h"
  34
  35 #include "reg.h"
  36 #include "conf.h"
  37 #include "acx.h"
  38 #include "tx.h"
  39 #include "wl18xx.h"
  40 #include "io.h"
  41
  42
  43 #define WL18XX_RX_CHECKSUM_MASK      0x40
  44
  45 static char *ht_mode_param;
  46 static char *board_type_param;
  47 static bool dc2dc_param = false;
  48 static int n_antennas_2_param = 1;
  49 static int n_antennas_5_param = 1;
  50 static bool checksum_param = true;
  51 static bool enable_11a_param = true;
  52
  53 static const u8 wl18xx_rate_to_idx_2ghz[] = {
  54         /* MCS rates are used only with 11n */
  55         15,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
  56         14,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
  57         13,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
  58         12,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
  59         11,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
  60         10,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
  61         9,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
  62         8,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
  63         7,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
  64         6,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
  65         5,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
  66         4,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
  67         3,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
  68         2,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
  69         1,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
  70         0,                             /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
  71
  72         11,                            /* WL18XX_CONF_HW_RXTX_RATE_54   */
  73         10,                            /* WL18XX_CONF_HW_RXTX_RATE_48   */
  74         9,                             /* WL18XX_CONF_HW_RXTX_RATE_36   */
  75         8,                             /* WL18XX_CONF_HW_RXTX_RATE_24   */
  76
  77         /* TI-specific rate */
  78         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22   */
  79
  80         7,                             /* WL18XX_CONF_HW_RXTX_RATE_18   */
  81         6,                             /* WL18XX_CONF_HW_RXTX_RATE_12   */
  82         3,                             /* WL18XX_CONF_HW_RXTX_RATE_11   */
  83         5,                             /* WL18XX_CONF_HW_RXTX_RATE_9    */
  84         4,                             /* WL18XX_CONF_HW_RXTX_RATE_6    */
  85         2,                             /* WL18XX_CONF_HW_RXTX_RATE_5_5  */
  86         1,                             /* WL18XX_CONF_HW_RXTX_RATE_2    */
  87         0                              /* WL18XX_CONF_HW_RXTX_RATE_1    */
  88 };
  89
  90 static const u8 wl18xx_rate_to_idx_5ghz[] = {
  91         /* MCS rates are used only with 11n */
  92         15,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
  93         14,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
  94         13,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
  95         12,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
  96         11,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
  97         10,                           /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
  98         9,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
  99         8,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
 100         7,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
 101         6,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
 102         5,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
 103         4,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
 104         3,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
 105         2,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
 106         1,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
 107         0,                            /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
 108
 109         7,                             /* WL18XX_CONF_HW_RXTX_RATE_54   */
 110         6,                             /* WL18XX_CONF_HW_RXTX_RATE_48   */
 111         5,                             /* WL18XX_CONF_HW_RXTX_RATE_36   */
 112         4,                             /* WL18XX_CONF_HW_RXTX_RATE_24   */
 113
 114         /* TI-specific rate */
 115         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22   */
 116
 117         3,                             /* WL18XX_CONF_HW_RXTX_RATE_18   */
 118         2,                             /* WL18XX_CONF_HW_RXTX_RATE_12   */
 119         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_11   */
 120         1,                             /* WL18XX_CONF_HW_RXTX_RATE_9    */
 121         0,                             /* WL18XX_CONF_HW_RXTX_RATE_6    */
 122         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_5_5  */
 123         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_2    */
 124         CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_1    */
 125 };
 126
 127 static const u8 *wl18xx_band_rate_to_idx[] = {
 128         [IEEE80211_BAND_2GHZ] = wl18xx_rate_to_idx_2ghz,
 129         [IEEE80211_BAND_5GHZ] = wl18xx_rate_to_idx_5ghz
 130 };
 131
 132 enum wl18xx_hw_rates {
 133         WL18XX_CONF_HW_RXTX_RATE_MCS15 = 0,
 134         WL18XX_CONF_HW_RXTX_RATE_MCS14,
 135         WL18XX_CONF_HW_RXTX_RATE_MCS13,
 136         WL18XX_CONF_HW_RXTX_RATE_MCS12,
 137         WL18XX_CONF_HW_RXTX_RATE_MCS11,
 138         WL18XX_CONF_HW_RXTX_RATE_MCS10,
 139         WL18XX_CONF_HW_RXTX_RATE_MCS9,
 140         WL18XX_CONF_HW_RXTX_RATE_MCS8,
 141         WL18XX_CONF_HW_RXTX_RATE_MCS7,
 142         WL18XX_CONF_HW_RXTX_RATE_MCS6,
 143         WL18XX_CONF_HW_RXTX_RATE_MCS5,
 144         WL18XX_CONF_HW_RXTX_RATE_MCS4,
 145         WL18XX_CONF_HW_RXTX_RATE_MCS3,
 146         WL18XX_CONF_HW_RXTX_RATE_MCS2,
 147         WL18XX_CONF_HW_RXTX_RATE_MCS1,
 148         WL18XX_CONF_HW_RXTX_RATE_MCS0,
 149         WL18XX_CONF_HW_RXTX_RATE_54,
 150         WL18XX_CONF_HW_RXTX_RATE_48,
 151         WL18XX_CONF_HW_RXTX_RATE_36,
 152         WL18XX_CONF_HW_RXTX_RATE_24,
 153         WL18XX_CONF_HW_RXTX_RATE_22,
 154         WL18XX_CONF_HW_RXTX_RATE_18,
 155         WL18XX_CONF_HW_RXTX_RATE_12,
 156         WL18XX_CONF_HW_RXTX_RATE_11,
 157         WL18XX_CONF_HW_RXTX_RATE_9,
 158         WL18XX_CONF_HW_RXTX_RATE_6,
 159         WL18XX_CONF_HW_RXTX_RATE_5_5,
 160         WL18XX_CONF_HW_RXTX_RATE_2,
 161         WL18XX_CONF_HW_RXTX_RATE_1,
 162         WL18XX_CONF_HW_RXTX_RATE_MAX,
 163 };
 164
 165 static struct wlcore_conf wl18xx_conf = {
 166         .sg = {
 167                 .params = {
 168                         [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
 169                         [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
 170                         [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
 171                         [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
 172                         [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
 173                         [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
 174                         [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
 175                         [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
 176                         [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
 177                         [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
 178                         [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
 179                         [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
 180                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
 181                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
 182                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
 183                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
 184                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
 185                         [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
 186                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
 187                         [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
 188                         [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
 189                         [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
 190                         [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
 191                         [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
 192                         [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
 193                         [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
 194                         /* active scan params */
 195                         [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
 196                         [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
 197                         [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
 198                         /* passive scan params */
 199                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800,
 200                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200,
 201                         [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
 202                         /* passive scan in dual antenna params */
 203                         [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
 204                         [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0,
 205                         [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0,
 206                         /* general params */
 207                         [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
 208                         [CONF_SG_ANTENNA_CONFIGURATION] = 0,
 209                         [CONF_SG_BEACON_MISS_PERCENT] = 60,
 210                         [CONF_SG_DHCP_TIME] = 5000,
 211                         [CONF_SG_RXT] = 1200,
 212                         [CONF_SG_TXT] = 1000,
 213                         [CONF_SG_ADAPTIVE_RXT_TXT] = 1,
 214                         [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
 215                         [CONF_SG_HV3_MAX_SERVED] = 6,
 216                         [CONF_SG_PS_POLL_TIMEOUT] = 10,
 217                         [CONF_SG_UPSD_TIMEOUT] = 10,
 218                         [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
 219                         [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
 220                         [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
 221                         /* AP params */
 222                         [CONF_AP_BEACON_MISS_TX] = 3,
 223                         [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
 224                         [CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
 225                         [CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
 226                         [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
 227                         [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
 228                         /* CTS Diluting params */
 229                         [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
 230                         [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
 231                 },
 232                 .state = CONF_SG_PROTECTIVE,
 233         },
 234         .rx = {
 235                 .rx_msdu_life_time           = 512000,
 236                 .packet_detection_threshold  = 0,
 237                 .ps_poll_timeout             = 15,
 238                 .upsd_timeout                = 15,
 239                 .rts_threshold               = IEEE80211_MAX_RTS_THRESHOLD,
 240                 .rx_cca_threshold            = 0,
 241                 .irq_blk_threshold           = 0xFFFF,
 242                 .irq_pkt_threshold           = 0,
 243                 .irq_timeout                 = 600,
 244                 .queue_type                  = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
 245         },
 246         .tx = {
 247                 .tx_energy_detection         = 0,
 248                 .sta_rc_conf                 = {
 249                         .enabled_rates       = 0,
 250                         .short_retry_limit   = 10,
 251                         .long_retry_limit    = 10,
 252                         .aflags              = 0,
 253                 },
 254                 .ac_conf_count               = 4,
 255                 .ac_conf                     = {
 256                         [CONF_TX_AC_BE] = {
 257                                 .ac          = CONF_TX_AC_BE,
 258                                 .cw_min      = 15,
 259                                 .cw_max      = 63,
 260                                 .aifsn       = 3,
 261                                 .tx_op_limit = 0,
 262                         },
 263                         [CONF_TX_AC_BK] = {
 264                                 .ac          = CONF_TX_AC_BK,
 265                                 .cw_min      = 15,
 266                                 .cw_max      = 63,
 267                                 .aifsn       = 7,
 268                                 .tx_op_limit = 0,
 269                         },
 270                         [CONF_TX_AC_VI] = {
 271                                 .ac          = CONF_TX_AC_VI,
 272                                 .cw_min      = 15,
 273                                 .cw_max      = 63,
 274                                 .aifsn       = CONF_TX_AIFS_PIFS,
 275                                 .tx_op_limit = 3008,
 276                         },
 277                         [CONF_TX_AC_VO] = {
 278                                 .ac          = CONF_TX_AC_VO,
 279                                 .cw_min      = 15,
 280                                 .cw_max      = 63,
 281                                 .aifsn       = CONF_TX_AIFS_PIFS,
 282                                 .tx_op_limit = 1504,
 283                         },
 284                 },
 285                 .max_tx_retries = 100,
 286                 .ap_aging_period = 300,
 287                 .tid_conf_count = 4,
 288                 .tid_conf = {
 289                         [CONF_TX_AC_BE] = {
 290                                 .queue_id    = CONF_TX_AC_BE,
 291                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 292                                 .tsid        = CONF_TX_AC_BE,
 293                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 294                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 295                                 .apsd_conf   = {0, 0},
 296                         },
 297                         [CONF_TX_AC_BK] = {
 298                                 .queue_id    = CONF_TX_AC_BK,
 299                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 300                                 .tsid        = CONF_TX_AC_BK,
 301                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 302                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 303                                 .apsd_conf   = {0, 0},
 304                         },
 305                         [CONF_TX_AC_VI] = {
 306                                 .queue_id    = CONF_TX_AC_VI,
 307                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 308                                 .tsid        = CONF_TX_AC_VI,
 309                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 310                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 311                                 .apsd_conf   = {0, 0},
 312                         },
 313                         [CONF_TX_AC_VO] = {
 314                                 .queue_id    = CONF_TX_AC_VO,
 315                                 .channel_type = CONF_CHANNEL_TYPE_EDCF,
 316                                 .tsid        = CONF_TX_AC_VO,
 317                                 .ps_scheme   = CONF_PS_SCHEME_LEGACY,
 318                                 .ack_policy  = CONF_ACK_POLICY_LEGACY,
 319                                 .apsd_conf   = {0, 0},
 320                         },
 321                 },
 322                 .frag_threshold              = IEEE80211_MAX_FRAG_THRESHOLD,
 323                 .tx_compl_timeout            = 350,
 324                 .tx_compl_threshold          = 10,
 325                 .basic_rate                  = CONF_HW_BIT_RATE_1MBPS,
 326                 .basic_rate_5                = CONF_HW_BIT_RATE_6MBPS,
 327                 .tmpl_short_retry_limit      = 10,
 328                 .tmpl_long_retry_limit       = 10,
 329                 .tx_watchdog_timeout         = 5000,
 330         },
 331         .conn = {
 332                 .wake_up_event               = CONF_WAKE_UP_EVENT_DTIM,
 333                 .listen_interval             = 1,
 334                 .suspend_wake_up_event       = CONF_WAKE_UP_EVENT_N_DTIM,
 335                 .suspend_listen_interval     = 3,
 336                 .bcn_filt_mode               = CONF_BCN_FILT_MODE_ENABLED,
 337                 .bcn_filt_ie_count           = 2,
 338                 .bcn_filt_ie = {
 339                         [0] = {
 340                                 .ie          = WLAN_EID_CHANNEL_SWITCH,
 341                                 .rule        = CONF_BCN_RULE_PASS_ON_APPEARANCE,
 342                         },
 343                         [1] = {
 344                                 .ie          = WLAN_EID_HT_OPERATION,
 345                                 .rule        = CONF_BCN_RULE_PASS_ON_CHANGE,
 346                         },
 347                 },
 348                 .synch_fail_thold            = 10,
 349                 .bss_lose_timeout            = 100,
 350                 .beacon_rx_timeout           = 10000,
 351                 .broadcast_timeout           = 20000,
 352                 .rx_broadcast_in_ps          = 1,
 353                 .ps_poll_threshold           = 10,
 354                 .bet_enable                  = CONF_BET_MODE_ENABLE,
 355                 .bet_max_consecutive         = 50,
 356                 .psm_entry_retries           = 8,
 357                 .psm_exit_retries            = 16,
 358                 .psm_entry_nullfunc_retries  = 3,
 359                 .dynamic_ps_timeout          = 40,
 360                 .forced_ps                   = false,
 361                 .keep_alive_interval         = 55000,
 362                 .max_listen_interval         = 20,
 363         },
 364         .itrim = {
 365                 .enable = false,
 366                 .timeout = 50000,
 367         },
 368         .pm_config = {
 369                 .host_clk_settling_time = 5000,
 370                 .host_fast_wakeup_support = false
 371         },
 372         .roam_trigger = {
 373                 .trigger_pacing               = 1,
 374                 .avg_weight_rssi_beacon       = 20,
 375                 .avg_weight_rssi_data         = 10,
 376                 .avg_weight_snr_beacon        = 20,
 377                 .avg_weight_snr_data          = 10,
 378         },
 379         .scan = {
 380                 .min_dwell_time_active        = 7500,
 381                 .max_dwell_time_active        = 30000,
 382                 .min_dwell_time_passive       = 100000,
 383                 .max_dwell_time_passive       = 100000,
 384                 .num_probe_reqs               = 2,
 385                 .split_scan_timeout           = 50000,
 386         },
 387         .sched_scan = {
 388                 /*
 389                  * Values are in TU/1000 but since sched scan FW command
 390                  * params are in TUs rounding up may occur.
 391                  */
 392                 .base_dwell_time                = 7500,
 393                 .max_dwell_time_delta           = 22500,
 394                 /* based on 250bits per probe @1Mbps */
 395                 .dwell_time_delta_per_probe     = 2000,
 396                 /* based on 250bits per probe @6Mbps (plus a bit more) */
 397                 .dwell_time_delta_per_probe_5   = 350,
 398                 .dwell_time_passive             = 100000,
 399                 .dwell_time_dfs                 = 150000,
 400                 .num_probe_reqs                 = 2,
 401                 .rssi_threshold                 = -90,
 402                 .snr_threshold                  = 0,
 403         },
 404         .ht = {
 405                 .rx_ba_win_size = 10,
 406                 .tx_ba_win_size = 10,
 407                 .inactivity_timeout = 10000,
 408                 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
 409         },
 410         .mem = {
 411                 .num_stations                 = 1,
 412                 .ssid_profiles                = 1,
 413                 .rx_block_num                 = 40,
 414                 .tx_min_block_num             = 40,
 415                 .dynamic_memory               = 1,
 416                 .min_req_tx_blocks            = 45,
 417                 .min_req_rx_blocks            = 22,
 418                 .tx_min                       = 27,
 419         },
 420         .fm_coex = {
 421                 .enable                       = true,
 422                 .swallow_period               = 5,
 423                 .n_divider_fref_set_1         = 0xff,       /* default */
 424                 .n_divider_fref_set_2         = 12,
 425                 .m_divider_fref_set_1         = 148,
 426                 .m_divider_fref_set_2         = 0xffff,     /* default */
 427                 .coex_pll_stabilization_time  = 0xffffffff, /* default */
 428                 .ldo_stabilization_time       = 0xffff,     /* default */
 429                 .fm_disturbed_band_margin     = 0xff,       /* default */
 430                 .swallow_clk_diff             = 0xff,       /* default */
 431         },
 432         .rx_streaming = {
 433                 .duration                      = 150,
 434                 .queues                        = 0x1,
 435                 .interval                      = 20,
 436                 .always                        = 0,
 437         },
 438         .fwlog = {
 439                 .mode                         = WL12XX_FWLOG_ON_DEMAND,
 440                 .mem_blocks                   = 2,
 441                 .severity                     = 0,
 442                 .timestamp                    = WL12XX_FWLOG_TIMESTAMP_DISABLED,
 443                 .output                       = WL12XX_FWLOG_OUTPUT_HOST,
 444                 .threshold                    = 0,
 445         },
 446         .rate = {
 447                 .rate_retry_score = 32000,
 448                 .per_add = 8192,
 449                 .per_th1 = 2048,
 450                 .per_th2 = 4096,
 451                 .max_per = 8100,
 452                 .inverse_curiosity_factor = 5,
 453                 .tx_fail_low_th = 4,
 454                 .tx_fail_high_th = 10,
 455                 .per_alpha_shift = 4,
 456                 .per_add_shift = 13,
 457                 .per_beta1_shift = 10,
 458                 .per_beta2_shift = 8,
 459                 .rate_check_up = 2,
 460                 .rate_check_down = 12,
 461                 .rate_retry_policy = {
 462                         0x00, 0x00, 0x00, 0x00, 0x00,
 463                         0x00, 0x00, 0x00, 0x00, 0x00,
 464                         0x00, 0x00, 0x00,
 465                 },
 466         },
 467         .hangover = {
 468                 .recover_time               = 0,
 469                 .hangover_period            = 20,
 470                 .dynamic_mode               = 1,
 471                 .early_termination_mode     = 1,
 472                 .max_period                 = 20,
 473                 .min_period                 = 1,
 474                 .increase_delta             = 1,
 475                 .decrease_delta             = 2,
 476                 .quiet_time                 = 4,
 477                 .increase_time              = 1,
 478                 .window_size                = 16,
 479         },
 480 };
 481
 482 static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
 483         .phy = {
 484                 .phy_standalone                 = 0x00,
 485                 .primary_clock_setting_time     = 0x05,
 486                 .clock_valid_on_wake_up         = 0x00,
 487                 .secondary_clock_setting_time   = 0x05,
 488                 .rdl                            = 0x01,
 489                 .auto_detect                    = 0x00,
 490                 .dedicated_fem                  = FEM_NONE,
 491                 .low_band_component             = COMPONENT_2_WAY_SWITCH,
 492                 .low_band_component_type        = 0x05,
 493                 .high_band_component            = COMPONENT_2_WAY_SWITCH,
 494                 .high_band_component_type       = 0x09,
 495                 .tcxo_ldo_voltage               = 0x00,
 496                 .xtal_itrim_val                 = 0x04,
 497                 .srf_state                      = 0x00,
 498                 .io_configuration               = 0x01,
 499                 .sdio_configuration             = 0x00,
 500                 .settings                       = 0x00,
 501                 .enable_clpc                    = 0x00,
 502                 .enable_tx_low_pwr_on_siso_rdl  = 0x00,
 503                 .rx_profile                     = 0x00,
 504         },
 505 };
 506
 507 static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = {
 508         [PART_TOP_PRCM_ELP_SOC] = {
 509                 .mem  = { .start = 0x00A02000, .size  = 0x00010000 },
 510                 .reg  = { .start = 0x00807000, .size  = 0x00005000 },
 511                 .mem2 = { .start = 0x00800000, .size  = 0x0000B000 },
 512                 .mem3 = { .start = 0x00000000, .size  = 0x00000000 },
 513         },
 514         [PART_DOWN] = {
 515                 .mem  = { .start = 0x00000000, .size  = 0x00014000 },
 516                 .reg  = { .start = 0x00810000, .size  = 0x0000BFFF },
 517                 .mem2 = { .start = 0x00000000, .size  = 0x00000000 },
 518                 .mem3 = { .start = 0x00000000, .size  = 0x00000000 },
 519         },
 520         [PART_BOOT] = {
 521                 .mem  = { .start = 0x00700000, .size = 0x0000030c },
 522                 .reg  = { .start = 0x00802000, .size = 0x00014578 },
 523                 .mem2 = { .start = 0x00B00404, .size = 0x00001000 },
 524                 .mem3 = { .start = 0x00C00000, .size = 0x00000400 },
 525         },
 526         [PART_WORK] = {
 527                 .mem  = { .start = 0x00800000, .size  = 0x000050FC },
 528                 .reg  = { .start = 0x00B00404, .size  = 0x00001000 },
 529                 .mem2 = { .start = 0x00C00000, .size  = 0x00000400 },
 530                 .mem3 = { .start = 0x00000000, .size  = 0x00000000 },
 531         },
 532         [PART_PHY_INIT] = {
 533                 /* TODO: use the phy_conf struct size here */
 534                 .mem  = { .start = 0x80926000, .size = 252 },
 535                 .reg  = { .start = 0x00000000, .size = 0x00000000 },
 536                 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
 537                 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
 538         },
 539 };
 540
 541 static const int wl18xx_rtable[REG_TABLE_LEN] = {
 542         [REG_ECPU_CONTROL]              = WL18XX_REG_ECPU_CONTROL,
 543         [REG_INTERRUPT_NO_CLEAR]        = WL18XX_REG_INTERRUPT_NO_CLEAR,
 544         [REG_INTERRUPT_ACK]             = WL18XX_REG_INTERRUPT_ACK,
 545         [REG_COMMAND_MAILBOX_PTR]       = WL18XX_REG_COMMAND_MAILBOX_PTR,
 546         [REG_EVENT_MAILBOX_PTR]         = WL18XX_REG_EVENT_MAILBOX_PTR,
 547         [REG_INTERRUPT_TRIG]            = WL18XX_REG_INTERRUPT_TRIG_H,
 548         [REG_INTERRUPT_MASK]            = WL18XX_REG_INTERRUPT_MASK,
 549         [REG_PC_ON_RECOVERY]            = WL18XX_SCR_PAD4,
 550         [REG_CHIP_ID_B]                 = WL18XX_REG_CHIP_ID_B,
 551         [REG_CMD_MBOX_ADDRESS]          = WL18XX_CMD_MBOX_ADDRESS,
 552
 553         /* data access memory addresses, used with partition translation */
 554         [REG_SLV_MEM_DATA]              = WL18XX_SLV_MEM_DATA,
 555         [REG_SLV_REG_DATA]              = WL18XX_SLV_REG_DATA,
 556
 557         /* raw data access memory addresses */
 558         [REG_RAW_FW_STATUS_ADDR]        = WL18XX_FW_STATUS_ADDR,
 559 };
 560
 561 static const struct wl18xx_clk_cfg wl18xx_clk_table[NUM_CLOCK_CONFIGS] = {
 562         [CLOCK_CONFIG_16_2_M]   = { 7,  104,  801, 4,  true },
 563         [CLOCK_CONFIG_16_368_M] = { 9,  132, 3751, 4,  true },
 564         [CLOCK_CONFIG_16_8_M]   = { 7,  100,    0, 0, false },
 565         [CLOCK_CONFIG_19_2_M]   = { 8,  100,    0, 0, false },
 566         [CLOCK_CONFIG_26_M]     = { 13, 120,    0, 0, false },
 567         [CLOCK_CONFIG_32_736_M] = { 9,  132, 3751, 4,  true },
 568         [CLOCK_CONFIG_33_6_M]   = { 7,  100,    0, 0, false },
 569         [CLOCK_CONFIG_38_468_M] = { 8,  100,    0, 0, false },
 570         [CLOCK_CONFIG_52_M]     = { 13, 120,    0, 0, false },
 571 };
 572
 573 /* TODO: maybe move to a new header file? */
 574 #define WL18XX_FW_NAME "ti-connectivity/wl18xx-fw.bin"
 575
 576 static int wl18xx_identify_chip(struct wl1271 *wl)
 577 {
 578         int ret = 0;
 579
 580         switch (wl->chip.id) {
 581         case CHIP_ID_185x_PG10:
 582                 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG10)",
 583                              wl->chip.id);
 584                 wl->sr_fw_name = WL18XX_FW_NAME;
 585                 /* wl18xx uses the same firmware for PLT */
 586                 wl->plt_fw_name = WL18XX_FW_NAME;
 587                 wl->quirks |= WLCORE_QUIRK_NO_ELP |
 588                               WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED |
 589                               WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN;
 590
 591                 /* TODO: need to blocksize alignment for RX/TX separately? */
 592                 break;
 593         default:
 594                 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
 595                 ret = -ENODEV;
 596                 goto out;
 597         }
 598
 599 out:
 600         return ret;
 601 }
 602
 603 static void wl18xx_set_clk(struct wl1271 *wl)
 604 {
 605         u32 clk_freq;
 606
 607         wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
 608
 609         /* TODO: PG2: apparently we need to read the clk type */
 610
 611         clk_freq = wl18xx_top_reg_read(wl, PRIMARY_CLK_DETECT);
 612         wl1271_debug(DEBUG_BOOT, "clock freq %d (%d, %d, %d, %d, %s)", clk_freq,
 613                      wl18xx_clk_table[clk_freq].n, wl18xx_clk_table[clk_freq].m,
 614                      wl18xx_clk_table[clk_freq].p, wl18xx_clk_table[clk_freq].q,
 615                      wl18xx_clk_table[clk_freq].swallow ? "swallow" : "spit");
 616
 617         wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_N, wl18xx_clk_table[clk_freq].n);
 618         wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_M, wl18xx_clk_table[clk_freq].m);
 619
 620         if (wl18xx_clk_table[clk_freq].swallow) {
 621                 /* first the 16 lower bits */
 622                 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_1,
 623                                      wl18xx_clk_table[clk_freq].q &
 624                                      PLLSH_WCS_PLL_Q_FACTOR_CFG_1_MASK);
 625                 /* then the 16 higher bits, masked out */
 626                 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_Q_FACTOR_CFG_2,
 627                                      (wl18xx_clk_table[clk_freq].q >> 16) &
 628                                      PLLSH_WCS_PLL_Q_FACTOR_CFG_2_MASK);
 629
 630                 /* first the 16 lower bits */
 631                 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_1,
 632                                      wl18xx_clk_table[clk_freq].p &
 633                                      PLLSH_WCS_PLL_P_FACTOR_CFG_1_MASK);
 634                 /* then the 16 higher bits, masked out */
 635                 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_P_FACTOR_CFG_2,
 636                                      (wl18xx_clk_table[clk_freq].p >> 16) &
 637                                      PLLSH_WCS_PLL_P_FACTOR_CFG_2_MASK);
 638         } else {
 639                 wl18xx_top_reg_write(wl, PLLSH_WCS_PLL_SWALLOW_EN,
 640                                      PLLSH_WCS_PLL_SWALLOW_EN_VAL2);
 641         }
 642 }
 643
 644 static void wl18xx_boot_soft_reset(struct wl1271 *wl)
 645 {
 646         /* disable Rx/Tx */
 647         wl1271_write32(wl, WL18XX_ENABLE, 0x0);
 648
 649         /* disable auto calibration on start*/
 650         wl1271_write32(wl, WL18XX_SPARE_A2, 0xffff);
 651 }
 652
 653 static int wl18xx_pre_boot(struct wl1271 *wl)
 654 {
 655         wl18xx_set_clk(wl);
 656
 657         /* Continue the ELP wake up sequence */
 658         wl1271_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
 659         udelay(500);
 660
 661         wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
 662
 663         /* Disable interrupts */
 664         wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
 665
 666         wl18xx_boot_soft_reset(wl);
 667
 668         return 0;
 669 }
 670
 671 static void wl18xx_pre_upload(struct wl1271 *wl)
 672 {
 673         u32 tmp;
 674
 675         wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
 676
 677         /* TODO: check if this is all needed */
 678         wl1271_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND);
 679
 680         tmp = wlcore_read_reg(wl, REG_CHIP_ID_B);
 681
 682         wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
 683
 684         tmp = wl1271_read32(wl, WL18XX_SCR_PAD2);
 685 }
 686
 687 static void wl18xx_set_mac_and_phy(struct wl1271 *wl)
 688 {
 689         struct wl18xx_priv *priv = wl->priv;
 690         struct wl18xx_conf_phy *phy = &priv->conf.phy;
 691         struct wl18xx_mac_and_phy_params params;
 692
 693         memset(&params, 0, sizeof(params));
 694
 695         params.phy_standalone = phy->phy_standalone;
 696         params.rdl = phy->rdl;
 697         params.enable_clpc = phy->enable_clpc;
 698         params.enable_tx_low_pwr_on_siso_rdl =
 699                 phy->enable_tx_low_pwr_on_siso_rdl;
 700         params.auto_detect = phy->auto_detect;
 701         params.dedicated_fem = phy->dedicated_fem;
 702         params.low_band_component = phy->low_band_component;
 703         params.low_band_component_type =
 704                 phy->low_band_component_type;
 705         params.high_band_component = phy->high_band_component;
 706         params.high_band_component_type =
 707                 phy->high_band_component_type;
 708         params.number_of_assembled_ant2_4 =
 709                 n_antennas_2_param;
 710         params.number_of_assembled_ant5 =
 711                 n_antennas_5_param;
 712         params.external_pa_dc2dc = dc2dc_param;
 713         params.tcxo_ldo_voltage = phy->tcxo_ldo_voltage;
 714         params.xtal_itrim_val = phy->xtal_itrim_val;
 715         params.srf_state = phy->srf_state;
 716         params.io_configuration = phy->io_configuration;
 717         params.sdio_configuration = phy->sdio_configuration;
 718         params.settings = phy->settings;
 719         params.rx_profile = phy->rx_profile;
 720         params.primary_clock_setting_time =
 721                 phy->primary_clock_setting_time;
 722         params.clock_valid_on_wake_up =
 723                 phy->clock_valid_on_wake_up;
 724         params.secondary_clock_setting_time =
 725                 phy->secondary_clock_setting_time;
 726
 727         params.board_type = priv->board_type;
 728
 729         wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
 730         wl1271_write(wl, WL18XX_PHY_INIT_MEM_ADDR, (u8 *)&params,
 731                      sizeof(params), false);
 732 }
 733
 734 static void wl18xx_enable_interrupts(struct wl1271 *wl)
 735 {
 736         wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_ALL_EVENTS_VECTOR);
 737
 738         wlcore_enable_interrupts(wl);
 739         wlcore_write_reg(wl, REG_INTERRUPT_MASK,
 740                          WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
 741 }
 742
 743 static int wl18xx_boot(struct wl1271 *wl)
 744 {
 745         int ret;
 746
 747         ret = wl18xx_pre_boot(wl);
 748         if (ret < 0)
 749                 goto out;
 750
 751         wl18xx_pre_upload(wl);
 752
 753         ret = wlcore_boot_upload_firmware(wl);
 754         if (ret < 0)
 755                 goto out;
 756
 757         wl18xx_set_mac_and_phy(wl);
 758
 759         ret = wlcore_boot_run_firmware(wl);
 760         if (ret < 0)
 761                 goto out;
 762
 763         wl18xx_enable_interrupts(wl);
 764
 765 out:
 766         return ret;
 767 }
 768
 769 static void wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
 770                                void *buf, size_t len)
 771 {
 772         struct wl18xx_priv *priv = wl->priv;
 773
 774         memcpy(priv->cmd_buf, buf, len);
 775         memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len);
 776
 777         wl1271_write(wl, cmd_box_addr, priv->cmd_buf, WL18XX_CMD_MAX_SIZE,
 778                      false);
 779 }
 780
 781 static void wl18xx_ack_event(struct wl1271 *wl)
 782 {
 783         wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL18XX_INTR_TRIG_EVENT_ACK);
 784 }
 785
 786 static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
 787 {
 788         u32 blk_size = WL18XX_TX_HW_BLOCK_SIZE;
 789         return (len + blk_size - 1) / blk_size + spare_blks;
 790 }
 791
 792 static void
 793 wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
 794                           u32 blks, u32 spare_blks)
 795 {
 796         desc->wl18xx_mem.total_mem_blocks = blks;
 797         desc->wl18xx_mem.reserved = 0;
 798 }
 799
 800 static void
 801 wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
 802                             struct sk_buff *skb)
 803 {
 804         desc->length = cpu_to_le16(skb->len);
 805
 806         wl1271_debug(DEBUG_TX, "tx_fill_hdr: hlid: %d "
 807                      "len: %d life: %d mem: %d", desc->hlid,
 808                      le16_to_cpu(desc->length),
 809                      le16_to_cpu(desc->life_time),
 810                      desc->wl18xx_mem.total_mem_blocks);
 811 }
 812
 813 static enum wl_rx_buf_align
 814 wl18xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
 815 {
 816         if (rx_desc & RX_BUF_PADDED_PAYLOAD)
 817                 return WLCORE_RX_BUF_PADDED;
 818
 819         return WLCORE_RX_BUF_ALIGNED;
 820 }
 821
 822 static u32 wl18xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
 823                                     u32 data_len)
 824 {
 825         struct wl1271_rx_descriptor *desc = rx_data;
 826
 827         /* invalid packet */
 828         if (data_len < sizeof(*desc))
 829                 return 0;
 830
 831         return data_len - sizeof(*desc);
 832 }
 833
 834 static void wl18xx_tx_immediate_completion(struct wl1271 *wl)
 835 {
 836         wl18xx_tx_immediate_complete(wl);
 837 }
 838
 839 static int wl18xx_hw_init(struct wl1271 *wl)
 840 {
 841         int ret;
 842         struct wl18xx_priv *priv = wl->priv;
 843         u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE |
 844                 HOST_IF_CFG_ADD_RX_ALIGNMENT;
 845
 846         u32 sdio_align_size = 0;
 847
 848         /* (re)init private structures. Relevant on recovery as well. */
 849         priv->last_fw_rls_idx = 0;
 850
 851         /* Enable Tx SDIO padding */
 852         if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) {
 853                 host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
 854                 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
 855         }
 856
 857         /* Enable Rx SDIO padding */
 858         if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) {
 859                 host_cfg_bitmap |= HOST_IF_CFG_RX_PAD_TO_SDIO_BLK;
 860                 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
 861         }
 862
 863         ret = wl18xx_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap,
 864                                             sdio_align_size,
 865                                             WL18XX_TX_HW_BLOCK_SPARE,
 866                                             WL18XX_HOST_IF_LEN_SIZE_FIELD);
 867         if (ret < 0)
 868                 return ret;
 869
 870         if (checksum_param) {
 871                 ret = wl18xx_acx_set_checksum_state(wl);
 872                 if (ret != 0)
 873                         return ret;
 874         }
 875
 876         return ret;
 877 }
 878
 879 static void wl18xx_set_tx_desc_csum(struct wl1271 *wl,
 880                                     struct wl1271_tx_hw_descr *desc,
 881                                     struct sk_buff *skb)
 882 {
 883         u32 ip_hdr_offset;
 884         struct iphdr *ip_hdr;
 885
 886         if (!checksum_param) {
 887                 desc->wl18xx_checksum_data = 0;
 888                 return;
 889         }
 890
 891         if (skb->ip_summed != CHECKSUM_PARTIAL) {
 892                 desc->wl18xx_checksum_data = 0;
 893                 return;
 894         }
 895
 896         ip_hdr_offset = skb_network_header(skb) - skb_mac_header(skb);
 897         if (WARN_ON(ip_hdr_offset >= (1<<7))) {
 898                 desc->wl18xx_checksum_data = 0;
 899                 return;
 900         }
 901
 902         desc->wl18xx_checksum_data = ip_hdr_offset << 1;
 903
 904         /* FW is interested only in the LSB of the protocol  TCP=0 UDP=1 */
 905         ip_hdr = (void *)skb_network_header(skb);
 906         desc->wl18xx_checksum_data |= (ip_hdr->protocol & 0x01);
 907 }
 908
 909 static void wl18xx_set_rx_csum(struct wl1271 *wl,
 910                                struct wl1271_rx_descriptor *desc,
 911                                struct sk_buff *skb)
 912 {
 913         if (desc->status & WL18XX_RX_CHECKSUM_MASK)
 914                 skb->ip_summed = CHECKSUM_UNNECESSARY;
 915 }
 916
 917 static u32 wl18xx_sta_get_ap_rate_mask(struct wl1271 *wl,
 918                                        struct wl12xx_vif *wlvif)
 919 {
 920         u32 hw_rate_set = wlvif->rate_set;
 921
 922         if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
 923             wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
 924                 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
 925                 hw_rate_set |= CONF_TX_RATE_USE_WIDE_CHAN;
 926
 927                 /* we don't support MIMO in wide-channel mode */
 928                 hw_rate_set &= ~CONF_TX_MIMO_RATES;
 929         }
 930
 931         return hw_rate_set;
 932 }
 933
 934 static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl,
 935                                              struct wl12xx_vif *wlvif)
 936 {
 937         if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
 938             wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
 939                 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
 940                 return CONF_TX_RATE_USE_WIDE_CHAN;
 941         } else {
 942                 wl1271_debug(DEBUG_ACX, "using MIMO rate mask");
 943                 return CONF_TX_MIMO_RATES;
 944         }
 945 }
 946
 947 static s8 wl18xx_get_pg_ver(struct wl1271 *wl)
 948 {
 949         u32 fuse;
 950
 951         wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
 952
 953         fuse = wl1271_read32(wl, WL18XX_REG_FUSE_DATA_1_3);
 954         fuse = (fuse & WL18XX_PG_VER_MASK) >> WL18XX_PG_VER_OFFSET;
 955
 956         wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
 957
 958         return (s8)fuse;
 959 }
 960
 961 static void wl18xx_conf_init(struct wl1271 *wl)
 962 {
 963         struct wl18xx_priv *priv = wl->priv;
 964
 965         /* apply driver default configuration */
 966         memcpy(&wl->conf, &wl18xx_conf, sizeof(wl18xx_conf));
 967
 968         /* apply default private configuration */
 969         memcpy(&priv->conf, &wl18xx_default_priv_conf, sizeof(priv->conf));
 970 }
 971
 972 static int wl18xx_plt_init(struct wl1271 *wl)
 973 {
 974         wl1271_write32(wl, WL18XX_SCR_PAD8, WL18XX_SCR_PAD8_PLT);
 975
 976         return wl->ops->boot(wl);
 977 }
 978
 979 static void wl18xx_get_mac(struct wl1271 *wl)
 980 {
 981         u32 mac1, mac2;
 982
 983         wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
 984
 985         mac1 = wl1271_read32(wl, WL18XX_REG_FUSE_BD_ADDR_1);
 986         mac2 = wl1271_read32(wl, WL18XX_REG_FUSE_BD_ADDR_2);
 987
 988         /* these are the two parts of the BD_ADDR */
 989         wl->fuse_oui_addr = ((mac2 & 0xffff) << 8) +
 990                 ((mac1 & 0xff000000) >> 24);
 991         wl->fuse_nic_addr = (mac1 & 0xffffff);
 992
 993         wlcore_set_partition(wl, &wl->ptable[PART_DOWN]);
 994 }
 995
 996 static struct wlcore_ops wl18xx_ops = {
 997         .identify_chip  = wl18xx_identify_chip,
 998         .boot           = wl18xx_boot,
 999         .plt_init       = wl18xx_plt_init,
1000         .trigger_cmd    = wl18xx_trigger_cmd,
1001         .ack_event      = wl18xx_ack_event,
1002         .calc_tx_blocks = wl18xx_calc_tx_blocks,
1003         .set_tx_desc_blocks = wl18xx_set_tx_desc_blocks,
1004         .set_tx_desc_data_len = wl18xx_set_tx_desc_data_len,
1005         .get_rx_buf_align = wl18xx_get_rx_buf_align,
1006         .get_rx_packet_len = wl18xx_get_rx_packet_len,
1007         .tx_immediate_compl = wl18xx_tx_immediate_completion,
1008         .tx_delayed_compl = NULL,
1009         .hw_init        = wl18xx_hw_init,
1010         .set_tx_desc_csum = wl18xx_set_tx_desc_csum,
1011         .get_pg_ver     = wl18xx_get_pg_ver,
1012         .set_rx_csum = wl18xx_set_rx_csum,
1013         .sta_get_ap_rate_mask = wl18xx_sta_get_ap_rate_mask,
1014         .ap_get_mimo_wide_rate_mask = wl18xx_ap_get_mimo_wide_rate_mask,
1015         .get_mac        = wl18xx_get_mac,
1016 };
1017
1018 /* HT cap appropriate for wide channels */
1019 static struct ieee80211_sta_ht_cap wl18xx_ht_cap = {
1020         .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
1021                IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_DSSSCCK40,
1022         .ht_supported = true,
1023         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1024         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1025         .mcs = {
1026                 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
1027                 .rx_highest = cpu_to_le16(150),
1028                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1029                 },
1030 };
1031
1032 /* HT cap appropriate for MIMO rates in 20mhz channel */
1033 static struct ieee80211_sta_ht_cap wl18xx_mimo_ht_cap = {
1034         .cap = IEEE80211_HT_CAP_SGI_20,
1035         .ht_supported = true,
1036         .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
1037         .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
1038         .mcs = {
1039                 .rx_mask = { 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, },
1040                 .rx_highest = cpu_to_le16(144),
1041                 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
1042                 },
1043 };
1044
1045 int __devinit wl18xx_probe(struct platform_device *pdev)
1046 {
1047         struct wl1271 *wl;
1048         struct ieee80211_hw *hw;
1049         struct wl18xx_priv *priv;
1050
1051         hw = wlcore_alloc_hw(sizeof(*priv));
1052         if (IS_ERR(hw)) {
1053                 wl1271_error("can't allocate hw");
1054                 return PTR_ERR(hw);
1055         }
1056
1057         wl = hw->priv;
1058         priv = wl->priv;
1059         wl->ops = &wl18xx_ops;
1060         wl->ptable = wl18xx_ptable;
1061         wl->rtable = wl18xx_rtable;
1062         wl->num_tx_desc = 32;
1063         wl->num_rx_desc = 16;
1064         wl->normal_tx_spare = WL18XX_TX_HW_BLOCK_SPARE;
1065         wl->gem_tx_spare = WL18XX_TX_HW_GEM_BLOCK_SPARE;
1066         wl->band_rate_to_idx = wl18xx_band_rate_to_idx;
1067         wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX;
1068         wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0;
1069         wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv);
1070         memcpy(&wl->ht_cap, &wl18xx_ht_cap, sizeof(wl18xx_ht_cap));
1071         if (ht_mode_param && !strcmp(ht_mode_param, "mimo"))
1072                 memcpy(&wl->ht_cap, &wl18xx_mimo_ht_cap,
1073                        sizeof(wl18xx_mimo_ht_cap));
1074
1075         wl18xx_conf_init(wl);
1076
1077         if (!board_type_param) {
1078                 board_type_param = kstrdup("dvp", GFP_KERNEL);
1079                 priv->board_type = BOARD_TYPE_DVP_18XX;
1080         } else if (!strcmp(board_type_param, "fpga")) {
1081                 priv->board_type = BOARD_TYPE_FPGA_18XX;
1082         } else if (!strcmp(board_type_param, "hdk")) {
1083                 priv->board_type = BOARD_TYPE_HDK_18XX;
1084                 /* HACK! Just for now we hardcode HDK to 0x06 */
1085                 priv->conf.phy.low_band_component_type = 0x06;
1086         } else if (!strcmp(board_type_param, "dvp")) {
1087                 priv->board_type = BOARD_TYPE_DVP_18XX;
1088         } else if (!strcmp(board_type_param, "evb")) {
1089                 priv->board_type = BOARD_TYPE_EVB_18XX;
1090         } else if (!strcmp(board_type_param, "com8")) {
1091                 priv->board_type = BOARD_TYPE_COM8_18XX;
1092         } else {
1093                 wl1271_error("invalid board type '%s'", board_type_param);
1094                 wlcore_free_hw(wl);
1095                 return -EINVAL;
1096         }
1097
1098         if (!checksum_param) {
1099                 wl18xx_ops.set_rx_csum = NULL;
1100                 wl18xx_ops.init_vif = NULL;
1101         }
1102
1103         wl->enable_11a = enable_11a_param;
1104
1105         return wlcore_probe(wl, pdev);
1106 }
1107
1108 static const struct platform_device_id wl18xx_id_table[] __devinitconst = {
1109         { "wl18xx", 0 },
1110         {  } /* Terminating Entry */
1111 };
1112 MODULE_DEVICE_TABLE(platform, wl18xx_id_table);
1113
1114 static struct platform_driver wl18xx_driver = {
1115         .probe          = wl18xx_probe,
1116         .remove         = __devexit_p(wlcore_remove),
1117         .id_table       = wl18xx_id_table,
1118         .driver = {
1119                 .name   = "wl18xx_driver",
1120                 .owner  = THIS_MODULE,
1121         }
1122 };
1123
1124 static int __init wl18xx_init(void)
1125 {
1126         return platform_driver_register(&wl18xx_driver);
1127 }
1128 module_init(wl18xx_init);
1129
1130 static void __exit wl18xx_exit(void)
1131 {
1132         platform_driver_unregister(&wl18xx_driver);
1133 }
1134 module_exit(wl18xx_exit);
1135
1136 module_param_named(ht_mode, ht_mode_param, charp, S_IRUSR);
1137 MODULE_PARM_DESC(ht_mode, "Force HT mode: wide or mimo");
1138
1139 module_param_named(board_type, board_type_param, charp, S_IRUSR);
1140 MODULE_PARM_DESC(board_type, "Board type: fpga, hdk, evb, com8 or "
1141                  "dvp (default)");
1142
1143 module_param_named(dc2dc, dc2dc_param, bool, S_IRUSR);
1144 MODULE_PARM_DESC(dc2dc, "External DC2DC: boolean (defaults to false)");
1145
1146 module_param_named(n_antennas_2, n_antennas_2_param, uint, S_IRUSR);
1147 MODULE_PARM_DESC(n_antennas_2, "Number of installed 2.4GHz antennas: 1 (default) or 2");
1148
1149 module_param_named(n_antennas_5, n_antennas_5_param, uint, S_IRUSR);
1150 MODULE_PARM_DESC(n_antennas_5, "Number of installed 5GHz antennas: 1 (default) or 2");
1151
1152 module_param_named(checksum, checksum_param, bool, S_IRUSR);
1153 MODULE_PARM_DESC(checksum, "Enable TCP checksum: boolean (defaults to true)");
1154
1155 module_param_named(enable_11a, enable_11a_param, bool, S_IRUSR);
1156 MODULE_PARM_DESC(enable_11a, "Enable 11a (5GHz): boolean (defaults to true)");
1157
1158 MODULE_LICENSE("GPL v2");
1159 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
1160 MODULE_FIRMWARE(WL18XX_FW_NAME);